JPH06267282A - Flash ROM writing circuit for automobile control device - Google Patents

Abstract

(57) [Summary] [Structure] A write voltage monitor circuit is provided in the write target device to eliminate the uncertainty of write information due to an abnormal write voltage (writing is not sufficient and the write value changes). Further, by providing a monitor circuit for checking whether the writing target device is operating normally, it is possible to prevent the writing target device from erroneously writing due to runaway. [Effect] It is possible to monitor the write voltage by the write target device and eliminate the uncertainty of the write information due to an abnormal write voltage (writing is not sufficient and the write value changes). Further, by monitoring whether the written device is operating normally, it is possible to prevent the written device from writing by mistake due to runaway.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a writing circuit using a FROM as a memory of an automobile control device.

[0002]

2. Description of the Related Art EPROMs (read-only memories that can be erased and electrically written by ultraviolet rays) or mask ROMs (read-only memories that cannot be rewritten) have been used as conventional techniques.

[0003]

In the above-mentioned prior art, it was impossible to electrically erase. In addition, it was impossible to write in the state of being assembled in the device.

Further, in the rewriting of the FROM, there is a risk of runaway if erroneous erasing or erroneous rewriting, because the rewriting is performed after erasing the program or data of its own at once.

[0005]

In this embodiment, writing can be performed in a state where it is incorporated in the device, and in order to prevent runaway due to erroneous writing, writing can be surely performed by monitoring the writing voltage, and writing is performed. Monitor whether the writing device is operating normally, and if it is not writing, do not write.

[0006]

The reason why the write voltage is monitored by the write target device is to eliminate the uncertainty of the write information (the write value is changed and the write value is changed) due to the write voltage abnormality. Further, the reason why the written device is operating normally is to prevent the written device from writing by mistake due to runaway.

[0007]

EXAMPLE An example of the present invention will be described below. FIG. 1 shows an embodiment of claims 1 and 2.

Reference numeral 1 is a microcomputer (hereinafter referred to as CPU) of the control device. 2 is a FROM. 1 and 2 are connected by 7 address buses and 8 data buses. Reference numeral 3 is a write enable circuit A. Control signal from CPU 13,
14 is input. The control signal 13 is normally HIGH,
The write operation is set to LOW, and the control signal 14 is set to normal operation LOW and write operation HIGH. From 3, the voltage switching signal 11 and the rewrite permission signal 18 are output. Signal 11
Is input to the voltage switching circuit 4 to switch between the rewriting power source 5 and the VCC (logic power source). The output voltage is input to the VPP terminal of the FROM. Signal 18 is
It becomes a write enable signal to the 2nd FROM. 12 and 10
Is a monitor input of the writing power source, and the voltage is monitored by the A / D converter. An external comparator may be provided and compared with the comparison voltage to be converted into a logic level and then taken into the CPU. Also, only 12 of the two signals may be used. 6 is
This is an example of connecting to the CPU, which indicates a writing device, by SCI (serial communication interface), but there is no problem with other information transmitting means.

FIG. 2 is a detailed circuit example of the write enable circuit A. When 13 and 14 are in a high impedance state at reset, RA and RB are pulled up and pulled down so that the write enable circuit does not erroneously output. In addition, it is set so as not to enter the write mode.

FIG. 3 shows an embodiment of claims 1 and 3. 1
The input signal 15 of the write enable circuit B of No. 6 is an alternating signal. In FIG. 16, the RESET2 signal becomes the reset signal of the detailed circuit of 16 shown in FIG. RESET1 is a LOW active signal from the CPU. RESET0 is a system reset signal of the control device and is a LOW active signal. The counter 1 and the flip-flop F / F1 in the detailed circuit of FIG. 4 are abnormality detection circuits when the frequency of the alternating voltage signal of 15 is high. Counter 2, flip-flop F
/ F2 indicates an abnormality detection circuit when the frequency of the alternating voltage signal 15 is low. The edge detection circuit is a circuit for extracting an edge portion from the alternating voltage signal of 15, and the counter 1
Clock input and a reset signal for the counter 2. The clock generator serves as a reset signal for the counter 1 and a clock signal for the counter 2. For the operation, see FIG.
Will be described later.

FIG. 5 shows a case where the FROM of claim 2 is built in a CPU. 17 is a C with a built-in FROM
It is PU. The write permission circuit A is the same as the write permission circuit B shown in FIG. 4, but there is no problem.

FIG. 6 shows a chart of the operation of the write enable circuit A. When rewriting after turning on the control power, 13
Is set to LOW, and the signal of 14 is set to HIGH. C
When PU is abnormal, this signal is high impedance or the write is not permitted because the logic does not match.

FIG. 7 shows operation waveforms of the write enable circuit B of FIG. CK is higher than the frequency of the A edge detection pulse
The frequency of pulse 1 is set low.

Under normal conditions, the counter 1 counts up the edge detection pulse A. CK1 is input with a count value lower than the abnormal H determination value NH, and the counter 1 is reset. Therefore, the output Q1 of the counter 1 remains LOW.

When the frequency of the edge detection pulse A increases during the H abnormality, the count value of the counter 1 exceeds the abnormality H determination value NH. Therefore, the output Q1 of the counter 1 is HI
It becomes GH. F / F1 is F by the output Q1 of counter 1.
/ F1 is changed from LOW to HIGH. With this signal, the rewrite permission signal 11 becomes LOW, which is not permitted.

When the frequency of the edge detection pulse A becomes low during the L abnormality, the count value of the counter 2 exceeds the abnormal L determination value NL. Therefore, the output Q2 of the counter 2 is HI
It becomes GH. F / F2 is F by the output Q2 of the counter 2.
/ F2 is changed from LOW to HIGH. With this signal, the rewrite permission signal 11 becomes LOW, which is not permitted.
In the embodiment of FIG. 3, an H abnormality and an L abnormality are output by the NOR gate. As a result, normality / abnormality of the repetition frequency of 15 alternating voltages is detected and used as a rewriting permission signal.

[0017]

According to the present invention, by monitoring the write voltage by the device to be written, the uncertainty of the write information due to the abnormal write voltage (writing is not sufficient and the write value changes) is eliminated. be able to. Further, by monitoring whether the written device is operating normally, it is possible to prevent the written device from erroneously writing due to runaway.

[Brief description of drawings]

1 is a block diagram of an embodiment of the present invention, claims 1 and 2. FIG.

FIG. 2 is a detailed diagram of a write enable circuit A.

FIG. 3 is a block diagram of an embodiment of the present invention, claims 1 and 3.

FIG. 4 is a detailed diagram of a write enable circuit B.

FIG. 5 is an embodiment in the case of a CPU with a built-in FROM;
2 is a block diagram of FIG.

FIG. 6 is a timing chart of a write enable circuit A.

FIG. 7 is a timing chart of a write enable circuit B.

[Explanation of symbols]

1 ... CPU, 2 ... FROM, 3 ... Write permission circuit A,
4 ... Voltage switching circuit, 5 ... Write power supply, 6 ... Writing device, 7 ... Address bus, 8 ... Data bus, 9 ... VC
C (logic power supply), 10 ... Rewriting power supply voltage monitor 1, 1
DESCRIPTION OF SYMBOLS 1 ... Voltage switching signal output, 12 ... Rewriting power supply voltage monitor 2, 13 ... Control signal, 14 ... Control signal, 15 ... Alternate voltage signal, 16 ... Write permission circuit B, 17 ... FROM built-in CPU, 18 ... Rewriting permission signal.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kenji Tabuchi 2520 Takaba, Takata, Katsuta City, Ibaraki Prefecture Hitachi, Ltd. Automotive Equipment Division

Claims (3)

[Claims] 1. A circuit using a flash memory (electrically erasable and electrically writable read-only memory hereafter FROM) as a read-only memory (hereinafter ROM) for storing programs and data of an automobile control device. A flash ROM writing circuit for a vehicle control device, which monitors the rewriting voltage applied to and starts rewriting if the monitored voltage is normal. 2. One of the two output signals of the rewrite control device
If one is a HIGH voltage and the other is a LOW voltage, rewriting is performed, and the flash R of the vehicle controller is characterized.
OM write circuit. 3. An output signal of the rewrite device outputs a HIGH voltage and a LOW voltage at a constant cycle (hereinafter referred to as an alternating voltage signal).
A flash ROM writing circuit for an automobile control device, which is rewritten only when the flash ROM is in operation.