JPH06266312A - Liquid crystal display device - Google Patents

Abstract

(57) [Summary] [Purpose] When capturing and displaying image data from a personal computer, the phase is automatically adjusted to prevent mis-sampling. [Structure] A video signal from a personal computer 1 is digitized by an A / D converter 41 which operates by a clock from a PLL section 42 and sent to an X driver 44 of a liquid crystal display panel 43 on a line-by-line basis. The video signal is also input to the phase detector 48, and the phase detector 48 determines whether or not the signal at a predetermined sampling position is at the same level in the vertical cycle over several fields. Is determined and the output clock phase of the PLL unit 42 is controlled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device for displaying image data output by a personal computer (hereinafter referred to as a personal computer).

[0002]

2. Description of the Related Art Due to the rapid spread of personal computers, there is an increasing demand for display devices that display characters representing the calculation results of personal computers and figures in drawings. As a current display device, a liquid crystal display device is used in most of so-called laptop personal computers, in which the main body of the personal computer and the display device are integrated. However, a single unit that is used by connecting to a disc top type personal computer, which is the mainstream of personal computers, has a cathode ray tube (CRT) display device, which is advantageous in terms of definition and cost. is doing.

However, since the liquid crystal system has many advantages such as better convergence and focus performance and smaller depth than the CRT system, the liquid crystal system can be used even in a disk top type personal computer if the definition is improved and the cost is reduced. It is likely to become mainstream.

FIG. 5 shows an example in which a liquid crystal display device is connected to a disc top type personal computer. In FIG. 5, 1
Is a disc top type personal computer (hereinafter simply referred to as a personal computer), and 20 is a liquid crystal display device. There is a central processing unit (CPU) 3 inside the personal computer 1, and this CP
Digital data for video is output from U3 and temporarily stored in a video memory (hereinafter referred to as VRAM) 4. VRA
When a certain amount of data is accumulated in M4, a control signal group (vertical synchronization (VD) pulse, horizontal synchronization (H
(D) pulse, clock, address, etc.) is given to the VRAM4, whereby the data inside the VRAM4 is
It is constructed and read out as video data (having data such as a blanking signal before and after the pattern data). This video data is input to the digital-analog (D / A) converter 6 and output as an analog video signal.

FIG. 6 shows signals of various parts in the personal computer 1. FIG. 2A shows a VD pulse, FIG. 6B shows an HD pulse, and FIG. 6C shows a clock.
Further, FIG. 6D shows a digital video signal output from the VRAM 4, and FIG. 6E shows an analog video signal output from the D / A converter 6.

The analog digital (A
The analog video signal is supplied to the / D) converter 21. Further, in order to synchronize with the personal computer 1, a VD pulse and an HD pulse are input to a phase locked loop (PLL) unit 22 inside the liquid crystal display device 20. PLL
The unit 22 generates various timing signals and clocks in synchronization with the VD pulse and the HD pulse. The clock from the PLL unit 22 is input to the A / D converter 21. The digitized video signal is input to the X driver 24 of the liquid crystal panel unit 23 and is sequentially sampled for each signal of one scanning line. The timing signal of the PLL unit 22 is also input to the panel control unit 27. The panel control unit 27 gives a timing signal to the X driver 24 and the Y driver 25 of the liquid crystal panel 23. X driver 24
A signal for one scanning line sent to (the signal has the same rate as the output of the VRAM 4 in the personal computer 1)
Is the liquid crystal panel 23 specified by the Y driver 25.
Are sent to all scan lines simultaneously. Thereby, the liquid crystal panel 23
The liquid crystal of the liquid crystal cell is driven to display an image. The liquid crystal panel 23 includes a display unit 26 of the liquid crystal panel 23, a vertical line (signal electrode) group from the X driver 24, and a Y driver 2
Horizontal lines (scanning electrodes) from 5 are assembled in a matrix form, and a thin film transistor (TFT) is provided at each intersection, and a liquid crystal is driven by applying a potential corresponding to the luminance level to display an image. It is like this.

One line of the video data shown in FIG. 7A is shifted and written in the X driver 23 in a line cycle, and the fetch timing signal and the shift clock thereof are supplied to the panel controller 27. Given by. When one line of data is written in the X driver 23, the display line for displaying the data is designated by the Y driver 25, and the designated pulse is given to the designated scan electrode. The scanning electrodes are sequentially designated line by line from the upper side to the lower side of the screen in one line cycle. As a result, the image is displayed on the display unit 26.

[0008]

According to the above-mentioned liquid crystal display device, the clock of the personal computer 1 and the liquid crystal display device 20.
7 (B) due to the phase shift of the same frequency clock in
There is a drawback that the phenomenon shown in (3) is likely to occur. At present, when a video signal output from a single personal computer 1 is displayed on a single display device, an analog video signal is adopted as a standard video signal. However, in general, a video signal of a personal computer has few color gradations and many characters, so that the output of the D / A converter 6 sampled by the clock in the personal computer as shown in (b) of FIG. 7 (B). Although the video signal is analog, it has a stepped shape. When this is sampled again with the clock in the display device to be a digital video signal, as shown in (c) or (d) of FIG. 7B,
Although the voltage level of a pixel can be sampled, in the case of (d), a situation occurs in which an adjacent pixel is sampled.
In such a case, for example, a character or the like having a width of 1 pixel should originally be white, but may become black in a certain field. Then, for the human eye, the letters look gray in general and are hard to see. Therefore, an object of the present invention is to provide a liquid crystal display device which prevents mis-sampling when image data of a personal computer is fetched and displayed.

[0009]

According to the present invention, there is provided a PLL section for generating a sampling clock synchronized with a synchronizing signal of an input video signal, and a sampling means for sampling the video signal based on the sampling clock from the PLL section. In a display device including a liquid crystal display panel to which an output video signal from the sampling means is supplied,

A signal corresponding to a specific sampling position is taken in over several fields of the video signal, it is judged whether or not the signal level is the same, and if different, the P
Phase detection means for controlling the output clock phase of the LL section.

[0011]

By the above means, when the sampling phase of the sampling clock is deviated, the phase of the sampling clock can be changed to control the sampling phase to a normal state.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. In the figure, the personal computer 1 is the same as the configuration shown in FIG. The video signal output from the personal computer 1 is supplied to the analog-digital (A / D) converter 21 of the liquid crystal display device 20. Further, in order to synchronize with the personal computer 1, a VD pulse and an HD pulse are input to a phase locked loop (PLL) unit 42 inside the liquid crystal display device 40. PLL
The unit 42 generates various timing signals and clocks in synchronization with the VD pulse and the HD pulse. The clock from the PLL unit 42 is input to the A / D converter 41. The digitized video signal is input to the X driver 44 of the liquid crystal panel unit 43, and is sequentially sampled for each signal of one scanning line. The timing signal of the PLL unit 42 is also input to the panel control unit 47. The panel control unit 47 gives a timing signal to the X driver 44 and the Y driver 45 of the liquid crystal panel 43. X driver 44
A signal for one scanning line sent to (the signal has the same rate as the output of the VRAM 4 in the personal computer 1)
Is the liquid crystal panel 43 designated by the Y driver 45.
Are sent to all scan lines simultaneously. Thereby, the liquid crystal panel 43
The liquid crystal of the liquid crystal cell is driven to display an image. The liquid crystal panel 43 includes a display unit 46 of the liquid crystal panel 43, a vertical line (signal electrode) group from the X driver 44, and a Y driver 4
Horizontal lines (scanning electrodes) from 5 are assembled in a matrix form, and a thin film transistor (TFT) is provided at each intersection, and a liquid crystal is driven by applying a potential corresponding to the luminance level to display an image. It is like this.

By the way, in this system, the output of the A / D converter 41 is also supplied to the phase detector 48.
The phase detector 48 monitors an area in which the signal level of the video signal does not change (for example, a specific level position of the color signal) for several fields, and when the level does not change, determines that the sampling phase is normal, Is changed, it is determined to be mis-sampling. The phase detector 48 supplies the determination output to the PLL unit 42. When the determination signal for determining mis-sampling is input to the PLL unit 42, the PLL unit 42 switches the phase of the sampling clock and outputs it. As a result, the phase detector 48 again monitors the level of the video signal at the predetermined position for several fields. By repeating this operation,
The sampling phase is maintained at the normal phase. FIG. 2 shows a specific configuration example of the phase detector 48.

The video signal from the A / D converter 41 is supplied to the input terminal 51. The input terminal 51 is supplied to the flip-flop circuit 53-1. Flip-flop circuit 53-1
Uses the VD pulse supplied to the input terminal 52 as a clock. The input video signal is sampled at the rising edge of this clock and led to the non-inverting output terminal Q, and its output is held until the rising edge of the next clock.

The output of the flip-flop circuit 53-1 is supplied to the A input of the selector 54-1 and this selector 54-1 is supplied.
Is supplied to the flip-flop circuit 53-2, and the output of the flip-flop circuit 53-2 is supplied to the selector 5
It is supplied to the A input of 4-2. In this way, the flip-flop circuit and the selector are sequentially connected alternately, and the output of the selector 54-n is input to the flip-flop circuit 53-n in the last stage. The B inputs of the selectors 54-1 to 54-n are
The video signal of the input terminal 51 is directly input. The selectors 54-1 to 54-n selectively derive the signal at the A input terminal when the signal input to the S terminal is at a low level, and select the signal at the B input terminal when the signal input to the S terminal is at a high level. Select and derive signals.

Next, each flip-flop circuit 53-1 to 53
The output of -n is input to the exclusive OR circuit 55. The exclusive OR circuit 55 is a circuit that detects whether or not the outputs of all the flip-flop circuits 53-1 to 53-n are the same, and outputs the low level “L” when they are the same, However, if there are different outputs, it changes to "H" level. The output of the exclusive OR circuit 55 is supplied to one of the AND circuits 56 and the clock input terminal of the counter 42a of the PLL unit 42. The VD pulse is supplied to the other of the AND circuits 56.

The output of the AND circuit 56 is supplied to one of the OR circuits 57. A reset signal generated when the power is turned on is supplied to the other side of the OR circuit 57. The output of the OR circuit 57 is the selector 54-1.
To 54-n S terminal. The counter 42a advances the count when the output of the exclusive OR circuit 55 changes from low level to high level, for example. Based on this counter value, the selector 42b selects and derives any one of a plurality of clocks having different phases, and
/ D converter.

First, it is assumed that the display device is powered on in the first field. Then, a reset signal (high level in FIG. 3 (h)) is input from the OR circuit 57, and each selector 54
-1 to 54-n select the B input, and as a result, the input terminal 51
The signals A'of are first selected all at once. Therefore, when the VD pulse is applied to the flip-flop circuits 53-1 to 53-n, each of them will latch the signal A ′. Therefore, at this time, the exclusive OR circuit 55 outputs the low level "L". Then, the output of the AND circuit 56 and the output of the OR circuit 57 become low level "L".

When a VD pulse is input in the next second field, the flip-flop circuit 53-1 latches the input at this time. Now, let the input at this time be A (this signal level is the same as the signal A ′, but is set to A for distinction). FIG. 3B shows a flip-flop circuit 53.
-1 shows the latch contents. In the present state, since the output of the exclusive OR circuit 55 is at the low level "L", the selectors 54-1 to 54-n are in the state of selecting the A input. This signal A is sequentially shifted to the flip-flop circuit at the subsequent stage every time the VD pulse is input. If mis-sampling occurs in the (n-1) th field and the signal X is sampled, the signal X is output in the (n-1) th field as shown in FIG. 3C. It will be. FIG. 3 (c)-
FIG. 3F shows the flip-flop circuits 53-2 to 53-5 in the subsequent stage.
The contents of 3-n are shown. When the signals X of different levels are sampled in this way, the output of the exclusive OR circuit 55 becomes high level "H" (FIG. 3 (g)), the output of the AND circuit 56 also becomes high level, and the OR circuit The output of 57 also becomes high level (FIG. 3 (h)).
This corresponds to resetting again. As a result, the signal A ″ at the input terminal 51 at this point is latched by the flip-flop circuits 53-1 to 53-n.

After that, the above operation is repeated. If the sampled signals are always at the same level, reset is not performed, the output of the exclusive OR circuit 55 is at low level, the output value of the counter 42a does not change, and the output clock phase of the PLL unit 42 is maintained. Will be done.

By the way, a signal which is always at a constant level like the above-mentioned sampling signal easily exists in an output video signal of a personal computer having many still images such as character information.
For example, vertical lines such as characters are often handled with one pixel,
“MEMORY TEST XXXK” that is displayed when the power of the personal computer is turned on.
The vertical line of the letter "T" of "B" should be selected for sampling. Various other sampling targets are conceivable, but it goes without saying that the pulse phase to be captured, that is, the VD pulse in the above example, is adjusted according to the position of the character to be sampled. Also, instead of always making a determination, set the sampling phase aptitude determination period,
The determination may be made during this determination period. The present invention is not limited to the above embodiments.

In the above embodiment, the signal to be sampled is selected from the existing video signals. However, the reference signal may be positively inserted from the personal computer side into the video signal and sampled.

FIG. 4A shows an embodiment therefor. For example, a reference signal that is easily detected by the phase detector 48 is recorded on a hard disk or a floppy disk 8 loaded in the personal computer 1. Then, when the power is turned on or the user's operation is performed, the reference signal is changed to the CPU.
3, output as a video signal through the VRAM 4 and the D / A converter 6, input to the liquid crystal display device 40, and may be used for determining phase synchronization of the sampling clock.
Various methods can be considered as the type of the reference signal. For example, as shown in FIG. 4B, the signal is such that several vertical lines each having a thickness corresponding to one pixel are displayed. Since the other parts are the same as those in the previous embodiment, the same reference numerals are given and the description thereof will be omitted.

[0025]

As described above, according to the present invention, when the image data of the personal computer is fetched and displayed, the phase is automatically adjusted to prevent mis-sampling.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a specific configuration example of the phase detector of FIG.

FIG. 3 is a timing chart for explaining the operation of the phase detector of FIG.

FIG. 4 is a diagram showing another embodiment of the present invention.

FIG. 5 is a diagram showing a conventional display device.

FIG. 6 is a timing chart for explaining the operation of the device of FIG.

FIG. 7 is an explanatory diagram of the operation of the conventional display device and its problems.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Personal computer, 3 ... CPU, 4 ... VRAM, 5 ... Control part, 6 ... D / A converter, 40 ... Liquid crystal display device, 41 ... A
/ D converter, 42 ... PLL section, 43 ... Display panel, 44
... X driver, 45 ... Y driver, 47 ... Panel control unit.

Claims (4)

[Claims] 1. A PLL section for generating a sampling clock synchronized with a synchronizing signal of an input video signal, a sampling means for sampling the video signal based on the sampling clock from the PLL section, and an output video from the sampling means. In a display device including a liquid crystal display panel to which a signal is supplied, a signal corresponding to a specific sampling position is taken in over several fields of the video signal, it is determined whether the signal level is the same or not, The liquid crystal display device, further comprising: a phase detection unit that controls the output clock phase of the PLL unit. 2. The liquid crystal display device according to claim 1, wherein the signal corresponding to the specific sampling position is a predetermined character signal of a video signal output from a personal computer. 3. The liquid crystal display device according to claim 1, wherein the signal corresponding to the specific sampling position is a predetermined color signal of a video signal output from a personal computer. 4. The liquid crystal display device according to claim 1, wherein the signal corresponding to the specific sampling position is a signal corresponding to a reference signal recorded on a disc of a personal computer.