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JPH06260799A - Circuit board inspecting method, and circuit board - Google Patents

Circuit board inspecting method, and circuit board

Info

Publication number
JPH06260799A
JPH06260799A JP5075251A JP7525193A JPH06260799A JP H06260799 A JPH06260799 A JP H06260799A JP 5075251 A JP5075251 A JP 5075251A JP 7525193 A JP7525193 A JP 7525193A JP H06260799 A JPH06260799 A JP H06260799A
Authority
JP
Japan
Prior art keywords
circuit board
circuit
main surface
mounting
component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5075251A
Other languages
Japanese (ja)
Other versions
JP2814869B2 (en
Inventor
Hirotaka Ito
裕貴 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Daifuku Co Ltd
Original Assignee
Daifuku Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Daifuku Co Ltd filed Critical Daifuku Co Ltd
Priority to JP5075251A priority Critical patent/JP2814869B2/en
Publication of JPH06260799A publication Critical patent/JPH06260799A/en
Application granted granted Critical
Publication of JP2814869B2 publication Critical patent/JP2814869B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0266Marks, test patterns or identification means
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections

Landscapes

  • Supply And Installment Of Electrical Components (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

PURPOSE:To inspect a mounted circuit board with a good accuracy through a simple process, by contacting twin probes respectively with the sections of test pads provided on the mounted circuit board exposed to the second principal surface of the mounting circuit board, and by inspecting whether a surface mount type part or the section to be connected therewith electrically is good or bad. CONSTITUTION:A test pad 15 is so provided on a circuit board main body 12 that it is connected electrically with the section of a wiring pattern 13 which is provided only on a first principal surface 12a and which serves only as the interconnecting section between plural surface mount circuit parts 22 and that its certain section is exposed to a second principal surface 12b. Then, twin probes 6a, 6b are contacted respectively with sections 15e of the test pads 15 provided on a mounted circuit board 20 which are exposed to the second principal surface 12b, or are contacted respectively with the sections of the circuit part 22 provided on the mounted circuit board 20 which are exposed to the second principal surface 12b. Thereby, it is inspected whether the surface mount type circuit part 22 provided on the mounted circuit board 20 is good or bad, or whether the section to be connected electrically with the part 22 is good or bad.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、表面実装型回路部品
が実装された実装回路基板の検査を行う回路基板検査方
法、およびこの検査方法を実施するのに適した回路基板
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board inspection method for inspecting a mounted circuit board on which surface mount type circuit components are mounted, and a circuit board suitable for carrying out this inspection method.

【0002】[0002]

【従来の技術】回路部品が実装された実装回路基板にお
いて、回路部品、配線パターン、およびそれらの間の接
続の良否を検査する実装回路基板の検査は、インサーキ
ットテスタ(検査装置)に備わる検査ピン(探針)を回
路部品の端子部分に押し当てることにより従来行われて
いた。図5は、この従来の検査方法を説明する説明図で
ある。実装回路基板10は、回路基板本体2の主面上に
所定の配線パターン3が配設されて成る回路基板1と、
この回路基板1に実装される回路部品4、5とを有して
いる。回路部品4、5に備わるピン4b、5bが、配線
パターン3の所定の部分にハンダ付けされることによ
り、回路部品4、5が回路基板1の所定の位置に実装さ
れている。また、回路部品4、5は、それぞれの本体部
4a、5aが回路基板本体2の表面、すなわち部品面
(第1の主面)2a側に位置するように実装されてい
る。
2. Description of the Related Art In a mounted circuit board on which circuit components are mounted, an inspection of the mounted circuit board for inspecting the circuit components, wiring patterns, and connections between them is performed by an in-circuit tester (inspection device). This is conventionally done by pressing a pin (probe) against the terminal part of the circuit component. FIG. 5 is an explanatory diagram for explaining this conventional inspection method. The mounting circuit board 10 includes a circuit board 1 formed by disposing a predetermined wiring pattern 3 on a main surface of a circuit board body 2.
It has circuit components 4 and 5 mounted on this circuit board 1. The pins 4b and 5b provided on the circuit components 4 and 5 are soldered to predetermined portions of the wiring pattern 3 so that the circuit components 4 and 5 are mounted at predetermined positions on the circuit board 1. The circuit components 4 and 5 are mounted such that the respective main body portions 4a and 5a are located on the surface of the circuit board main body 2, that is, on the component surface (first main surface) 2a side.

【0003】回路部品4、5の中のディスクリート部品
4は、回路基板本体2の裏面、すなわちハンダ面(第2
の主面)2bにピン4bの先端部分が露出する回路部品
である。ディスクリート部品4のみが実装された実装回
路基板10においては、ピン4bのハンダ面2bに露出
する部分に、1対の検査ピン6a、6bのそれぞれを押
し当てて接触させることにより、検査が行なわれてい
た。一方、ピン5bがハンダ面2bに露出しない表面実
装部品(表面実装型回路部品)5が実装された実装回路
基板10においては、表面実装部品5のピン5bに検査
ピン6a、6bを押し当てることによって表面実装部品
5の良否の検査が実行されていた。
The discrete component 4 among the circuit components 4 and 5 is the back surface of the circuit board body 2, that is, the solder surface (second
Is a circuit component in which the tip portion of the pin 4b is exposed on the main surface 2b. In the mounted circuit board 10 on which only the discrete component 4 is mounted, the inspection is performed by pressing the pair of inspection pins 6a and 6b into contact with the exposed portions of the pins 4b on the solder surface 2b. Was there. On the other hand, in the mounting circuit board 10 on which the surface mounting component (surface mounting type circuit component) 5 in which the pin 5b is not exposed to the solder surface 2b is mounted, the inspection pins 6a and 6b are pressed against the pin 5b of the surface mounting component 5. Thus, the quality inspection of the surface mount component 5 has been executed.

【0004】[0004]

【発明が解決しようとする課題】表面実装部品5が実装
された実装回路基板10の検査は、上述のような方法で
行われていたので、まず第1に検査ピン6a、6bを、
ハンダ面2bだけではなく部品面2aにも押し当てる必
要があり、検査工程が複雑にならざるを得ないという問
題点があった。また、両面を検査すべく検査装置の治具
を構成する必要があるので、検査装置のコストが高くな
るという問題点があった。
Since the mounting circuit board 10 on which the surface mounting component 5 is mounted has been inspected by the method as described above, firstly, the inspection pins 6a and 6b are
There is a problem in that it is necessary to press not only the solder surface 2b but also the component surface 2a, which complicates the inspection process. In addition, since it is necessary to configure a jig of the inspection device to inspect both sides, there is a problem that the cost of the inspection device becomes high.

【0005】第2に、近年において表面実装部品5のフ
ァインピッチ化が進行するのに伴い、検査ピン6a、6
bを使った検査が精度良く行うことが困難になるという
問題点があった。このため、検査が行えない部分を残し
たまま出荷せざるを得ないという事態が生まれており、
表面実装部品と配線パターンの間の接触不良が多発しつ
つあるという問題点があった。
Secondly, as the fine pitch of the surface mount component 5 has progressed in recent years, the inspection pins 6a, 6
There is a problem that it is difficult to perform the inspection using b with high accuracy. For this reason, there has been a situation in which it is unavoidable to ship products while leaving parts that cannot be inspected.
There is a problem that poor contact between the surface mount component and the wiring pattern is frequently occurring.

【0006】第3に、図6に模式的に示すように、ハン
ダ不良によってピン5bと配線パターン3との間が良好
に接続されていない、いわゆる「リード浮き」の場合に
おいても、検査ピン6a、6bの圧力によって検査の時
点ではピン5bと配線パターン3との間が一時的に接続
されることがあった。このため、本来不良と判定すべき
回路部分を合格と誤判定するという問題点があった。
Thirdly, as shown schematically in FIG. 6, even in the case of so-called "lead floating", in which the pin 5b and the wiring pattern 3 are not well connected due to defective soldering, the inspection pin 6a. , 6b, the pin 5b and the wiring pattern 3 may be temporarily connected at the time of the inspection. Therefore, there is a problem that a circuit portion that should be originally determined to be defective is erroneously determined to be acceptable.

【0007】この発明は上記のような問題点を解消する
ためになされたもので、簡単な工程で、しかも判定精度
のよい実装回路基板の検査を行い得る回路基板検査方
法、およびこの検査方法を実施するのに適した回路基板
を提供することを目的とする。
The present invention has been made in order to solve the above problems, and provides a circuit board inspection method capable of inspecting a mounted circuit board with high accuracy in a simple process, and an inspection method therefor. An object is to provide a circuit board suitable for implementation.

【0008】[0008]

【課題を解決するための手段】この発明に係る回路基板
検査方法は、複数の表面実装型回路部品を含む複数の回
路部品が回路基板に実装されて成る実装回路基板を検査
する回路基板検査方法であって、(a)第1および第2
の主面を有する電気絶縁体の回路基板本体を準備する工
程と、(b)1対の探針を備え、検査対象物に接触する
当該1対の探針の間の電気的特性を検出することによ
り、当該検査対象物の良否を検査する検査装置を準備す
る工程と、(c)前記複数の回路部品の間を電気的に接
続すべき配線パターンを、少なくとも前記第1の主面に
配設する工程と、(d)実質的に電気導電体のテストパ
ッドを、前記配線パターンの中の前記第1の主面にのみ
配設される部分であって、前記複数の表面実装型回路部
品の間のみを接続する部分に電気的に接続し、かつその
一部が前記第2の主面に露出するように、前記回路基板
本体に設置する工程と、(e)前記複数の回路部品の各
1の本体部が前記回路基板本体の前記第1の主面側に位
置するように、当該複数の回路部品を前記回路基板本体
の所定の位置に実装することにより、実装回路基板を作
成する工程と、(f)前記1対の探針の1を、前記実装
回路基板における前記テストパッドの前記第2の主面に
露出する部分に接触させ、他の1を当該実装回路基板に
おける他の前記テストパッドの前記第2の主面に露出す
る部分、または当該実装回路基板における前記回路部品
の前記第2の主面に露出する部分に接触させることによ
り、当該実装回路基板における前記表面実装型回路部品
または当該表面実装型回路部品に電気的に接続すべき部
分の良否を検査する工程と、を備える。
A circuit board inspection method according to the present invention is a circuit board inspection method for inspecting a mounted circuit board formed by mounting a plurality of circuit components including a plurality of surface mount type circuit components on a circuit board. And (a) the first and second
A step of preparing a circuit board body of an electrical insulator having a main surface of (1), and (b) including a pair of probes, and detecting electrical characteristics between the pair of probes in contact with an inspection object. Accordingly, a step of preparing an inspection device for inspecting the quality of the inspection object is provided, and (c) a wiring pattern for electrically connecting the plurality of circuit components is arranged on at least the first main surface. And (d) a portion in which a test pad of a substantially electric conductor is disposed only on the first main surface of the wiring pattern, and the plurality of surface mount circuit components are provided. A step of electrically connecting to only a portion connecting between the two, and installing the portion on the circuit board body so that a part of the plurality of circuit components is exposed to the second main surface; Each of the main body parts is located on the first main surface side of the circuit board main body, A step of forming a mounting circuit board by mounting a number of circuit components at predetermined positions on the circuit board body; and (f) replacing one of the pair of probes 1 with the test pad of the mounting circuit board. The other 1 is brought into contact with a portion exposed on the second main surface, and the other 1 is exposed on the second main surface of the other test pad of the mounting circuit board, or of the circuit component of the mounting circuit board. A step of inspecting the quality of the surface mount type circuit component of the mount circuit board or a part to be electrically connected to the surface mount type circuit component by contacting the part exposed on the second main surface, Equipped with.

【0009】この発明に係る回路基板は、複数の表面実
装型回路部品を含む複数の回路部品を実装すべき回路基
板であって、(a)前記複数の回路部品の各1の本体部
が位置すべき側である第1の主面と、第2の主面とを有
する電気絶縁体の回路基板本体と、(b)前記複数の回
路部品の間を所定の要領で電気的に接続すべき配線パタ
ーンであって、少なくとも前記第1の主面に配設される
配線パターンと、(c)前記配線パターンの中の前記第
1の主面にのみ配設される部分であって、前記複数の表
面実装型回路部品の間のみを接続する部分に電気的に接
続し、前記回路基板本体に設置されるテストパッドであ
って、かつその一部が前記第2の主面に露出する実質的
に電気導電体のテストパッドと、を備える。
A circuit board according to the present invention is a circuit board on which a plurality of circuit components including a plurality of surface mount type circuit components are to be mounted, and (a) each one main body portion of the plurality of circuit components is positioned. The electrically insulating circuit board body having the first main surface and the second main surface, which are the sides to be formed, and (b) the plurality of circuit components should be electrically connected in a predetermined manner. A plurality of wiring patterns, at least a wiring pattern arranged on the first main surface, and (c) a portion of the wiring pattern arranged only on the first main surface, A test pad which is electrically connected to a portion connecting only the surface mount type circuit components, and which is installed on the circuit board body, and a part of which is exposed on the second main surface. And an electrical conductor test pad.

【0010】[0010]

【作用】この発明における回路基板検査方法では、表面
実装型回路部品を実装する実装回路基板において、この
実装回路基板に配設された配線パターンの中で、回路部
品の本体が位置する第1の主面にのみ配設される部分で
あって、表面実装型部品にのみ接続する部分に電気的に
接続するテストパッドを設ける。テストパッドは実質的
に導電性であって、かつその一部が実装回路基板の第2
の主面に露出する。実装回路基板の検査は、回路部品の
第2の主面に露出する部分とテストパッドの同じく第2
の主面に露出する部分の中の何れかに、検査装置の探針
を接触させることにより行う。このため、探針を常に第
2の主面側にのみ接触させればよいので、検査の工程が
単純となる。また、探針を表面実装部品に接触させる必
要がないので、ファインピッチを有する表面実装部品を
実装した実装回路基板の検査においても、精度の良い検
査が実行し得る。更に、探針によって表面実装部品に圧
力を付加することもないので、表面実装部品と配線パタ
ーンの間の接続不良部分を、見落とすことなく検出する
ことができる。
According to the circuit board inspection method of the present invention, in the mounting circuit board on which the surface mounting type circuit component is mounted, in the wiring pattern arranged on the mounting circuit board, the main body of the circuit component is located. A test pad that is electrically connected to a portion that is provided only on the main surface and that is connected only to the surface mount type component is provided. The test pad is substantially conductive, and a portion of the test pad is on the second side of the mounting circuit board.
Exposed on the main surface of. The inspection of the mounted circuit board is performed by exposing the portion exposed on the second main surface of the circuit component and the second portion of the test pad.
The probe of the inspection device is brought into contact with any of the portions exposed on the main surface of the. For this reason, since the probe need only contact the second main surface side at all times, the inspection process is simplified. Further, since it is not necessary to bring the probe into contact with the surface mount component, it is possible to perform a highly accurate inspection even in the inspection of the mounted circuit board on which the surface mount component having a fine pitch is mounted. Furthermore, since no pressure is applied to the surface-mounted component by the probe, a defective connection portion between the surface-mounted component and the wiring pattern can be detected without overlooking.

【0011】この発明における回路基板では、回路部品
の本体が位置すべき第1の主面にのみ配設される配線パ
ターンの部分であって、表面実装型部品にのみ接続する
部分に電気的に接続するテストパッドを有する。テスト
パッドは実質的に導電性であって、かつその一部が実装
回路基板の第2の主面に露出している。このため、この
回路基板に表面実装部品を含む回路部品を実装して成る
実装回路基板の検査が、回路部品の第2の主面に露出す
る部分とテストパッドの同じく第2の主面に露出する部
分の中の何れかに、検査装置の探針を接触させることに
よって実行し得る。このため、実装回路基板の検査が単
純な工程でかつ精度良く行い得る。
In the circuit board according to the present invention, the portion of the wiring pattern provided only on the first main surface on which the main body of the circuit component is to be located, and electrically connected to the portion to be connected only to the surface mount type component. It has a test pad to connect to. The test pad is substantially conductive, and a part thereof is exposed on the second main surface of the mounting circuit board. Therefore, the inspection of the mounted circuit board formed by mounting the circuit component including the surface mount component on this circuit board is performed by exposing the portion exposed on the second main surface of the circuit component and the same second main surface of the test pad. This can be performed by bringing the probe of the inspection device into contact with any of the parts to be covered. Therefore, the mounting circuit board can be inspected in a simple process with high accuracy.

【0012】[0012]

【実施例】<実装回路基板の構成>図2は、この発明の
実施例における回路基板に表面実装型回路部品が実装さ
れた実装回路基板の構造を示す正面断面図(図2
(a))および平面図(図2(b))である。実装回路
基板20は、回路基板本体12の主面上に所定の配線パ
ターン13が配設されて成る回路基板11と、この回路
基板11に実装される回路部品とを有している。図2に
は、回路基板11に実装された2つの表面実装部品(表
面実装型回路部品)21、22が描かれている。表面実
装部品21、22にそれぞれ備わるピン21b、22b
が、配線パターン13の所定の部分にハンダ付けされる
ことにより、表面実装部品21、22が回路基板11の
所定の位置に実装されている。また、表面実装部品2
1、22は、それぞれの本体部21a、22aが回路基
板本体12の表面、すなわち部品面(第1の主面)12
a側に位置するように実装されている。表面実装部品2
1は例えば表面実装型の容量素子であり、表面実装部品
22は例えば表面実装型の集積回路素子である。配線パ
ターン13は例えば銅材で構成され、例えば良く知られ
るプリント配線技術を用いて形成される。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS <Structure of Mounted Circuit Board> FIG. 2 is a front sectional view showing the structure of a mounted circuit board in which surface mount type circuit components are mounted on the circuit board according to an embodiment of the present invention (FIG. 2).
(A)) and a top view (FIG.2 (b)). The mounted circuit board 20 includes a circuit board 11 in which a predetermined wiring pattern 13 is arranged on the main surface of the circuit board body 12, and circuit components mounted on the circuit board 11. In FIG. 2, two surface mount components (surface mount type circuit components) 21 and 22 mounted on the circuit board 11 are illustrated. Pins 21b and 22b provided on the surface mount components 21 and 22 respectively
However, the surface mount components 21 and 22 are mounted at predetermined positions on the circuit board 11 by being soldered to predetermined portions of the wiring pattern 13. In addition, surface mount component 2
1 and 22, the main body portions 21a and 22a are the surface of the circuit board main body 12, that is, the component surface (first main surface) 12
It is mounted so as to be located on the a side. Surface mount component 2
Reference numeral 1 is, for example, a surface mount type capacitive element, and surface mount component 22 is, for example, a surface mount type integrated circuit element. The wiring pattern 13 is made of, for example, a copper material and is formed by using, for example, a well-known printed wiring technique.

【0013】配線パターン13を構成するひと続きの部
分配線パターンの中で、表面実装部品同士のみを接続
し、かつ部品面12a上にのみ配置される部分配線パタ
ーンには、テストパッドが設けられている。図2の例で
は、表面実装部品21および22の間のみに接続する部
分配線パターン13aに、テストパッド15が設けられ
ている。
A test pad is provided in the partial wiring pattern that connects only surface mount components and is arranged only on the component surface 12a in the continuous partial wiring pattern that constitutes the wiring pattern 13. There is. In the example of FIG. 2, the test pad 15 is provided on the partial wiring pattern 13a connected only between the surface mount components 21 and 22.

【0014】図3はテストパッド15の構造を示す部分
断面斜視図(図3(a)、図3(c))および側面断面
図(図3(b))である。回路基板11には、部分配線
パターン13aおよび回路基板本体12を貫通する貫通
孔15aが設けられている。貫通孔15aの内側面15
bには配線パターン13と同じ材質の鍍金15cが施さ
れている。部品面12aおよび回路基板本体2の裏面、
すなわちハンダ面(第2の主面)12bへの貫通孔15
aの開口部には、配線パターン13と同じ材質であって
所定の径を有する円形パターン15d、15eがそれぞ
れ設けられている。これらの鍍金15c、円形パターン
15d、15eは、導電体であってしかも部分配線パタ
ーン13aと電気的に接続されている。
FIG. 3 is a partial sectional perspective view (FIGS. 3A and 3C) and a side sectional view (FIG. 3B) showing the structure of the test pad 15. The circuit board 11 is provided with a through hole 15a penetrating the partial wiring pattern 13a and the circuit board body 12. Inner surface 15 of through hole 15a
Plating 15c of the same material as the wiring pattern 13 is applied to b. The component surface 12a and the back surface of the circuit board body 2,
That is, the through hole 15 to the solder surface (second main surface) 12b
Circular patterns 15d and 15e made of the same material as the wiring pattern 13 and having a predetermined diameter are provided in the opening a. The plating 15c and the circular patterns 15d and 15e are conductors and are electrically connected to the partial wiring pattern 13a.

【0015】配線パターン13をプリント配線技術を用
いて形成する際には、それに先だって回路基板本体12
の主面上の全面に渡ってあらかじめ銅鍍金が施される。
回路基板本体12の所定の位置にあらかじめ貫通孔15
aを設けることにより、この銅鍍金の際に鍍金15c、
および円形パターン15d、15eを同時に形成するこ
とができる。
When the wiring pattern 13 is formed by using the printed wiring technique, the circuit board body 12 is preceded by it.
Copper plating is applied in advance over the entire main surface of the.
The through hole 15 is previously provided at a predetermined position of the circuit board body 12.
By providing a, the plating 15c,
The circular patterns 15d and 15e can be simultaneously formed.

【0016】すなわち、テストパッド15それ自体は、
従来知られるスルーホールあるいはバイアホールと同様
の構造を有し、かつ同様の方法で形成することができ
る。しかしながら、スルーホールはディスクリート部品
の接続を目的としたものであり、また、バイアホールは
回路基板本体12における2つの主面に配設された配線
パターン13の間を電気的に接続する目的で設けられる
ものである。この発明におけるテストパッド15はそれ
らのいずれでもなく、表面実装部品のみを接続しかつ部
品面12aにのみ配設される、配線パターン13の部分
配線パターン13aに設けられることを特徴としてい
る。テストパッド15が設けられるこの位置には、スル
ーホール、バイアホールともに設けられていない。すな
わち、スルーホール、またはバイアホールによって、テ
ストパッド15の代用とすることはできない点に注目さ
れたい。テストパッド15によって、後述するように、
実装回路基板20の検査を高い効率、精度をもって実行
することが可能となる。
That is, the test pad 15 itself is
It has the same structure as a conventionally known through hole or via hole and can be formed by a similar method. However, the through holes are provided for the purpose of connecting discrete components, and the via holes are provided for the purpose of electrically connecting between the wiring patterns 13 arranged on the two main surfaces of the circuit board body 12. It is what is done. The test pad 15 in the present invention is characterized in that it is provided on a partial wiring pattern 13a of the wiring pattern 13, which is connected to only the surface mount components and is arranged only on the component surface 12a, not any of them. At this position where the test pad 15 is provided, neither a through hole nor a via hole is provided. That is, it should be noted that the test pad 15 cannot be substituted by the through hole or the via hole. With the test pad 15, as will be described later,
It is possible to perform the inspection of the mounted circuit board 20 with high efficiency and accuracy.

【0017】テストパッド15の寸法、すなわち円形パ
ターン15d、15eの外径A、C、および内径Bに関
する2通りの代表例を表1に掲げる。比較的小径のもの
を、仮にミニバイヤと称し、それより大径のものをミド
ルバイヤと称している。
Table 1 shows two representative examples of the dimensions of the test pad 15, that is, the outer diameters A and C and the inner diameter B of the circular patterns 15d and 15e. The one with a relatively small diameter is tentatively called a mini-via, and the one with a larger diameter is called a middle bayer.

【0018】[0018]

【表1】 [Table 1]

【0019】なお言うまでもなく、実装回路基板20に
は、表面実装部品だけではなく、それに加えてディスク
リート部品が実装されていてもよい。
Needless to say, the mounting circuit board 20 may be mounted with not only surface mounting components but also discrete components.

【0020】<検査の方法>上述の実装回路基板20を
形成した後に行う、実装回路基板20の検査方法につい
て述べる。図1および図4は、この検査方法を示す説明
図である。検査ピン6a、6bを備えるインサーキット
テスタ(検査装置)6は、装置本体6cにおいて、検査
ピン(探針)6a、6bの間の抵抗、容量、誘導、イン
ピーダンス、電圧等の電気的特性の検出を行う。
<Inspection Method> A method of inspecting the mounting circuit board 20 performed after the mounting circuit board 20 is formed will be described. 1 and 4 are explanatory views showing this inspection method. The in-circuit tester (inspection device) 6 including the inspection pins 6a and 6b detects electrical characteristics such as resistance, capacitance, induction, impedance, and voltage between the inspection pins (probes) 6a and 6b in the device body 6c. I do.

【0021】図1には、表面実装部品22が有する1対
のピン22bに接続する部分配線パターン13aがいず
れも、他の表面実装部品にのみ接続されており、かつ部
品面12aにのみ配設されている例を示している。従っ
て、これらの部分配線パターン13aには、テストパッ
ド15が設けられている。実装回路基板20上にある表
面実装部品22の特性の良否、あるいは表面実装部品2
2と部分配線パターン13aとの接続の良否の検査は、
検査ピン6a、6bをハンダ面12bの側から2つのテ
ストパッド15にそれぞれ押し当てることによって実行
される。この検査において、表面実装部品22が本来有
する所定の電気的特性が検出されるならば、表面実装部
品22それ自体、表面実装部品22と部分配線パターン
13aとの接続のいずれもが良好であると判定し得る。
逆に所定の電気的特性が得られなければ、それらの何れ
かが不良であると判定し得る。この場合には、不良原因
が何れであるかが目視等によって更に追求され、処分、
交換、修復などの所定の処置が構じられる。
In FIG. 1, each of the partial wiring patterns 13a connected to the pair of pins 22b of the surface mount component 22 is connected only to another surface mount component and is arranged only on the component surface 12a. An example is shown. Therefore, the test pads 15 are provided on these partial wiring patterns 13a. The quality of the characteristics of the surface mount component 22 on the mount circuit board 20 or the surface mount component 2
2 is an inspection of the quality of the connection between the partial wiring pattern 13a and
It is performed by pressing the inspection pins 6a and 6b against the two test pads 15 from the solder surface 12b side. If the predetermined electrical characteristics originally possessed by the surface mount component 22 are detected in this inspection, then both the surface mount component 22 itself and the connection between the surface mount component 22 and the partial wiring pattern 13a are good. You can judge.
On the contrary, if the predetermined electrical characteristics are not obtained, it can be determined that any one of them is defective. In this case, the cause of the defect is further sought by visual inspection, and the disposal,
Predetermined measures such as replacement and repair are planned.

【0022】図4は、実装回路基板20上にあるディス
クリート部品23の特性の良否を検査する方法を示して
いる。配線パターン13に接続するスルーホール16が
有する貫通孔にピン23bを貫通させ、かつピン23b
をスルーホール16にハンダ付けすることによって、デ
ィスクリート部品23が回路基板11の所定の位置に実
装されている。ディスクリート部品23の検査は、ハン
ダ面12bの側から検査ピン6a、6bを、ハンダ面1
2bに露出するピン23bの先端部に押し当てることに
より実行される。
FIG. 4 shows a method for inspecting the quality of the characteristics of the discrete component 23 on the mounting circuit board 20. The pin 23b is penetrated through the through hole of the through hole 16 connected to the wiring pattern 13, and the pin 23b
The discrete component 23 is mounted at a predetermined position on the circuit board 11 by soldering the to the through hole 16. When inspecting the discrete component 23, the inspection pins 6a and 6b are attached to the solder surface 1 from the side of the solder surface 12b.
It is executed by pressing the tip of the pin 23b exposed to 2b.

【0023】図4には、実装回路基板20に実装されて
いる表面実装部品22の検査方法をも同時に示してい
る。表面実装部品22では、1対のピン22bに接続す
る配線パターン13の中で1つは他の表面実装部品21
にのみ接続されており、他の1つはディスクリート部品
23に接続されている。検査ピン6a、6bを、表面実
装部品22の1つのピン22bと、他方のピン22bに
配線パターン13で接続されるディスクリート部品23
の1つのピン23bとに、ハンダ面12bの側からそれ
ぞれ押し当てることにより、表面実装部品22の特性の
良否、および表面実装部品22と配線パターン13との
間の接続の良否の検査が実行される。
FIG. 4 also shows a method of inspecting the surface mount component 22 mounted on the mount circuit board 20 at the same time. In the surface mount component 22, one of the wiring patterns 13 connected to the pair of pins 22b is the other surface mount component 21.
And the other one is connected to the discrete component 23. Discrete component 23 in which inspection pins 6a and 6b are connected to one pin 22b of surface mount component 22 and the other pin 22b by wiring pattern 13.
Each of the pins 23b is pressed against the solder surface 12b from the side of the solder surface 12b, so that the quality of the characteristics of the surface mount component 22 and the quality of the connection between the surface mount component 22 and the wiring pattern 13 are inspected. It

【0024】以上の例に示したように、この実施例の検
査方法では、検査ピン6a、6bを、テストパッド1
5、またはディスクリート部品のハンダ面12bに露出
するピンに、ハンダ面12bの側から押し当てることに
よって、実装回路基板20上にある表面実装部品21、
22等、およびそれらと配線パターン13との接続状態
に関する検査が実行される。検査ピン6a、6bを部品
面12aの側には押し当てる必要がなく、ハンダ面12
bの側にのみ押し当てれば良いので、検査工程が従来の
方法よりも単純で効率がよい。また、従来の方法と異な
り、表面実装部品21等のピン21bに検査ピン6a、
6bで押し当てる必要がないので、ファインピッチを有
する表面実装部品21等の検査が容易に行い得る他、検
査ピン6a、6bの圧力によって、ピン21b等と配線
パターン13との間の接続不良を見落とす恐れもない。
As shown in the above example, in the inspection method of this embodiment, the inspection pins 6a and 6b are connected to the test pad 1
5, or the surface mount component 21 on the mounting circuit board 20 by pressing against the pins exposed on the solder face 12b of the discrete component from the solder face 12b side,
22 and the like, and the connection state between them and the wiring pattern 13 are inspected. It is not necessary to press the inspection pins 6a and 6b against the component surface 12a side.
Since it is necessary to press only on the side of b, the inspection process is simpler and more efficient than the conventional method. Further, unlike the conventional method, the inspection pin 6a is attached to the pin 21b of the surface mount component 21 or the like.
Since it is not necessary to press with the 6b, the surface mount component 21 having a fine pitch and the like can be easily inspected, and the connection between the pin 21b and the wiring pattern 13 can be prevented due to the pressure of the inspection pins 6a and 6b. There is no fear of overlooking.

【0025】[0025]

【発明の効果】この発明の回路基板検査方法では、回路
基板にあらかじめテストパッドを設け、このテストパッ
ドを用いて、検査装置の探針を回路基板の第2の主面側
に接触させることにより、表面実装型回路部品を実装す
る実装回路基板の検査を実行する。このため、探針を第
1および第2の主面側の双方に接触させる必要がないの
で、単純な工程で検査を実行し得る効果がある。また、
探針を表面実装型回路部品に接触させる必要がないの
で、ファインピッチを有する表面実装部品を実装した実
装回路基板の検査においても、精度の良い検査を実行し
得る効果がある。更に、探針が表面実装部品に圧力を付
加することがないので、表面実装部品と配線パターンの
間の接続不良部分を検出し損なうことなく、精度のよい
検査を実行し得る効果がある。
According to the circuit board inspection method of the present invention, a test pad is provided in advance on the circuit board, and the probe of the inspection device is brought into contact with the second main surface side of the circuit board using this test pad. , The inspection of the mounting circuit board on which the surface mounting type circuit component is mounted is executed. For this reason, it is not necessary to bring the probe into contact with both the first and second principal surface sides, so that there is an effect that the inspection can be executed in a simple process. Also,
Since it is not necessary to bring the probe into contact with the surface mount type circuit component, there is an effect that an accurate test can be executed even in the inspection of the mounted circuit board on which the surface mount component having a fine pitch is mounted. Further, since the probe does not apply pressure to the surface mount component, there is an effect that an accurate inspection can be performed without failing to detect a defective connection portion between the surface mount component and the wiring pattern.

【0026】この発明における回路基板では、表面実装
型部品にのみ接続し、第1の主面にのみ配設される配線
パターンの部分にテストパッドが設けられている。この
ため、この回路基板に表面実装部品を含む回路部品を実
装して成る実装回路基板の検査が、単純な工程でかつ精
度良く行い得る効果がある。
In the circuit board according to the present invention, the test pad is provided in the portion of the wiring pattern which is connected only to the surface mount type component and is arranged only on the first main surface. Therefore, there is an effect that an inspection of a mounted circuit board formed by mounting a circuit component including a surface mount component on this circuit substrate can be performed with high accuracy in a simple process.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の実施例における検査方法を示す説明
図である。
FIG. 1 is an explanatory diagram showing an inspection method according to an embodiment of the present invention.

【図2】この発明の実施例における実装回路基板の構造
を示す構造図である。
FIG. 2 is a structural diagram showing a structure of a mounting circuit board according to an embodiment of the present invention.

【図3】この発明の実施例におけるテストパッドの構造
を示す構造図である。
FIG. 3 is a structural diagram showing a structure of a test pad according to an embodiment of the present invention.

【図4】この発明の実施例における検査方法を示す説明
図である。
FIG. 4 is an explanatory diagram showing an inspection method according to an embodiment of the present invention.

【図5】従来の検査方法を説明する説明図である。FIG. 5 is an explanatory diagram illustrating a conventional inspection method.

【図6】従来の検査方法を説明する説明図である。FIG. 6 is an explanatory diagram illustrating a conventional inspection method.

【符号の説明】[Explanation of symbols]

6 インサーキットテスタ 6a、6b 検査ピン(探針) 11 回路基板 12 回路基板本体 12a 部品面(第1の主面) 12b ハンダ面(第2の主面) 13 配線パターン 15 テストパッド 20 実装回路基板 21、22 表面実装部品(表面実装型回路部品) 23 ディスクリート部品 21a、22a、23a 本体部 6 in-circuit tester 6a, 6b inspection pin (probe) 11 circuit board 12 circuit board body 12a component surface (first main surface) 12b solder surface (second main surface) 13 wiring pattern 15 test pad 20 mounting circuit board 21, 22 Surface-Mounted Components (Surface-Mounted Circuit Components) 23 Discrete Components 21a, 22a, 23a Main Body

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 複数の表面実装型回路部品を含む複数の
回路部品が回路基板に実装されて成る実装回路基板を検
査する回路基板検査方法であって、 (a)第1および第2の主面を有する電気絶縁体の回路
基板本体を準備する工程と、 (b)1対の探針を備え、検査対象物に接触する当該1
対の探針の間の電気的特性を検出することにより、当該
検査対象物の良否を検査する検査装置を準備する工程
と、 (c)前記複数の回路部品の間を電気的に接続すべき配
線パターンを、少なくとも前記第1の主面に配設する工
程と、 (d)実質的に電気導電体のテストパッドを、前記配線
パターンの中の前記第1の主面にのみ配設される部分で
あって、前記複数の表面実装型回路部品の間のみを接続
する部分に電気的に接続し、かつその一部が前記第2の
主面に露出するように、前記回路基板本体に設置する工
程と、 (e)前記複数の回路部品の各1の本体部が前記回路基
板本体の前記第1の主面側に位置するように、当該複数
の回路部品を前記回路基板本体の所定の位置に実装する
ことにより、実装回路基板を作成する工程と、 (f)前記1対の探針の1を、前記実装回路基板におけ
る前記テストパッドの前記第2の主面に露出する部分に
接触させ、他の1を当該実装回路基板における他の前記
テストパッドの前記第2の主面に露出する部分、または
当該実装回路基板における前記回路部品の前記第2の主
面に露出する部分に接触させることにより、当該実装回
路基板における前記表面実装型回路部品または当該表面
実装型回路部品に電気的に接続すべき部分の良否を検査
する工程と、 を備える回路基板検査方法。
1. A circuit board inspection method for inspecting a mounted circuit board in which a plurality of circuit components including a plurality of surface mount type circuit components are mounted on a circuit board, comprising: (a) first and second main components. A step of preparing a circuit board body of an electric insulator having a surface, and (b) a step of providing a pair of probes and contacting an inspection object.
A step of preparing an inspection device for inspecting the quality of the inspection object by detecting an electrical characteristic between the pair of probes; and (c) electrically connecting the plurality of circuit components. Arranging a wiring pattern on at least the first main surface, and (d) arranging a substantially electrically conductive test pad only on the first main surface in the wiring pattern. The part is electrically connected to a part that connects only the plurality of surface mount type circuit components, and is installed on the circuit board body so that a part of the part is exposed to the second main surface. And (e) the plurality of circuit components are arranged in a predetermined manner on the circuit board body so that each one of the plurality of circuit components is located on the first main surface side of the circuit board body. A step of creating a mounting circuit board by mounting at a position, and (f) before One of the pair of probes is brought into contact with a portion of the mounting circuit board exposed to the second main surface of the test pad, and the other one is connected to the other portion of the test pad of the mounting circuit board. The surface mounting type circuit component or the surface mounting on the mounting circuit board is brought into contact with the portion exposed on the main surface of No. 2 or the portion exposing on the second main surface of the circuit component on the mounting circuit board. A method of inspecting a circuit board, comprising the step of inspecting the quality of a portion to be electrically connected to the mold circuit component.
【請求項2】 複数の表面実装型回路部品を含む複数の
回路部品を実装すべき回路基板であって、 (a)前記複数の回路部品の各1の本体部が位置すべき
側である第1の主面と、第2の主面とを有する電気絶縁
体の回路基板本体と、 (b)前記複数の回路部品の間を所定の要領で電気的に
接続すべき配線パターンであって、少なくとも前記第1
の主面に配設される配線パターンと、 (c)前記配線パターンの中の前記第1の主面にのみ配
設される部分であって、前記複数の表面実装型回路部品
の間のみを接続する部分に電気的に接続し、前記回路基
板本体に設置されるテストパッドであって、かつその一
部が前記第2の主面に露出する実質的に電気導電体のテ
ストパッドと、 を備える回路基板。
2. A circuit board on which a plurality of circuit components including a plurality of surface mount type circuit components are to be mounted, wherein: (a) a side on which a main body of each one of the plurality of circuit components is to be located; A circuit board body of an electrical insulator having one main surface and a second main surface, and (b) a wiring pattern for electrically connecting the plurality of circuit components in a predetermined manner, At least the first
And (c) a portion of the wiring pattern, which is provided only on the first main surface, between the plurality of surface mount type circuit components. A test pad which is electrically connected to a connecting portion and which is installed on the circuit board body, and which is a substantially electrically conductive test pad, a part of which is exposed on the second main surface; Circuit board equipped.
JP5075251A 1993-03-08 1993-03-08 Circuit board inspection method and circuit board Expired - Fee Related JP2814869B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5075251A JP2814869B2 (en) 1993-03-08 1993-03-08 Circuit board inspection method and circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5075251A JP2814869B2 (en) 1993-03-08 1993-03-08 Circuit board inspection method and circuit board

Publications (2)

Publication Number Publication Date
JPH06260799A true JPH06260799A (en) 1994-09-16
JP2814869B2 JP2814869B2 (en) 1998-10-27

Family

ID=13570821

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5075251A Expired - Fee Related JP2814869B2 (en) 1993-03-08 1993-03-08 Circuit board inspection method and circuit board

Country Status (1)

Country Link
JP (1) JP2814869B2 (en)

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US8853694B2 (en) 2012-01-09 2014-10-07 Samsung Electronics Co., Ltd. Chip on film package including test pads and semiconductor devices including the same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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US7884924B2 (en) 2006-11-29 2011-02-08 Hitachi, Ltd. Residual stress measuring method and system
US8853694B2 (en) 2012-01-09 2014-10-07 Samsung Electronics Co., Ltd. Chip on film package including test pads and semiconductor devices including the same

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