JPH06260539A - Semiconductor device - Google Patents

Abstract

(57) [Summary] [Object] To provide a semiconductor device capable of easily and in detail examining history data for each semiconductor chip. [Structure] When manufacturing a DRAM 11, a ROM 1 that stores history data relating to the preceding steps of the manufacturing process.
2 in the same package. The DRAM 11, R
The OM 11 is formed on the same semiconductor chip to form a one-chip microcomputer. Also, the above R
The OM 11 is a mask ROM that writes the data in a wiring pattern or a mask pattern when forming a gate electrode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor technology, and more particularly to a technology that is particularly effective when applied to the attachment of related information to the semiconductor device itself, and is used, for example, for storing history data of packaged semiconductor chips Regarding useful technology.

[0002]

2. Description of the Related Art Conventionally, a wafer scribe area before a dicing process is provided with a lot number to which the wafer belongs, a wafer number indicating how many wafers are in the lot, and the like. Based on this, data about the history of the wafer can be read out from the management data recorded in a management book or the like. Then, when the wafer inspection is performed before the dicing process, the inspection result is analyzed based on the history data of the wafer, and the analysis result is reflected in the subsequent manufacturing technology.

[0003]

However, the lot number and the wafer number can be used only in the wafer state, and the history cannot be known after dicing. For this reason, there is also known a product management method in which the product after packaging is given a serial number so that the history can be known, but the serial number given in this case is provided in correspondence with the lot number. Therefore, only the information to the extent that the lot to which the semiconductor chip belongs can be specified, that is, the management to the extent that the manufacturing date is determined. This is because there are about 1000 chips included in one lot, so that serial number management becomes complicated to manage data for each chip, and data corresponding to each number can be stored and held. Because it is not easy.

Further, when the history data is known by performing management based on the serial number, the history data of the chip must be retrieved from a large amount of separately stored information based on the serial number. A great deal of labor will be required for the investigation. The present invention has been made in view of such circumstances, and a main object of the present invention is to provide a semiconductor device capable of easily and in detail examining history data for each semiconductor chip.

[0005]

The typical ones of the inventions disclosed in the present application will be outlined below. That is, a storage unit in which the history data related to the previous process of the semiconductor chip is stored is provided in the package. Further, it is desirable that the storage section is formed on the semiconductor chip.

[0006]

The history data for each semiconductor chip can be stored individually and in detail, and even after packaging, the reading can be performed without breaking the chip.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing an internal configuration of a semiconductor memory device (DRAM) to which the present invention is applied. As shown in this figure, in a semiconductor chip 1 in which a semiconductor memory device (DRAM) is formed, a DRAM section (first memory section) 11 and a ROM section in which history data related to the previous process of the chip is stored. (Second storage unit) 12 is formed. The semiconductor memory device is composed of a MOS device, although not particularly limited thereto.

The semiconductor chip 1 is provided with an address decoder 13 connected to these two storage units 11 and 12, an output circuit 14, a switching circuit 15 and a test mode signal generating circuit 16. The two storage units 11 and 1
2 and the output circuit 14, the switching circuit 15 is connected to the test mode signal generation circuit 1
On the basis of the control signal from 6, the above two storage units 11, 1
One of the two output terminals is connected to the output circuit 14. In the semiconductor memory device of this embodiment, the DRAM section 11, the ROM section 12, the address decoder 1 are used.
3, the output circuit 14, the switching circuit 15, and the test mode signal generation circuit 16 are all formed on the same chip.

The switching circuit 15 is provided between the MOS transistors Tr ₁ and Tr ₂ respectively connected to the output terminal of the ROM section 12 and the output terminal of the RAM section 11, and between the two transistors, as shown in the figure. It consists of an inverter. And in normal mode (other than test mode),
The control signal from the test mode signal generation circuit 16 is held at a high level, the MOS transistor Tr ₂ is turned on (transistor Tr ₁ is turned off) at this time, and the RAM section 11 is turned on.
The output terminal of is connected to the output circuit 14. Therefore, in the semiconductor chip 1, the RAM section 11 functions based on the signal from the address decoder 13 (function in the normal mode).

Then, when a low-level control signal indicating that the test mode should be performed is output from the test mode signal generation circuit 16, this time, the MOS transistor Tr ₁
Is turned on (transistor Tr ₂ is off), ROM section 1
Two output terminals are connected to the output circuit 14. At this time,
In the semiconductor chip 1, the ROM section 12 functions based on the signal from the address decoder 13, and the signal representing the history data is output from the output circuit 14. The test mode signal generation circuit 16 outputs a high-level or low-level control signal according to the input timing of a signal (for example, a RAS signal or a CAS signal) input from the outside.

By the way, in the ROM section 12, the lot number to which the wafer of the semiconductor chip 1 belonged, the wafer number in the lot, the sample number representing the position of the chip in the wafer, and the gate size. Various history data related to the previous process such as data related to the manufacturing process, etc. are written. The ROM section 12
Is composed of a mask ROM composed of MOS transistors, and the writing of the various history data to the ROM section 12 corresponds to the contents of data to be stored.
This is performed by determining the presence or absence of wiring of each cell in the OM portion or the presence or absence of a gate electrode. In this case, the stored contents are
It is determined by a plurality of mask patterns used for exposure in the wiring forming step or the gate electrode forming step. For this reason,
The history data related to the previous process, for example, RAM and ROM
In the wiring forming process of step 1, by determining the presence or absence of the wiring pattern or the gate of the ROM portion according to the stored content,
The history data to be stored can be saved each time in the wiring process or the gate formation process. Therefore, it is not necessary to collectively manage the data of all the chips and then perform the complicated work such as writing each data in correspondence with each chip.

As described above in detail, in the semiconductor memory device of this embodiment, the RAM portion for performing the original function of the memory device and the history data of the preceding process of the chip are stored on the same semiconductor chip. Since the ROM part is formed, it is possible to electrically and non-destructively know the history of the previous process even after packaging, and it can be used as data for defect analysis and process improvement. . Further, since each semiconductor chip is provided with a storage unit for storing the history, only the data relating to the individual chips can be efficiently stored, and the management of the history data is simplified. Further, since the storage unit is formed of MOS transistors, the RO having a desired storage capacity can be provided in a narrow range.
The M part can be secured.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in this embodiment, an example in which the RAM section and the ROM section are formed on the same semiconductor chip is shown, but the RO storing the history data is shown.
The M portion may be formed on another chip and housed in the same package. In this case, unlike the above embodiment,
Data of all chips is temporarily stored separately and managed collectively,
After that, it is necessary to write the data corresponding to each chip in association with each chip. Further, in this embodiment, an example in which the history data is stored in the mask ROM has been shown.
Another ROM such as a ROM may be provided in the package and the history data may be written therein.

In the above explanation, the case where the invention made by the present inventor is mainly applied to the history survey of the LSI such as the semiconductor memory device which is the field of application which is the background has been explained, but the present invention is not limited thereto. Not something
For example, it can be widely used for storing information related to the semiconductor device such as specifications and usage conditions of the semiconductor device.

[0015]

According to the present invention, after mounting a semiconductor chip on a package, it is possible to easily and in detail investigate the history of the preceding process without destroying the semiconductor chip.

[Brief description of drawings]

FIG. 1 is a semiconductor memory device (DRA) to which the present invention is applied.
It is a block diagram which shows the internal structure of M).

[Explanation of symbols]

 1 semiconductor chip 11 DRAM part 12 ROM part 15 switching circuit 16 test mode signal generation circuit

Claims (3)

[Claims] 1. A semiconductor device comprising a storage section in a package, in which history data relating to a previous step of a semiconductor chip manufacturing process is stored. 2. The semiconductor device according to claim 1, wherein the storage section is formed on the semiconductor chip. 3. The semiconductor device according to claim 1, wherein the storage unit is composed of a mask ROM.