JPH06259986A - Semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] To realize a single-chip microcomputer, etc. that secures both high speed in the high speed mode and low power consumption in the low speed mode. A frequency-voltage conversion circuit FVC whose output potential is changed in proportion to the frequency of a clock signal is provided in a single-chip microcomputer having a read-only memory and having a high-speed mode and a low-speed mode,
The output voltage of the frequency-voltage conversion circuit FVC is supplied as a control voltage VG to the gates of the drive MOSFET N3 of the unit read amplifiers URA0 to URA15 that form the read amplifier RA of the read-only memory. Thus, in the high speed mode, the potential of the control voltage VG is increased to operate the read amplifier RA at a high speed, and in the low speed mode, the potential of the control voltage VG is decreased to reduce the power consumption of the read amplifier RA.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a technique which is particularly effective when used in a single-chip microcomputer having a built-in read-only memory and having a high speed mode and a low speed mode. .

[0002]

2. Description of the Related Art There is a single chip microcomputer having a read only memory for storing a control program of a central processing unit, fixed data and the like. The read-only memory has multiple bits according to the bit configuration of the internal bus of the single-chip microcomputer, and is provided corresponding to each bit of 16-bit read data that is simultaneously output, for example, as shown in FIG. 1
Six unit read amplifiers URA0 to URA15 are provided. These unit read amplifiers are provided with common data lines CD0 to C0 from 16 memory cells selected in the memory array.
A current sense circuit CS that converts a read current output through D15 into a predetermined voltage signal, and a pair of N-channel type differential MOSFETs (metal oxide semiconductor field effect transistors. In this specification, MOSFETs are used. And a differential amplifier circuit DA centered on N1 and N2. An N-channel type which acts as a current source by receiving a predetermined control voltage VG at its gate between the commonly coupled sources of the differential MOSFETs N1 and N2 forming the differential amplifier circuit DA and the ground potential of the circuit. Drive MOSFET N3 is provided.

For a mask ROM provided with a read amplifier having a MOSFET as a basic structure, for example, 199
It is described on pages 754 to 761 of "Hitachi IC Memory Data Book", published by Hitachi, Ltd., September 1st. Also, for a single-chip microcomputer incorporating a read-only memory, for example, 199
"H32 / 200" issued by Hitachi, Ltd. in February 2000
HD642032 User's Manual ”and the like.

[0004]

In the conventional read-only memory described above, the control voltage VG supplied to the gate of the drive MOSFET N3 forming the differential amplifier circuit DA is a constant voltage having a constant potential, The potential is set according to the operating current value to be passed through the differential amplifier circuit DA via the drive MOSFET N3. That is, when the potential of the control voltage VG is set to be relatively high, the drive M
The value of the operating current given to the differential amplifier circuit DA via the OSFET N3 becomes relatively large. Therefore, the read amplifier RA, and eventually the single-chip microcomputer incorporating the read amplifier RA, operates at high speed.
The power consumption becomes relatively large. On the other hand, when the potential of the control voltage VG is set relatively low, the drive MOS
The value of the operating current supplied to the differential amplifier circuit DA via the FET N3 is relatively small. For this reason, the power consumption of the read amplifier RA and eventually of the single-chip microcomputer incorporating the read amplifier RA is small, but the operation thereof is relatively slow. That is, the control voltage VG
The potential must be set relatively high when the high speed of the single-chip microcomputer is important, and relatively low when the low power consumption of the single-chip microcomputer is important.

However, when the single-chip microcomputer has, for example, a high-speed mode in which the frequency of the clock signal is increased and a low-speed mode in which the frequency is decreased, the potential of the control voltage VG is set to be relatively high. Then, although the high speed of the single-chip microcomputer in the high speed mode can be ensured, the low power consumption in the low speed mode cannot be realized, and conversely, when the potential of the control voltage VG is set relatively low, the low speed mode Although low power consumption can be ensured, there is a problem that high speed in the high speed mode cannot be realized.

An object of the present invention is to realize a semiconductor device such as a single-chip microcomputer which secures both high speed in the high speed mode and low power consumption in the low speed mode.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, a single-chip microcomputer having a built-in read-only memory and having a high-speed mode and a low-speed mode is provided with a frequency-voltage conversion circuit whose output potential is changed in proportion to the frequency of a clock signal. Is supplied as a control voltage to the gates of the drive MOSFETs of the plurality of unit read amplifiers included in the read-only memory.

[0009]

According to the above means, in the high speed mode, the potential of the control voltage is increased to operate the read amplifier at high speed,
In the low speed mode, the operating voltage of the read amplifier can be reduced by lowering the potential of the control voltage. As a result, it is possible to realize a single-chip microcomputer or the like that ensures both high speed in the high speed mode and low power consumption in the low speed mode.

[0010]

1 is a block diagram showing an embodiment of a single chip microcomputer to which the present invention is applied. An outline of the configuration and operation of the single-chip microcomputer of this embodiment will be described first with reference to FIG. The circuit elements forming each block of FIG. 1 are formed on a single semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

In FIG. 1, a single-chip microcomputer of this embodiment is a central processing unit CPU of a stored program system and a random access memory R coupled to the central processing unit CPU via an internal bus IBUS.
AM, read only memory ROM, timer circuit TI
M and serial communication interface SC
I and a predetermined non-inverted clock signal CLKT
And a clock generation circuit CPG for receiving the inverted clock signal CLKB.

Here, the clock generation circuit CPG has a non-inverted clock signal CLKT and an inverted clock signal CLKB.
A predetermined internal clock signal is formed on the basis of and is supplied to the central processing unit CPU and the timer circuit TIM,
A part thereof, that is, the internal clock signal CP is supplied to the read-only memory ROM. In this embodiment, the single-chip microcomputer is in the high speed mode when the frequencies of the non-inverted clock signal CLKT and the inverted clock signal CLKB are relatively high, and in the low speed mode when the frequencies thereof are relatively low.

Next, the central processing unit CPU operates synchronously in accordance with the internal clock signal supplied from the clock generation circuit CPG, executes predetermined arithmetic processing in accordance with the program stored in the read-only memory ROM, and executes the single-chip micro-processor. Control and control each part of the computer. The random access memory RAM is
For example, it is composed of a static RAM having a predetermined storage capacity, and temporarily stores the calculation result and control data by the central processing unit CPU. Read-only memory ROM
Is a mask ROM having a predetermined storage capacity, and stores programs and fixed data necessary for controlling the central processing unit CPU.

In this embodiment, the internal bus IBUS of the single-chip microcomputer has a data bus of 16 bits, and the arithmetic processing by the central processing unit CPU is performed in units of 16 bits. Also,
The read-only memory ROM is 16
The unit read amplifier RA includes a read amplifier RA composed of unit read amplifiers URA0 to URA15, and each unit read amplifier includes a differential amplifier circuit DA centered on a pair of differential MOSFETs and a predetermined operating current to the differential amplifier circuit DA. Drive M to supply
And OSFET. Specific configurations of the read-only memory ROM and its read amplifier RA will be described later in detail.

The timer circuit TIM performs a predetermined time calculation process based on the internal clock signal supplied from the clock generation circuit CPG, and realizes the time management of the central processing unit CPU and a calendar function. Further, the serial communication interface SCI controls and manages continuous data exchange between a serial input / output device or the like coupled to the outside of the single chip microcomputer and the central processing unit CPU or the random access memory RAM.

FIG. 2 is a block diagram of an embodiment of the read only memory ROM included in the single chip microcomputer shown in FIG. Further, FIG. 3 shows an output characteristic diagram of an embodiment of the frequency-voltage conversion circuit FVC included in the read-only memory ROM of FIG. Based on these figures, an outline of the configuration and operation of the read-only memory ROM included in the single-chip microcomputer of this embodiment will be described.

In FIG. 2, the read-only memory ROM of this embodiment is composed of a so-called mask ROM, and has a memory array MARY which occupies most of the required layout area as a basic constituent element. Memory array M
The ARYs are arranged in a grid pattern at a plurality of word lines arranged in parallel in the vertical direction and a plurality of bit lines arranged in parallel in the horizontal direction and at intersections of these word lines and bit lines. And a large number of memory cells. These memory cells are composed of N-channel MOSFETs, and have selectively different threshold voltages by selectively changing the amount of impurities ion-implanted into the channel portion. That is, the memory cell has a relatively small threshold voltage when a relatively small amount of impurities are ion-implanted into its channel portion, and is a so-called low threshold voltage type N-channel MOSFET. At this time, the memory cell is supposed to hold data of logic "0", and a relatively large read current is flowed at the time of selection. On the other hand, when a relatively large amount of impurities are ion-implanted into the channel portion, the memory cell is assumed to have a relatively large threshold voltage, and acts as a so-called high threshold voltage type N-channel MOSFET. At this time, the memory cell is supposed to hold the data of logic "1", and a relatively small read current flows when selected.

The word lines forming the memory array MARY are coupled to the X address decoder XD and are selectively set to the high level. The X address decoder XD is supplied with i + 1-bit internal address signals X0 to Xi from the X address buffer XB. Further, in the X address buffer XB, X address signals AX0 to AXi are sent from a memory control circuit (not shown) of the single chip microcomputer via address input terminals AX0 to AXi.
Is supplied.

The X address buffer XB takes in and holds the X address signals AX0 to AXi supplied via the address input terminals AX0 to AXi, and holds the internal address signals X0 to Xi based on these X address signals.
Are formed and supplied to the X address decoder XD. The X address decoder XD decodes the internal address signals X0 to Xi supplied from the X address buffer XB, and selectively sets the corresponding word lines of the memory array MARY to the high level selected state.

Next, the bit lines forming the memory array MARY are the switch MOSF corresponding to the Y switch YS.
It is coupled to ET, and 16 lines are selectively connected to the common data lines CD0 to CD15 via the Y switch YS. The Y switch YS is a plurality of switch MOSFETs provided corresponding to each bit line of the memory array MARY.
including. The gates of these switch MOSFETs are sequentially connected in common to each other, and a corresponding bit line selection signal is supplied from the Y address decoder YD. The Y address decoder YD includes the Y address buffers YB through j + 1.
Bit internal address signals Y0 to Yj are supplied to the Y address buffer YB from a memory control circuit (not shown) of the single chip microcomputer via address input terminals AY0 to AYj.
AYj is supplied.

The Y address buffer YB fetches and holds the Y address signals AY0 to AYj supplied via the address input terminals AY0 to AYj, and at the same time, based on these Y address signals, the internal address signals Y0 to Yj.
Are formed and supplied to the Y address decoder YD. The Y address decoder YD decodes the internal address signals Y0 to Yj supplied from the Y address buffer YB, and selectively sets the corresponding bit line selection signal to the high level selected state. Switch MOSF that constitutes the Y switch YS
ET is selectively turned on 16 by 16 by setting the corresponding bit line selection signal to a high level, and selectively selects 16 corresponding bit lines of the memory array MARY and common data lines CD0 to CD15. To connect to.

The common data lines CD0 to CD15 are coupled to the input terminals of the corresponding unit read amplifiers of the read amplifier RA. A control voltage VG is commonly supplied from the frequency voltage conversion circuit FVC to these unit read amplifiers, and the output terminal thereof is coupled to the input terminal of the corresponding unit circuit of the data output buffer OB. Data output buffer OB
An internal control signal OE is commonly supplied to each unit circuit from the timing generation circuit TG, and its output terminal is coupled to the corresponding data output terminals D0 to D15. The frequency / voltage conversion circuit FVC is supplied with the internal clock signal CP from the clock generation circuit CPG, and the timing generation circuit T
An internal control signal CE is supplied from G. The internal control signal CE is selectively set to high level in response to the rise of the ROM enable signal ROEN, and the internal control signal O
E is selectively set to a high level in response to the rise of the ROM output enable signal ROOE.

The frequency-voltage conversion circuit FVC has an internal clock signal CP supplied from the clock generation circuit CPG and an internal control signal CE supplied from the timing generation circuit TG.
A predetermined control voltage VG is formed based on the above, and is supplied to each unit read amplifier of the read amplifier RA. In this embodiment, the potential of the control voltage VG output from the frequency-voltage conversion circuit FVC has a low level such as the ground potential of the circuit when the read-only memory ROM is in the non-selected state and the internal control signal CE is at the low level. When the read-only memory ROM is selected and the internal control signal CE is set to the high level, the internal clock signal C
It is selectively raised or lowered in proportion to the frequency of P. As a result, as shown in FIG. 3, the potential of the control voltage VG is F1 in which the single-chip microcomputer is in the high-speed mode and the frequency of the internal clock signal CP is relatively high.
Is set to a relatively high potential VG1, and the single-chip microcomputer is set to a low speed mode to set a relatively low potential VG2 when the internal clock signal CP is set to a relatively low frequency F2.

The read amplifier RA is connected to the common data line CD0.
16 unit read amplifiers URA0 to URA15 provided corresponding to CD15. These unit read amplifiers are selectively activated when the control voltage VG is set to the relatively high potential VG1 or the relatively low potential VG2, and the corresponding common memory cells are selected from the 16 memory cells selected in the memory array MARY. The read current output via the data lines CD0 to CD15 is converted into a voltage signal and amplified. The output signals of the unit read amplifiers URA0 to URA15, that is, the read signals RO0 to RO15 are supplied to the corresponding unit circuits of the data output buffer OB. In addition,
The specific configuration and operation of the read amplifier RA and its characteristics will be described later in detail.

The data output buffer OB includes 16 unit circuits provided corresponding to the unit read amplifiers URA0 to URA15 of the read amplifier RA. These unit circuits are selectively and simultaneously operated by setting the internal control signal OE to a high level, and the read amplifiers RA
The read signals RO0 to RO15 output from the corresponding unit read amplifiers of are further amplified and output to a memory control circuit (not shown) via the corresponding data output terminals D0 to D15.

The timing generation circuit TG forms the above various internal control signals based on the ROM enable signal ROEN and the ROM output enable signal ROOE supplied as the activation control signal from the memory control circuit of the single-chip microcomputer, Read-only memory RO
Supply to each part of M.

FIG. 4 shows the read-only memory R of FIG.
A circuit diagram of an embodiment of a read amplifier RA included in the OM is shown. Based on the figure, the read-only memory RO of the single-chip microcomputer of this embodiment
The specific configuration and operation of the read amplifier RA included in M and the characteristics of the single chip microcomputer of this embodiment will be described. In the figure, a MOSFET whose channel (back gate) part has an arrow
Is a P-channel type and is shown as distinguished from an N-channel MOSFET without an arrow.

In FIG. 4, the read amplifier RA includes 16 unit read amplifiers URA0 to URA15 provided corresponding to the common data lines CD0 to CD15. These unit read amplifiers are the unit read amplifiers URA0
As represented by the above, the current sense circuit CS and the differential amplifier circuit DA are respectively provided. Of these, the input terminal of the current sense circuit CS is coupled to the corresponding common data lines CD0 to CD15 as the input terminal of each unit read amplifier, and the non-inverted output signal of the differential amplifier circuit DA is the output of each unit read amplifier. Signals, that is, read signals RO0 to RO
It is supplied as 15 to the corresponding unit circuit of the data output buffer OB.

The current sense circuit CS of the unit read amplifiers URA0 to URA15 has a common data line CD corresponding to 16 selected memory cells of the memory array MARY.
The read current output through 0 to CD15 is converted into a voltage signal, that is, its output signal VS0 to VS15, and is transmitted to the corresponding differential amplifier circuit DA. In this embodiment, the potentials of the output signals VS0 to VS15 of the current sense circuit CS are not particularly limited, but it is assumed that the selected memory cell holds the data of logic "0" and the corresponding common data lines CD0 to CD15. Is set to a relatively high level when a relatively large read current is applied to the selected memory cell, and the selected memory cell holds data of logic "1". A relatively small read current is supplied to the corresponding common data lines CD0 to CD15. Is set to a comparatively low low level.

Next, the differential amplifier circuit DA includes a pair of N-channel type differential MOSFETs N1 and N2. The drains of these differential MOSFETs are coupled to the circuit power supply voltage through a pair of P-channel MOSFETs P1 and P2, and their commonly coupled sources are coupled to the circuit ground potential through an N-channel MOSFET N3. A predetermined reference potential VR is supplied from a constant voltage generating circuit (not shown) to the gate of the differential MOSFET N1, and output signals VS0 to VS15 of the corresponding current sense circuit CS are supplied to the gate of the differential MOSFET N2. The gates of the MOSFETs P1 and P2 are commonly coupled and then commonly coupled to the drain of the MOSFET P1, and the gate of the MOSFET N3 is coupled to the control voltage V.
G is supplied. It should be noted that the reference potential VR is set to an approximately intermediate level between the high level and the low level of the output signals VS0 to VS15 of the current sense circuit CS.

As a result, the MOSFETs P1 and P2 are
Acts as an active load for the differential MOSFETs N1 and N2, and the MOSFET N3 is a differential MOSF.
It functions as a drive MOSFET that gives a predetermined operating current according to the control voltage VG to ETN1 and N2. The drain potential of the differential MOSFET N2 is equal to the differential amplifier circuit D
Non-inverted output signal of A, that is, read signals RO0 to RO1
5 is supplied to the corresponding unit circuit of the data output buffer OB. As a result, the unit read amplifiers URA0 to URA0
Output signal of URA15, that is, read signals RO0 to RO
15 is selectively set to a high level or a low level according to the data held in the corresponding memory cell, that is, the output signals VS0 to VS15 of the corresponding current sense circuit CS.

That is, when the selected memory cell of the memory array MARY holds the data of logic "0" and the output signals VS0 to VS15 of the corresponding current sense circuit CS are set to the high level higher than the reference potential VR, the difference is generated. In the dynamic amplifier circuit DA, the corresponding differential MOSFET N2 is turned on and the differential MOSFET N1 is turned off. Therefore, the drain potential of the differential MOSFET N2, that is, the read signals RO0 to RO15 are set to a predetermined low level. On the other hand, the selected memory cell holds the data of logic "1" and outputs the output signal VS of the corresponding current sense circuit CS.
When 0 to VS15 are set to a low level lower than the reference potential VR, in the differential amplifier circuit DA, the corresponding differential MOSF
ETN2 is turned off, and differential MOSFET is used instead
N1 is turned on. Therefore, the differential MOSFET
The drain potential of N2, that is, the read signals RO0 to RO1
5 is set to a predetermined high level.

By the way, the unit read amplifiers URA0 to URA
As described above, the potential of the control voltage VG supplied to the gate of the drive MOSFET N3 of the RA15 is set to a relatively high potential VG1 when the single-chip microcomputer is set to the high speed mode, and is relatively low when it is set to the low speed mode. The potential is VG2. When the single-chip microcomputer is set to the high speed mode and the control voltage VG is set to the relatively high potential VG1, the unit read amplifiers URA0 to URA0.
In URA15, the drive MOSFET N3 is in a relatively strong ON state, and a relatively large operating current flows. For this reason,
Although the power consumption of the differential amplifier circuit DA is relatively large, the amplification operation of the read signal by the differential amplifier circuit DA is speeded up, thereby ensuring the high speed of the read amplifier RA and thus of the single-chip microcomputer.

On the other hand, the single-chip microcomputer is set to the low speed mode, and the control voltage VG has a relatively low potential V.
When set to G2, the unit read amplifiers URA0 to URA
At 15, the drive MOSFET N3 is in a relatively weak ON state, and a relatively small operating current is supplied to the differential amplifier circuit DA. Therefore, although the amplification operation of the read signal by the differential amplifier circuit DA is slightly delayed, the differential amplifier circuit DA
Of the read amplifier RA and thus of the single chip microcomputer is ensured. As a result, it is possible to realize a single-chip microcomputer that secures both the high speed that is emphasized in the high speed mode and the low power consumption that is emphasized in the low speed mode.

As shown in this embodiment, the present invention is applied to a semiconductor device such as a single-chip microcomputer having a built-in read-only memory and having a high speed mode and a low speed mode. The effect is obtained. (1) A single-chip microcomputer having a read-only memory and having a high-speed mode and a low-speed mode is provided with a frequency-voltage conversion circuit whose output potential is changed in proportion to the frequency of a clock signal. By supplying the output voltage of the voltage conversion circuit to the gates of the drive MOSFETs of the unit read amplifiers included in the read-only memory as the control voltage, the potential of the control voltage is increased in the high-speed mode to increase the read amplifier speed. In the low-speed mode of operation, the potential of the control voltage can be lowered to reduce the operating current of the read amplifier. (2) According to the above item (1), it is possible to realize a single-chip microcomputer or the like which secures both high speed in the high speed mode and low power consumption in the low speed mode.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the name of the low speed mode of the single chip microcomputer can be replaced with, for example, the low power consumption mode. In addition, the single chip microcomputer may include a mode control signal for selectively designating the high speed mode and the low speed mode. In this case, the potential of the control voltage VG supplied to the gate of the drive MOSFET N3 of each unit read amplifier of the read-only memory ROM may be selectively switched by the mode control signal. Random access memory R
Like the read amplifier RA, the AM can include a plurality of unit read amplifiers including a differential amplifier circuit and a driving MOSFET. In this case, the same potential switching is performed for the control voltage supplied to the gate of the drive MOSFET of the random access memory RAM to promote high speed in the high speed mode and low power consumption in the low speed mode of the single chip microcomputer. You can The bit configuration of the internal bus IBUS of the single chip microcomputer is 32 bits or 64 bits.
A bit structure can be adopted. In this case, the number of unit read amplifiers provided in the read amplifier RA is correspondingly increased, and the effect of the present invention is further enhanced. The single-chip microcomputer has a timer circuit TI
M and serial communication interface SCI
Is not an essential condition, and the block configuration can adopt various embodiments.

In FIG. 2, the memory array MARY is
For example, it can be divided into a plurality of sub memory arrays corresponding to the output data D0 to D15. In addition, the memory array MARY
The memory cell forming the memory cell may be configured to selectively hold data of logic "0" or logic "1" by, for example, selectively forming part of its wiring. The frequency-voltage conversion circuit FVC may be provided outside the read-only memory ROM, or may be shared by a plurality of blocks including a drive MOSFET serving as a current source. The block configuration of the read-only memory ROM and the combination of the activation control signal and the address signal are not restricted by this embodiment.

In FIG. 3, the frequency-voltage conversion circuit FVC
The output characteristic of is not required to be linear.
In FIG. 4, the data held in the selected memory cell of the memory array MARY and the output signal V of the current sense circuit CS.
Regarding the relationship with the logic levels of S0 to VS15, the read signals RO0 to RO15 are the differential MOSFE of the differential amplifier circuit DA.
You may invert it on condition that it is output as the drain potential of TN1. When the potential of the control voltage VG is controlled only by the frequency of the internal clock signal CP,
Another drive MOSF which is selectively turned on according to the internal control signal CE in series with the drive MOSFET N3.
ET should be provided. Unit read amplifiers URA0 to UR
A15 can be configured based on a bipolar transistor instead of the MOSFET. In this case, the potential of the control voltage supplied to the base of the transistor that also serves as the current source may be selectively switched according to the operation mode. Various embodiments can be adopted for the specific circuit configuration of the unit read amplifiers URA0 to URA15, the polarity of the power supply voltage, the conductivity type of the MOSFET, and the like.

In the above description, the case where the invention made by the present inventor is mainly applied to the single-chip microcomputer which is the field of application which is the background of the invention has been described. ECL including a single transistor as a only memory and a bipolar transistor serving as a current source
The present invention can also be applied to a logic integrated circuit device having an (Emitter Coupled Logic) circuit and an ECL circuit as a basic configuration. The present invention can be widely applied to semiconductor devices including at least a transistor serving as a current source.

[0040]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a single-chip microcomputer having a built-in read-only memory and having a high-speed mode and a low-speed mode is provided with a frequency-voltage conversion circuit whose output potential is changed in proportion to the frequency of a clock signal. The output voltage of is supplied as a control voltage to the gates of the drive MOSFETs of a plurality of unit read amplifiers included in the read-only memory, and in the high-speed mode, the potential of the control voltage is increased to operate the read amplifier at high speed. In low speed mode,
The operating current of the read amplifier can be reduced by lowering the potential of the control voltage. As a result, it is possible to realize a single-chip microcomputer or the like that secures both the high speed that is emphasized in the high speed mode and the low power consumption that is emphasized in the low speed mode.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a single-chip microcomputer to which the present invention is applied.

2 is a block diagram showing an embodiment of a read-only memory included in the single-chip microcomputer shown in FIG.

3 is an output characteristic diagram showing an embodiment of a frequency-voltage conversion circuit included in the read-only memory of FIG.

4 is a circuit diagram showing an embodiment of a read amplifier included in the read-only memory of FIG.

[Explanation of symbols]

CPU ... Central processing unit, CPG ... Clock generation circuit, IBUS ... Internal bus, RAM ... Random access memory, ROM ... Read-only memory,
TIM: timer circuit, SCI: serial communication interface. MARY ... Memory array, XD ... X address decoder, XB ... X
Address buffer, YS ... Y switch, YD ...
Y address decoder, YB ... Y address buffer,
RA ... Read amplifier, OB ... Data output buffer, FVC ... Frequency-voltage conversion circuit, TG ... Timing generation circuit. URA0 to URA15 ... Unit read amplifier, CS ... Current sense circuit, DA ... Differential amplifier circuit, P1-P2 ... P-channel MOSFE
T, N1 to N3 ... N-channel MOSFET.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 27/04 F 8427-4M

Claims (4)

[Claims] 1. A semiconductor comprising a transistor that acts as a current source when a gate or base thereof receives a predetermined control voltage, and the potential of the control voltage is selectively changed according to an operation mode. apparatus. 2. The semiconductor device has a high speed mode and a low speed mode, and the potential of the control voltage is
In the high speed mode, the value of the current passed through the transistor is set to be relatively large, and in the low speed mode, the value of the current passed through the transistor is set to be relatively small. The semiconductor device according to claim 1. 3. The semiconductor device is a single-chip microcomputer having a built-in read-only memory, the read-only memory comprises a plurality of read amplifiers, and the transistor has a difference between the read amplifiers. 2. A drive MOSFET for applying a predetermined operating current to the dynamic amplifier circuit.
Alternatively, the semiconductor device according to claim 2. 4. The semiconductor device is selectively set to the high-speed mode or the low-speed mode by increasing or decreasing the frequency of the clock signal, and the read-only memory is configured to output the clock signal of the clock signal. 4. The semiconductor device according to claim 1, further comprising a frequency-voltage conversion circuit that selectively switches the potential of the control voltage according to the frequency.