JPH0625932U - CPU board for parallel processing - Google Patents

Abstract

(57) [Summary] [Objective] To obtain a CPU board for parallel processing in which the waiting time for data transmission is shortened. [Structure] CPU section 11 having an input / output terminal to a system bus, dual port memory and memory control section 20 connected to the CPU section, CPU section 11 and dual port memory and memory control section 20 connected A data transmission driver 18 having an input / output terminal for a dedicated bus is provided, which is connected to the address decoder 12 for generating a select signal for controlling the dual port memory and the memory control unit 20.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a parallel processing CPU board applied to computer-controlled parallel processing.

[0002]

[Prior art]

 In a conventional computer, a plurality of CPU boards (CPU units) 1 are connected to a system bus 3 via address / data lines 2 as shown in FIG. Furthermore, a memory board 4 is likewise connected to the system bus 3.

Data transmission is sent to the memory board 4 via the system bus 3, and with respect to data transmission, only one CPU board 1 can be transmitted using the system bus 3 without fail.

[0004]

[Problems to be solved by the device]

 In the conventional CPU board described above, even if a plurality of boards are mounted on the system bus for parallel processing, the processing performance is improved according to the capacity of the CPU board, but data transmission is limited to one system board CPU board. Had to monopolize each time, and at that time, the other CPU boards waited until the system bus became empty. That is, there was a problem that the waiting time increased.

[0005]

[Means for Solving the Problems]

 The present invention takes the following measures to solve the above problems.

That is, as a CPU board for parallel processing, a CPU unit having an input / output terminal to a system bus, a dual port memory and a memory control unit connected to the CPU unit, the CPU unit and a dual port memory, An address decoder connected to the memory control unit for generating a select signal for judging transmitted / received data, and a data transmission driver connected to the dual port memory and the memory control unit and having an input / output terminal to a dedicated bus are provided.

[0007]

[Action]

 In the above means, for example, a plurality of parallel processing CPU boards are used and are connected to the system bus at the input / output terminals of the system bus. Further, in a predetermined pair of parallel processing CPU boards, the input / output terminals of the dedicated bus are connected to the dedicated bus. When connected and used in this way, for example, if the data generated by the first parallel processing CPU board is the last data and should be output, that data is output via the system bus. To be done. However, other data that requires further arithmetic processing is transmitted to another parallel processing CPU board via a dedicated data line and is newly processed as input data there. The reverse is also done.

In this way, the waiting time at the time of data transmission, which has been a bottleneck in the conventional CPU board configuration (because one CPU board has to monopolize the shared system bus, The CPU board then has no time to wait until the system bus is free. Also, by connecting the CPU boards required for parallel processing in the program with dedicated data lines, the processing performance improved according to the number of CPU units can be executed without being hindered by the data transmission time.

[0009]

【Example】

 An embodiment of the present invention will be described with reference to FIGS.

The parts described in the conventional example are denoted by the same reference numerals and the description thereof will be omitted, and the part related to the present invention will be mainly described.

In FIG. 1, an address decoder 12, a transmission dual port memory 13, a transmission controller 14, a reception controller 16 and a reception dual port memory 15 are connected to the CPU section 11. The address decoder 12 is connected to a transmission dual port memory 13, a transmission controller 14, a reception controller 16, and a reception dual port memory 15.

The transmission driver 18 of the data transmission driver 17 is connected to the transmission controller 14 and the transmission dual port memory 13. Further, the reception controller 19 of the data transmission driver 17 is connected to the reception dual port memory 15 for reception. These are the CPU boards 1a for parallel processing.

As shown in FIG. 2, the input / output terminal of the CPU section 11 of the parallel processing CPU board 1 a is connected to the system bus 3 via the address / data line 2. Further, for example, the input / output ends of the data transmission driver 17 between the substrate 1 and the substrate 2 of the parallel processing CPU substrate 1a are connected by the dedicated line 5.

In the above configuration, the CPU unit 11 performs arithmetic processing.

The address decoder 12 also generates a select signal for judging transmitted / received data. The dual port memory 13 for transmission receives an address, data and a write enable signal from the CPU section 11 and a select signal from the address decoder 12. In addition, a busy signal is sent to the CPU section 11 during writing to the memory. The transmission controller 14 is a control unit of the transmission dual-port memory 13, and receives an output enable signal from the CPU 11 and a select signal from the address decoder 12, receives the select signal to the transmission dual-port memory 13, and outputs the output enable signal. Generate a navel signal. The receiving dual-port memory 15 is similar to the transmitting dual-port memory 13, but receives the output enable signal instead of the write enable signal. The receiving controller 16 is a control unit of the receiving dual-port memory 15, and is similar to the transmitting controller 14, except that it receives a write enable signal instead of the output enable signal and receives a select signal to the receiving dual-port memory 15. Generate a write enable signal. The transmission driver 18 receives a transmission start signal from the transmission controller 14, receives data from the transmission dual port memory 13, and transmits the data. The reception driver 19 sends a data input signal to the reception controller 16, which serves as an interrupt signal from the reception controller 16 to the CPU section 11.

When a plurality of parallel CPU boards 1a having the above-mentioned functions are connected as shown in FIG. 2, even if the shared system bus 3 is exclusively used by another parallel processing CPU board 1a, Can be transmitted.

For example, if the data generated by the board 1 is the last data and is to be output, the data is transmitted to the memory board 4 via the system bus 3. However, other data that requires further arithmetic processing is transmitted to the board 2 via the dedicated data line 5 and is newly processed as input data to the parallel processing CPU board 1a.

On the contrary, the data can be input to the substrate 1 by using the dedicated data line 5.

That is, by using the parallel processing CPU board 1a having one CPU unit 11, the waiting time at the time of data transmission, which is a bottleneck in the conventional parallel processing CPU board configuration (shared Since one CPU board has to monopolize the system bus, it becomes possible for other CPU boards to eliminate the time required to wait until the system bus becomes available).

In this way, by connecting the CPU boards for parallel processing required for parallel processing in the program with dedicated data lines, the processing performance improved according to the number of CPUs can be executed without being hindered by the data transmission time. To be done.

Further, a data transmission driver 17 is further added to the parallel processing CPU board 1a and connected as shown in FIG. Then, the parallel processing is performed between the substrate 1 and the substrate 2 and between the substrate 1 and the substrate n, and the waiting time during data transmission is further shortened.

[0022]

[Effect of device]

 As described above, if a plurality of CPU boards for parallel processing of the present invention are used, data transmission can be performed without waiting for an empty state of the system bus. As a result, the computing power of the CPU unit can be fully utilized without being hindered by the waiting time for data transmission.

[Brief description of drawings]

FIG. 1 is a block diagram of a CPU board for parallel processing according to an embodiment of the present invention.

FIG. 2 is an explanatory view of the operation of the same embodiment.

FIG. 3 is an explanatory view of the operation of another embodiment of the present invention.

FIG. 4 is an explanatory diagram of a conventional example.

[Explanation of Codes] 1 CPU board 1a CPU board for parallel processing 2 Address / data line 3 System bus 4 Memory board 5 Dedicated line 11 CPU section 12 Address decoder 13 Transmit dual port memory 14 Transmit controller 15 Receive dual port memory 16 Reception controller 17 Data transmission driver 18 Transmission driver 19 Reception driver 20 Dual port memory and memory control unit

Claims (1)

[Scope of utility model registration request] 1. A CP having an input / output terminal for a system bus.
U unit, a dual port memory and memory control unit connected to the CPU unit, an address decoder connected to the CPU unit and dual port memory and memory control unit for generating a select signal for judging transmission / reception data, and the dual port A CPU board for parallel processing, comprising a data transmission driver connected to a memory and a memory control section and having an input / output terminal for a dedicated bus.