JPH06259039A - Liquid crystal display device - Google Patents

Abstract

(57) [Abstract] [Object] A liquid crystal display device including an active matrix liquid crystal display panel, in which the same pattern is continuously driven by alternating current drive without causing problems such as a decrease in aperture ratio and a decrease in yield. Even in the case of displaying, it is possible to display a high-quality image without afterimages and flicker. [Constitution] One pixel is composed of liquid crystal cells 25 and 26 in which a common electrode 29 is opposed to display electrodes 27 and 28 via a liquid crystal 30, and a liquid crystal cell 2 is arranged between data bus lines 31 and 32.
A voltage for driving Nos. 5 and 26 is applied.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a liquid crystal display panel (liqu
Among the id crystal display panels), the present invention relates to a liquid crystal display device including a so-called active matrix type liquid crystal display panel that is configured to cause pixels arranged in a matrix to perform a memory holding operation.

In recent years, C equipped with a CRT (cathode ray tube)
As a display device that replaces the RT display device, research and development of a liquid crystal display device including a liquid crystal display panel has been actively pursued.

In particular, an active matrix type liquid crystal display panel has a display quality comparable to that of a CRT.
A liquid crystal display device provided with this active matrix liquid crystal display panel is considered promising.

[0004]

[Prior art]

First Conventional Example ... FIG. 25 Conventionally, as a liquid crystal display device including an active matrix type liquid crystal display panel, there is known a liquid crystal display device including an active matrix type liquid crystal display panel whose circuit configuration of one pixel portion is shown in FIG. Has been.

In the figure, 1 is a liquid crystal cell, 2 is a display electrode (pixel electrode) provided for each pixel, 3 is a common electrode (common electrode) commonly provided for all pixels, and 4 is a liquid crystal. In this example, one liquid crystal cell 1 constitutes one pixel.

Further, 5 is a data bus line to which a data signal (display signal) is applied via a data driver (not shown), and 6 is a scan to which a scanning signal is applied via a scan driver (not shown). It is a bus line.

Further, 7 is a thin film transistor (hereinafter referred to as TFT) forming a switching element (active element) whose on / off is controlled by a scanning signal, and 8 is provided between the scan bus line 6 and the source of the TFT 7. Is the parasitic capacitance of.

Here, in writing to the liquid crystal cell 1, a data signal voltage is applied to the data bus line 5, and
The scan signal on the scan line 6 is turned on and TF
This is performed by turning on T7, applying a data signal voltage to the display electrode 2, and then turning off the TFT 7 when one horizontal scanning period has elapsed.

In this case, the liquid crystal cell 1 holds the applied data signal voltage until the writing in the next frame is performed, and displays the gray scale corresponding to the applied data signal voltage.

Second Conventional Example ... FIG. 26, FIG. 27 Further, as an LCD device having an active matrix type liquid crystal display panel, an active matrix type liquid crystal display panel having a circuit configuration of one pixel portion is shown in FIG. It is known to be equipped.

In the figure, 9 and 10 are liquid crystal cells, and 11 and
Reference numeral 12 is a display electrode, 13 is a common electrode provided in common to all pixels, and 14 is a liquid crystal. In this example, two liquid crystal cells 9 and 10 form one pixel.

Reference numeral 15 is a data bus line, 16 is a horizontal scan line (N line) scan bus line including this pixel, 17 is a next horizontal line (N + 1 line) scan bus line, and 18 and 19 are scan bus lines. A TFT whose on / off is controlled by 16 scanning signals.

Further, 20 is a TFT whose on / off is controlled by a scan signal of the scan bus line 17, 21 is a parasitic capacitance between the scan bus line 16 and the source of the TFT 18, and 22 is a scan bus line 16 and the TFT 19. It is the parasitic capacitance with the source.

FIG. 27 is a waveform diagram showing a part of the scan signal output by the scan driver included in the liquid crystal display device including the active matrix type liquid crystal display panel. FIG. 27A shows the scan bus line 16. 27B shows a scanning signal applied to the scan bus line 17, and FIG. 27B shows a scanning signal applied to the scan bus line 17.

That is, in this liquid crystal display device, the scanning signals applied to the adjacent scan bus lines of the horizontal lines of the active matrix type liquid crystal display panel are applied so that the ON voltages partially overlap.

Therefore, in the period t1, the TFTs 18 and 19 are
= ON, TFT 20 = OFF, and during period t2, TF
T18, 19, 20 = ON, and during period t3, TF
T18, 19 = OFF, TFT20 = ON.

As a result, for example, the TFT 19 is not turned on due to a failure, and the data bus line 1 is turned on during the period t1.
Even when the data signal voltage applied to 5 is not applied to the display electrode 12, the data signal voltage applied to the data bus line 15 passes through the TFT 18, the display electrode 11, and the TFT 20 in the period t2. It will be applied to the display electrode 12.

Therefore, according to this liquid crystal display device,
It is possible to achieve defect-free display, reduce the cost by improving the yield, and realize high-quality display without display defects.

[0019]

[Problems to be Solved by the Invention]

Problems of First Conventional Example ... FIGS. 28 and 29 FIG. 28 is for explaining problems of a liquid crystal display device (first conventional example) including the active matrix liquid crystal display panel shown in FIG. It is a waveform diagram of.

FIG. 28A is a scan signal applied to the scan bus line 6, and FIG. 28B is a data bus line 5.
28C shows the data signal applied to the display electrode 2 and the voltage of the display electrode 2 is shown in FIG.

That is, in this liquid crystal display device, when the scanning signal is changed from the ON voltage to the OFF voltage and the TFT 7 is changed from ON to OFF, the source potential of the TFT 7, that is, the voltage of the display electrode 2 is influenced by the parasitic capacitance 8. Shifts to the negative voltage side.

Therefore, when the same pattern is continuously displayed, the data signal voltage becomes asymmetric between the positive drive and the negative drive, and afterimages and flicker (flicker of screen) occur. There was a problem.

Incidentally, the shift amount Δ of the voltage of the display electrode 2
V is represented by Formula 1 where the capacitance value of the parasitic capacitance 8 is C _GS , the capacitance of the liquid crystal cell 1 is C _LC , and the difference between the on voltage and the off voltage of the scanning signal is ΔV _G.

[0024]

[Equation 1]

Therefore, conventionally, as indicated by a broken line 23 in FIG. 28C, the voltage (common voltage) to be applied to the common electrode 3 is shifted to the negative voltage side by ΔV, so that the positive drive and the negative drive are performed. A method has been proposed for realizing a symmetrical drive with respect to time.

However, the liquid crystal capacitance has voltage dependency, and the liquid crystal capacitance is different between white display and black display. Therefore, with this driving method, it is difficult to ensure sufficient symmetry between positive driving and negative driving.

Therefore, conventionally, as shown in FIG. 29, an auxiliary capacitance (holding capacitance) 24 having a smaller voltage dependence than the liquid crystal capacitance is provided in parallel with the liquid crystal cell 1, whereby the display electrode 2 by the parasitic capacitance 8 is provided. There has been proposed a method of reducing the voltage shift amount ΔV.

In this case, the shift amount Δ of the voltage of the display electrode 2
V becomes as shown in Equation 2 when the capacitance value of the auxiliary capacitance 24 is C _S.

[0029]

[Equation 2]

Even with this method, the shift amount ΔV cannot be completely eliminated, but the capacitance value C _{S of the} auxiliary capacitance 24 is reduced.
_Can be made sufficiently larger than the capacitance value C _LC of the liquid crystal cell 1, for example, a value larger by one digit or more, it is possible to make afterimages and flicker difficult to see.

However, writing to the auxiliary capacitance 24 having a large capacitance value is impossible with the current size of the TFT 7, and providing such an auxiliary capacitance 24 lowers the aperture ratio and complicates the process. Therefore, there is a problem in that the yield is reduced.

FIG. 30 shows a problem of the second conventional example. FIG. 30 shows a liquid crystal display device configured to drive the active matrix type liquid crystal display panel shown in FIG. 26 by the driving method shown in FIG. 27 (second conventional example). It is a wave form chart for explaining the problem which an example has.

FIG. 30 (A) is a scanning signal applied to the scan bus line 16, FIG. 30 (B) is a scanning signal applied to the scan bus line 17, and FIG. 30 (C) is a voltage of the display electrodes 11 and 12. Is shown.

That is, in this liquid crystal display device, when the scanning signal of the scan bus line 16 changes from the on-voltage to the off-voltage and the TFTs 18 and 19 change from on to off, the parasitic capacitances 21 and 22 influence the display electrode 11. , 12 are shifted to the low voltage side by ΔV.

Next, when the scan signal of the scan bus line 17 changes from the on voltage to the off voltage and the TFT 20 changes from on to off, the scan bus line 17 and the T bus are turned off.
Parasitic capacitance between drain and source of FT22 (not shown)
Due to the influence of, the voltage of the display electrodes 11 and 12 is further decreased by Δ.
It will shift by V.

As a result, in this liquid crystal display device,
The total shift amount of the voltage of the display electrodes 11 and 12 is doubled as compared with the case of the liquid crystal display device including the active matrix type liquid crystal display panel shown in FIG. 25, and afterimages and flicker are further reduced. There was a problem that it became obvious.

In view of the above point, the present invention can display a high-quality image without an afterimage and flicker even when the same pattern is continuously displayed by AC driving, and further, an auxiliary capacitance is provided. A first object of the present invention is to provide a liquid crystal display device including an active matrix liquid crystal display panel that does not cause problems such as a decrease in aperture ratio and a decrease in yield.

A liquid crystal display device including an active matrix type liquid crystal display panel of so-called 1 pixel 2 display electrode 3 transistor type as shown in FIG. 26, in which the same pattern is continuously displayed by AC driving. A second object is to provide a liquid crystal display device capable of displaying a high quality image by reducing the afterimage and flicker in some cases.

[0039]

[Means for Solving the Problems]

1st invention: FIG. 1 FIG. 1 is a diagram for explaining the principle of the first invention in the present invention.
2 shows a circuit configuration of one pixel portion of an active matrix type liquid crystal display panel included in the liquid crystal display device of the invention of FIG.

In the figure, 25 and 26 are liquid crystal cells, and 27 and 28.
Is a display electrode, 29 is a common electrode opposed to the display electrodes 27 and 28, and 30 is a liquid crystal. The liquid crystal cells 25 and 26 form one pixel.

The common electrode 29 is the display electrode 27,
It is provided only facing 28 and is electrically independent of the common electrodes of other pixels. That is, in the first aspect of the invention, the common electrode is provided for each pixel.

Further, 31 and 32 are data bus lines to which a voltage for driving the liquid crystal cells 25 and 26 is applied, and 3
3 is a scan bus line to which a scan signal is applied, 34,
35 is turned on by the scan signal of the scan bus line 33,
A transistor whose off state is controlled.

The transistors 34 and 35 are
Although it is composed of a MOS transistor using single crystal silicon, a TFT using a silicon thin film, etc., both a so-called N-channel type and a P-channel type can be used.

36 is a parasitic capacitance between the scan bus line 33 and the source of the transistor 34, and 37 is a parasitic capacitance between the scan bus line 33 and the source of the transistor 35.

That is, in the liquid crystal display device of the first invention, the common electrodes 29 are opposed to the display electrodes 27 and 28 with the liquid crystal 30 interposed therebetween to form the liquid crystal cells 25 and 26, and the display electrode 27 is connected to the transistor 34. The source and drain of the transistor 34 are connected to the data bus line 31 and the scan bus line 33, the display electrode 28 is connected to the source of the transistor 35, and the drain and gate of the transistor 35 are connected to the data bus. An active matrix type liquid crystal display panel which is connected to the line 32 and the scan bus line 33 and forms one pixel portion is provided, and a voltage for driving the liquid crystal cells 25 and 26 is applied between the data bus lines 31 and 32. Is configured as follows.

Second Invention FIG. 2 FIG. 2 is an explanatory view of the principle of the second invention in the present invention. In the figure, 38 is one pixel portion of an active matrix type liquid crystal display panel provided in the second invention. The circuit configuration of is shown.

Here, 39 and 40 are liquid crystal cells, and 41 and 4
Reference numeral 2 is a display electrode, 43 is a common electrode provided commonly to all pixels, and 44 is a liquid crystal. In this example, two liquid crystal cells 39 and 40 form one pixel.

Reference numeral 45 is a data bus line, 46 is a horizontal line (N line) scan bus line including this pixel, and 47 is a next horizontal line (N + 1 line) scan bus line.

Further, 48 and 49 are scan bus lines 4
6 is a transistor whose on / off is controlled by the scan signal 6. These transistors 48 and 49 are also composed of a MOS transistor using single crystal silicon, a TFT using a silicon thin film, and the like. Both N-channel type and P-channel type can be used. it can.

Reference numeral 50 designates a transistor whose on / off is controlled by a scan signal on the scan bus line 47.
1 is a parasitic capacitance between the scan bus line 46 and the source of the transistor 48, and 52 is a parasitic capacitance between the scan bus line 46 and the source of the transistor 49.

Reference numeral 53 is a scan driver, which is 5
Reference numeral 4 indicates a scan signal applied to the scan bus line 46 among the scan signals output from the scan driver 53, and reference numeral 55 indicates a scan signal applied to the scan bus line 47 among the scan signals output from the scan driver 53. Shows the signal.

Here, the scanning signal 54 is adapted to supply an on-voltage with two continuous square waves 56A and 56B, and the scanning signal 55 also has two continuous square waves 57.
The ON voltage is supplied by A and 58B.

Further, in the scanning signal 54 and the scanning signal 55, the falling timing of the square wave 56A coincides with the rising timing of the square wave 57A, and
Square wave 56B falling timing and square wave 57
The timing of the rising edge of B is matched.

That is, the scan driver 53 generates a scan signal for supplying the ON voltage in the form of continuous first and second square waves, and the scan signal of one scan bus line and the next scan. The scan signal of the bus line coincides with the falling timing of the first square wave of the scan signal of one scan bus line and the rising timing of the first square wave of the scan signal of the next scan bus line. In addition, the timing of the falling edge of the second square wave of the scan signal of one scan bus line and the timing of the rising edge of the second square wave of the scan signal of the next scan bus line are matched. It is configured to apply a scan signal to each scan bus line.

[0055]

[Action]

1st invention ... FIG. 1 In the 1st invention, in the 1st invention, the data bus lines 31, 3
A voltage for driving the liquid crystal cells 25 and 26 is applied between the two.

When the scan signal is turned on and the transistors 34 and 35 are turned on, the voltage of the display electrode 27 becomes the voltage applied to the data bus line 31, and the voltage of the display electrode 28 changes to the data. The voltage is applied to the bus line 32.

That is, the voltage between the display electrodes 27 and 28 becomes the same as the voltage between the data bus lines 31 and 32, and the liquid crystal cells 25 and 26 are capacitively divided between the data bus lines 31 and 32, respectively. It will hold half the applied voltage.

After that, when the scanning signal is turned off and the transistors 34 and 35 are turned off, the voltage of the display electrode 27 shifts to the low voltage side due to the parasitic capacitance 36, and the voltage of the display electrode 28 also changes. The parasitic capacitance 37 shifts to the low voltage side.

As described above, the voltages of the display electrodes 27 and 28 shift to the low voltage side, but since the parasitic capacitances 36 and 37 have the same capacitance value, the voltage shift amounts of the display electrodes 27 and 28 are also the same. Become.

As a result, even after the transistors 34 and 35 are turned off, the voltage between the display electrodes 27 and 28 is initially
The voltage applied between the data bus lines 31 and 32 is the same as the voltage applied between the data bus lines 31 and 32, so that the liquid crystal cells 25 and 26 also initially retain half of the voltage applied between the data bus lines 31 and 32. Become.

As described above, in the first invention, the liquid crystal cells 25 and 26 constituting one pixel are electrically connected in series with the other pixel via the common electrode 29 electrically independent from each other, and display is performed. By adopting a configuration in which a voltage between the data bus lines 31 and 32 is applied between the electrodes 27 and 28 via the transistors 34 and 35, parasitic capacitances 36 and 37 are formed.
It is possible to substantially cancel the voltage shift of the display electrodes 27 and 28 due to.

Therefore, according to the first aspect of the present invention, even when the same pattern is continuously displayed by the AC drive, the symmetry between the positive drive and the negative drive can be ensured, and the afterimage and Flicker can be eliminated and a high quality image can be displayed. In addition, the provision of the auxiliary capacitance does not cause problems such as a reduction in aperture ratio and a reduction in yield.

It is necessary to apply a voltage between the data bus lines 31 and 32 that is twice the voltage corresponding to the gradation to be displayed on the liquid crystal cells 25 and 26.
For example, it can be performed by applying first and second data signal voltages that are symmetrical to each other with respect to a predetermined reference voltage to the data bus lines 31 and 32.

Further, pixels adjacent to each other in the horizontal line direction with the data bus line 31 interposed therebetween use the data bus line 31 as their own data bus line 32, and the data bus line 3
The pixels adjacent to each other with the data bus 2 sandwiching the data bus line 32 using the data bus line 32 as its own data bus line 31,
A voltage for driving the liquid crystal cells 25 and 26 may be applied between 32.

The data bus line 32 is connected to a scan bus line other than the scan bus line 33, for example, the scan bus line of the previous horizontal line, and the voltage of the data bus line 32 is fixed to the off voltage of the scan signal. By applying a data signal voltage to the data bus line 31, the liquid crystal cells 25, 2 are connected between the data bus lines 31, 32.
It is also possible to apply a voltage for driving the drive circuit 6.

Further, a reference voltage bus line for applying a predetermined reference voltage is provided, the data bus line 32 is connected to the reference voltage bus line, the voltage of the data bus line 32 is fixed to the predetermined reference voltage, and By applying a data signal voltage to the bus line 31, a voltage for driving the liquid crystal cells 25 and 26 can be applied between the data bus lines 31 and 32.

In addition, a frame in which the voltage of the data bus line 32 is fixed to a predetermined reference voltage and a data signal voltage is applied to the data bus line 31, and the voltage of the data bus line 31 is fixed to a predetermined reference voltage, Bus line 32
By repeating the frame for applying the data signal voltage to the liquid crystal cell 2 between the data bus lines 31 and 32.
It can also be configured to apply a voltage for driving 5, 26.

Second Invention FIG. 2 In the second invention, the scan driver 5 is used in the second invention.
By 3, the scanning signal for supplying the ON voltage by the continuous first and second square waves is applied to the scan bus line.

In this case, the scan signal of one scan bus line and the scan signal of the next scan bus line are the timing of the falling edge of the first square wave of the scan signal of the one scan bus line, and While matching the rising timing of the first square wave of the scan signal of the scan canvas line, the second scan signal of the scan bus line
Each scanning signal is applied to each scan bus line so that the timing of the falling edge of the square wave and the timing of the rising edge of the second square wave of the scanning signal of the next scan bus line are matched.

For example, in FIG. 2, the scanning signal 54,
The scanning signal 55 matches the falling timing of the square wave 56A with the rising timing of the square wave 57A, and matches the falling timing of the square wave 56B with the rising timing of the square wave 57B. Thus, the scan bus lines 46 and 47 are applied.

As a result, when the square wave 56A of the scanning signal 54 falls, the voltages of the display electrodes 41 and 42 tend to shift to the low voltage side due to the influence of the parasitic capacitances 51 and 52.
In this case, since the square wave 57A of the scanning signal 55 rises, the parasitic capacitance between the scan bus line 47 and the drain and source of the transistor 50 causes the display electrode 41,
The voltage of 42 tends to shift to the high voltage side, and eventually the voltages of the display electrodes 41 and 42 do not change.

Next, when the square wave 56B of the scanning signal 54 falls, the display electrodes 4 are affected by the parasitic capacitances 51 and 52.
The voltages of 1 and 42 try to shift to the low voltage side, but in this case, since the square wave 57B of the scanning signal 55 rises, the parasitic capacitance between the scan bus line 47 and the drain and source of the transistor 50 causes display. Electrodes 41, 4
The voltage of 2 tends to shift to the high voltage side, and eventually the voltages of the display electrodes 41 and 42 do not change.

Next, when the square wave 57B of the scan signal 55 falls, the scan bus line 47 and the transistor 5
Due to the parasitic capacitance between the drain and the source of 0, the voltages of the display electrodes 41 and 42 are shifted to the low voltage side as shown by the solid line 58.

As described above, according to the second aspect of the invention, in the liquid crystal display device including the so-called one-pixel two-display-electrode-three-transistor-type active-matrix liquid crystal display panel, the voltage shift of the display electrodes 41 and 42 is performed. The amount can be suppressed to 1/2 of the conventional case.

[0075]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The first to sixth embodiments of the present invention will be described below with reference to FIGS. In addition, 1st Example-5th Example is an Example of 1st invention in this invention, 6th Example is an Example of 2nd invention.

First Embodiment FIG. 3 to FIG. 6 FIG. 3 is a diagram showing a circuit configuration of a part of an active matrix type liquid crystal display panel provided in the first embodiment of the present invention, in which 60 to 67 are shown. Liquid crystal cells, 68 to 75 are display electrodes, 76 to 79 are common electrodes electrically independent of each other, and 80 is a liquid crystal.

In this first embodiment, the liquid crystal cells 60, 61
The R (red) pixel 81 is constituted by the liquid crystal cells 62, 63.
The G (green) pixel 82 is formed of the liquid crystal cells 64 and 65.
B (blue) pixel 83 is constituted by the liquid crystal cells 66, 67.
The R pixel 84 is constituted by.

Further, 85 to 92 are data bus lines, and 9
3 is a scan bus line, and 94 to 101 are turned on and off by a scan signal of the scan bus line 93.
It is FT.

FIG. 4 is a diagram showing the overall configuration of the first embodiment of the present invention. In the figure, 102 is the active matrix type liquid crystal display panel shown in FIG. 3, and 103 is an odd-numbered data bus line. Analog data driver, 104
Is an analog data driver that drives even-numbered data bus lines, and 105 is a scan driver that drives scan bus lines.

Also, 106 clamps the RGB signals,
These RGB signals are amplified in accordance with the transmittance-voltage characteristic (TV characteristic) of the liquid crystal, and the reference voltage Vref, for example, 0 is amplified.
This is a data processing unit that generates two data signals A and B which are line-symmetric with respect to [V], and switches between positive and negative of these data signals A and B for each frame by an alternating signal and outputs.

FIG. 5 is a diagram showing the characteristics of the data processing unit 106. The characteristics of the data processing unit 106 may be linear as indicated by the straight line 107, and the curves 108, 1
It may be gamma-corrected as shown in FIG.

In FIG. 4, 110 is a sampling signal to be supplied to the analog data drivers 103 and 104 based on the vertical synchronizing signal VS and the horizontal synchronizing signal HS, a timing signal to be supplied to the scan driver 105, and data processing. The timing controller outputs an AC signal to be supplied to the unit 106.

FIG. 6 is a waveform diagram showing the operation of the first embodiment, and shows an example of writing to the R pixel 81 in FIG. 6A is a scan signal applied to the scan bus line 93, and FIG. 6B is a data signal A applied to the data bus line 85.
(C) shows the voltage of the display electrode 68.

FIG. 6D shows the data bus line 86.
The data signal B applied to the display electrode 69 is shown in FIG.
6F, the voltage held in the liquid crystal cell 60,
FIG. 6G shows the voltage held in the liquid crystal cell 61.

Here, when writing to the R pixel 81, as shown in FIG. 6A, the scanning signal is turned on, the TFTs 94 and 95 are turned on, and at the same time, as shown in FIG. ) And (D), positive and negative symmetrical data signals A and B having a voltage difference twice the voltage to be held in the liquid crystal cells 60 and 61 are applied to the data bus lines 85 and 86, respectively.

For example, each of the liquid crystal cells 60 and 61 has five
When holding [V], the data signal A of +5 [V] is applied to the data bus line 85, and the data signal B of -5 [V] is applied to the data bus line 86.

By doing so, the liquid crystal cells 60, 61 are formed.
, Respectively, due to capacity division, {+5-(-5)}
/ 2 = 10/2 = 5 [V] voltage is applied,
The voltage of [V] is held.

Here, when the scanning signal is changed from the ON voltage to the OFF voltage and the TFTs 94 and 95 are changed from ON to OFF, the source voltage of the TFT 94, that is, the voltage of the display electrode 68 is the same as that of the scan bus line 93 and the TFT 94. Due to the influence of the parasitic capacitance with the source, as shown in FIG. 6C, the voltage shifts to the lower potential side by ΔV.

The source voltage of the TFT 95, that is, the voltage of the display electrode 69 is the same as that of the scan bus line 93 and the TFT.
Due to the influence of the parasitic capacitance with the source of 95, as shown in FIG. 6E, the voltage shifts to the low potential side by ΔV.

As described above, the voltages of the display electrodes 68 and 69 shift to the low voltage side, but the scan bus line 93 and the T
Since the capacitance value of the parasitic capacitance between the FT 94 and the source is the same as the capacitance value of the parasitic capacitance between the scan bus line 93 and the source of the TFT 95, the shift amount ΔV of the voltage of the display electrodes 68 and 69 is also the same. Will be the same.

As a result, even after the TFTs 94 and 95 are turned off, the voltage between the display electrodes 68 and 69 is initially the same as the voltage applied between the data bus lines 85 and 86, and the liquid crystal cell 60, 61 also initially had a data bus line 8
Half of the voltage applied between 5 and 86 is continuously held.

As described above, in the first embodiment, the liquid crystal cells 60 and 61 constituting one pixel are electrically connected in series with the other pixel via the common electrode 76 which is electrically independent, and display is performed. By adopting a configuration in which a voltage between the data bus lines 85 and 86 is applied between the electrodes 68 and 69 via the TFTs 94 and 95, display by the parasitic capacitance between the scan bus line 93 and the sources of the TFTs 94 and 95 is performed. The voltage shift of the electrodes 68, 69 can be substantially canceled.

Therefore, according to the first embodiment, even when the same pattern is continuously displayed by the AC drive, it is possible to secure the symmetry between the positive drive and the negative drive, and the afterimage and Flicker can be eliminated and a high quality image can be displayed. In addition, the provision of the auxiliary capacitance does not cause problems such as a reduction in aperture ratio and a reduction in yield.

Second Embodiment ... FIGS. 7 to 13 FIG. 7 is a diagram showing a circuit configuration of a part of an active matrix type liquid crystal display panel included in the second embodiment of the present invention, in which 111 to 118 are shown. Liquid crystal cell, 119 to 126
Is a display electrode, 127 to 130 are common electrodes electrically independent of each other, and 131 is a liquid crystal.

In this second embodiment, the liquid crystal cells 111, 1
The R pixel 132 is composed of 12 and the liquid crystal cells 113 and 11
4 constitutes the G pixel 133, and the liquid crystal cells 115 and 116 are formed.
Constitutes a B pixel 134, and the liquid crystal cells 117 and 118 constitute an R pixel 135.

Further, 136 to 140 are data bus lines, 141 is a scan bus line, and 142 to 149 are TFTs whose on / off are controlled by the scan signal of the scan bus line 141.

That is, in this second embodiment, the R pixel 132
And the G pixel 133 share the data bus line 137,
The pixel 133 and the B pixel 134 share the data bus line 138, and the B pixel 134 and the R pixel 135 share the data bus line 139.

FIG. 8 is a diagram showing the overall construction of the second embodiment of the present invention. In the figure, 150 is the active matrix type liquid crystal display panel shown in FIG. 7, and 151 is driving the even-numbered data bus lines. It is an analog data driver.

Reference numeral 152 is an analog data driver for driving the odd-numbered data bus lines except the first data bus line 136, and the reference voltage Vref is applied to the first data bus line 136.

Further, 153 is a scan driver for driving the scan bus line, 154 is a clamp for RGB signals, and these RGB signals are amplified in accordance with the characteristics described later to generate a data signal. It is a data processing unit that switches and outputs each frame according to an alternating signal.

Reference numeral 155 denotes the analog data driver 1
Sampling signals A and B to be supplied to 51 and 152,
The timing controller outputs a timing signal to be supplied to the scan driver 153 and an AC signal to be supplied to the data processing unit 154.

FIG. 9 is a diagram showing the circuit configuration of the data processing unit 154. In the figure, reference numeral 156 is an RGB signal amplifier that clamps RGB signals and amplifies these RGB signals based on the characteristics shown in FIG.

That is, the RGB signal amplifying section 156 assumes that the transmittance-voltage characteristic of the liquid crystal is as shown in FIG.
When [V] is output and a white level signal is input,
It has a characteristic of outputting 4 [V].

It should be noted that there is a gap between the black level and the white level in FIG.
0 may be linear as indicated by a straight line 157, curve 15
It may be gamma-corrected as indicated by 8, 159.

In FIG. 9, reference numeral 160 denotes a delay circuit having a delay time of 1/3 of the period in which the RGB signal for one dot is output from the RGB signal amplification section 156.
Reference numerals 61 to 163 are addition / subtraction circuits.

When the reference voltage Vref> the output of the delay circuit 160, the adder / subtractor circuits 161 to 163 operate as an adder circuit, and when the reference voltage Vref <the output of the delay circuit 160, the adder / subtractor circuit 161 functions as a subtractor circuit. Operates and the reference voltage Vre
When f = the output of the delay circuit 160, the operation is determined by the alternating signal, and when the alternating signal = H level, it operates as an adding circuit, and when the alternating signal = L level,
It operates as a subtraction circuit.

Further, 164 is 1/1 of the period during which the RGB signal for one dot is output from the RGB signal amplifier 156.
With the period of 3 as the switching cycle, switching of the contacts to be connected by the contacts 164A is performed by changing the contacts 164B → 164C → 16.
It is a switch circuit which is repeatedly performed in the order of 4D → 164B.

165 is a contact point 165 during the blanking period.
A is connected to the contact 165B, the reference voltage Vref is supplied to the delay circuit 160, and the contact 165A is connected to the contact 1 during the display period.
The switch circuit is connected to 65C and supplies the output of the switch circuit 164 to the delay circuit 160.

FIG. 12 is a waveform diagram showing the operation of the second embodiment, where the reference voltage Vref is set to 0 [V], for example, in FIG.
3 shows an example in which bright display is performed on the B pixel 134, bright display is performed on the B pixel 134, and dark display is performed on the R pixel 135.

That is, each of the liquid crystal cells 111 and 112 is 5 [V], and each of the liquid crystal cells 113 and 114 is 2 [V].
[V], 2 [V] in the liquid crystal cells 115 and 116,
An example is shown in which the liquid crystal cells 117 and 118 hold 5 [V] respectively.

FIG. 12A shows the RGB signal amplifier 1
The R signal output from 56, the G signal output from the RGB signal amplifier 156 in FIG. 12B, and the R signal in FIG.
The B signal output from the GB signal amplifier 156 is shown.

FIG. 12D shows the sampling signal A supplied to the analog data driver 151, and FIG.
(E) shows the sampling signal B supplied to the analog data driver 152.

Here, in the period Ta, the switch circuit 16
4 selects the output of the adder / subtractor circuit 161, but in this case, the R signal output from the RGB signal amplifier 156 is
Since the R pixel 132 is a dark display, the voltage is 10 [V].

Also, during this period Ta, the output of the delay circuit 160 is 0 [V], which is the same as the reference voltage 0 [V]. Therefore, the operation of the adder / subtractor circuit 161 is determined by the alternating signal, In the frame, the alternating signal is set to the H level, for example. Therefore, the adder / subtractor circuit 16
1 operates as an adding circuit, and its output is 10 [V].

This voltage is taken into the analog data driver 151 at the falling edge of the sampling signal A, applied to the data bus line 137 and supplied to the delay circuit 160 as shown in FIG. 13, and the RGB signal is amplified. The delay circuit 160 is delayed by 1/3 of the period in which the RGB signal for one dot is output from the unit 156.
Is output from.

In the next period Tb, the switch circuit 164 selects the output of the adder / subtractor circuit 162. In this case, RG
The G signal output from the B signal amplification unit 156 is the G pixel 1
Since 33 is a bright display, it becomes 4 [V].

Also, during this period Tb, the output of the delay circuit 160 = 10 [V] and the reference voltage 0 [V] <the output of the delay circuit 160. Therefore, the adder / subtractor circuit 162 operates as a subtractor circuit, and the adder / subtractor The output of the circuit 162 is 10
[V] −4 [V] = 6 [V].

This voltage is taken in by the analog data driver 152 at the falling edge of the sampling signal B, applied to the data bus line 138 and supplied to the delay circuit 160, and the RGB signal is amplified, as shown in FIG. The delay circuit 160 is delayed by 1/3 of the period in which the RGB signal for one dot is output from the unit 156.
Is output from.

In the next period Tc, the switch circuit 164 selects the output of the addition / subtraction circuit 163. In this case, RG
The B signal output from the B signal amplifier 156 is the B pixel 1
Since 34 is displayed in white, it becomes 4 [V].

Further, in this period Tc, the output of the delay circuit 160 = 6 [V] and the reference voltage 0 [V] <the output of the delay circuit 160. Therefore, the adder / subtractor circuit 163 operates as a subtractor circuit, and the adder / subtractor is added. The output of the circuit 163 is 6 [V]-
4 [V] = 2 [V].

This voltage is taken into the analog data driver 151 at the falling edge of the sampling signal A, applied to the data bus line 139 and supplied to the delay circuit 160, and the RGB signal is amplified as shown in FIG. The delay circuit 160 is delayed by 1/3 of the period in which the RGB signal for one dot is output from the unit 156.
Is output from.

In the next period Td, the switch circuit 164
Again selects the output of the adder / subtractor circuit 161, but in this case, the G signal output from the RGB signal amplifier 156 is 10 [V] because the R pixel 135 is in dark display.
Becomes

Also, during this period Td, the output of the delay circuit 160 = 2 [V], and the reference voltage 0 [V] <the output of the delay circuit 160. Therefore, the adder / subtractor circuit 161 operates as a subtractor circuit, and the adder / subtractor is added. The output of the circuit 161 is 2 [V].
-10 [V] =-8 [V].

This voltage is taken in by the analog data driver 152 at the falling edge of the sampling signal B, applied to the data bus line 140 and supplied to the delay circuit 160 as shown in FIG. The delay circuit 160 is delayed by 1/3 of the period in which the RGB signal for one dot is output from the unit 156.
Is output from.

As a result, as shown in FIG. 13, the voltage difference between the data bus lines 136 and 137 is 10 [V] −0.
[V] = 10 [V], data bus lines 137, 138
The voltage difference between them is 10 [V] −6 [V] = 4 [V], and the voltage difference between the data bus lines 138 and 139 is 6 [V] −.
2 [V] = 4 [V], data bus lines 139 and 140
The voltage difference between them is 2 [V]-(-8 [V]) = 10 [V]
Becomes

Therefore, the liquid crystal cells 111 and 112 each have 5 [V], the liquid crystal cells 113 and 114 each have 2 [V], and the liquid crystal cells 115 and 116 each have 2 [V].
[V] and 5 [V] for the liquid crystal cells 117 and 118, respectively.
Is applied.

Also in the second embodiment, for example, in the R pixel 132, the liquid crystal cells 111 and 112 forming one pixel are electrically connected to each other via the common electrode 127 which is electrically independent from the other pixels. The display electrodes 119 and 120 are connected in series and the voltage between the data bus lines 136 and 137 is applied between the display electrodes 119 and 120 via the TFTs 142 and 143.

As a result, the scan bus lines 141 and T
The shift of the voltage of the display electrodes 119 and 120 due to the parasitic capacitance between the FTs 142 and 143 sources can be substantially canceled. The same applies to other pixels.

Therefore, according to the second embodiment as well,
Similar to the case of the first embodiment, even when the same pattern is continuously displayed by the AC drive, the symmetry between the positive drive and the negative drive can be secured, the afterimage and the flicker can be eliminated, and Quality images can be displayed. In addition, the provision of the auxiliary capacitance does not cause problems such as a reduction in aperture ratio and a reduction in yield.

Third Embodiment FIG. 14 to FIG. 16 FIG. 14 is a diagram showing a circuit configuration of a part of a liquid crystal display panel provided in a third embodiment of the present invention, in which 166 to 1 are shown.
73 is a liquid crystal cell, 174 to 181 are display electrodes, and 182 to 182.
185 is a common electrode that is electrically independent of each other, and 1
Reference numeral 86 is a liquid crystal.

In this third embodiment, the liquid crystal cells 166, 1
67 constitutes an R pixel 187, and liquid crystal cells 168, 16
9 constitutes a G pixel 188, and liquid crystal cells 170 and 171 are formed.
Constitutes a B pixel 189, and the liquid crystal cells 172 and 173 constitute an R pixel 190.

191 to 198 are data bus lines, 199 is the scan bus line of the previous horizontal line, 2
00 is a horizontal scan bus line including this pixel, and 201 to 208 are TFTs whose on / off is controlled by the scan signal of the scan bus line 200. In the third embodiment, the data bus lines 192, 194, 1
96 and 198 are connected to the scan bus line 199.

FIG. 15 is a diagram showing the overall construction of the third embodiment of the present invention. In the figure, 209 is the active matrix type liquid crystal display panel shown in FIG. 14, 210 is the odd-numbered data bus line. Analog data driver, 2
A scan driver 11 drives the scan bus line.

Further, 212 clamps RGB signals,
A data processing unit that amplifies these RGB signals according to the characteristics shown in FIG. 16 and outputs positive and negative data signals for each frame based on the alternating signal.

The characteristics of the data processing unit 212 are shown in FIG.
6 may be linear, as indicated by the straight line 213, curve 21
It may be gamma-corrected as shown in FIGS.

In FIG. 15, reference numeral 216 denotes a sampling signal to be supplied to the analog data driver 210 based on the vertical synchronizing signal VS and the horizontal synchronizing signal HS, a timing signal to be supplied to the scan driver 211, and a data processing section 212. It is a timing controller that outputs an alternating signal to be supplied.

That is, in the third embodiment, a data signal is applied to the left data bus line in the figure of each pixel, and an off voltage of the scanning signal is applied to the right data bus line in the figure. Driven.

For example, in the R pixel 187, the data signal is applied to the data bus line 191, and the off voltage of the scan signal of the scan bus line 199 is applied to the data bus line 192 to drive the data signal.

Also in the third embodiment, for example, in the R pixel 187, the liquid crystal cells 166 and 167 forming one pixel are electrically connected to each other via the common electrode 182 which is electrically independent from the other pixels. The display electrodes 174 and 175 are connected in series and the voltage between the data bus lines 191 and 192 is applied between the display electrodes 174 and 175 via the TFTs 201 and 202.

As a result, the scan bus lines 200 and T
The voltage shift of the display electrodes 174 and 175 due to the parasitic capacitance between the sources of the FTs 201 and 202 can be substantially canceled. The same applies to other pixels.

Therefore, according to the third embodiment as well,
Similar to the case of the first embodiment, even when the same pattern is continuously displayed by the AC drive, the symmetry between the positive drive and the negative drive can be secured, the afterimage and the flicker can be eliminated, and Quality images can be displayed. In addition, the provision of the auxiliary capacitance does not cause problems such as a reduction in aperture ratio and a reduction in yield.

Fourth Embodiment FIG. 17 to FIG. 19 FIG. 17 is a diagram showing a circuit configuration of a part of an active matrix type liquid crystal display panel provided in a fourth embodiment of the present invention, and 217 to 224 in the figure. Liquid crystal cell, 225-232
Is a display electrode, 233 to 236 are common electrodes electrically independent of each other, and 237 is a liquid crystal.

In this fourth embodiment, the liquid crystal cells 217, 2
18 constitutes an R pixel 238, and liquid crystal cells 219, 22
0 constitutes a G pixel 239, and liquid crystal cells 221 and 222 are formed.
Constitutes a B pixel 240, and the liquid crystal cells 223 and 224 constitute an R pixel 241.

242 to 249 are data bus lines, 250 is a scan bus line, 251 is a next scan bus line, 252 is a reference voltage bus line to which a reference voltage Vref is applied, and 253 to 260 are scan bus lines 250. TF whose on / off is controlled by the scanning signal
T, and in the fourth embodiment, the data bus lines 243, 245, 247, 249 are connected to the reference voltage bus line 252.

FIG. 18 is a diagram showing the entire structure of the fourth embodiment of the present invention. In the figure, 261 is the active matrix type liquid crystal display panel shown in FIG. 17, and 262 is an odd numbered data bus line. It is an analog data driver.

Further, reference numeral 263 is a scan driver for driving the scan bus line, and 264 is a clamp for RGB signals. The RGB signals are amplified in accordance with the characteristics shown in FIG. The data processing unit outputs a data signal.

The characteristics of the data processing unit 264 are shown in FIG.
9 may be linear, as indicated by the straight line 265,
It is also possible to apply gamma correction as shown in Nos. 6,267.

In FIG. 18, reference numeral 268 denotes a sampling signal to be supplied to the analog data driver 262 based on the vertical synchronizing signal VS and the horizontal synchronizing signal HS, a timing signal to be supplied to the scan driver 263, and a data processing section 264. It is a timing controller that outputs an alternating signal to be supplied to.

That is, in the fourth embodiment, a data signal is applied to the left data bus line in the figure of each pixel, and the reference voltage Vre is applied to the right data bus line in the figure.
It is driven by applying f.

For example, in the R pixel 238, a data signal is applied to the data bus line 242, and the reference voltage Vref of the reference voltage bus line 252 is applied to the data bus line 243 to drive it.

Also in the fourth embodiment, for example, in the R pixel 238, the liquid crystal cells 217 and 218 constituting one pixel are electrically connected via the common electrode 233 electrically isolated from other pixels. The display electrodes 225 and 226 are connected in series and a voltage is applied between the data bus lines 242 and 243 via the TFTs 253 and 254.

As a result, the scan bus lines 250 and T
The shift of the voltage of the display electrodes 225 and 226 due to the parasitic capacitance between the sources of the FTs 253 and 254 can be substantially canceled. The same applies to other pixels.

Therefore, according to the fourth embodiment as well,
Similar to the case of the first embodiment, even when the same pattern is continuously displayed by the AC drive, the symmetry between the positive drive and the negative drive can be secured, the afterimage and the flicker can be eliminated, and Quality images can be displayed. In addition, the provision of the auxiliary capacitance does not cause problems such as a reduction in aperture ratio and a reduction in yield.

Fifth Embodiment FIG. 20 to FIG. 22 FIG. 20 is a diagram showing a circuit configuration of a part of an active matrix type liquid crystal display panel provided in the fifth embodiment of the present invention, in which 269 to 276 are shown. Liquid crystal cell, 277-284
Is a display electrode, 285 to 288 are common electrodes electrically independent of each other, and 289 is a liquid crystal.

In the fifth embodiment, liquid crystal cells 269 and 2 are provided.
The R pixel 290 is composed of 70, and liquid crystal cells 271 and 27
2, the G pixel 291 is formed, and the liquid crystal cells 273 and 274 are formed.
Constitutes a B pixel 292, and the liquid crystal cells 275 and 276 constitute an R pixel 293.

Further, 294 to 301 are data bus lines, 302 is a scan bus line, and 303 to 310 are TFTs whose on / off are controlled by the scan signals of the scan bus line 302.

FIG. 21 is a diagram showing the overall configuration of the fifth embodiment of the present invention. In the figure, 311 drives the active matrix type liquid crystal display panel shown in FIG. 20, and 312 drives the odd-numbered data bus lines. Analog data driver, 3
An analog data driver 13 drives even-numbered data bus lines.

Here, the analog data driver 312
Are controlled by the switching signal A, for example, the data signal sampled by the sampling signal is output in an odd frame, and the reference voltage V is output in an even frame.
It is configured to output ref.

Further, the analog data driver 313 is
It is controlled by the switching signal B,
The reference voltage Vref is output, and the data signal sampled by the sampling signal is output in an even frame.

Further, 314 is a scan driver for driving the scan bus line, and 315 is a data processing unit for clamping RGB signals and outputting a data signal obtained by amplifying these RGB signals according to the characteristics shown in FIG. .

The characteristics of the data processing unit 315 are shown in FIG.
2 may be linear, as indicated by the straight line 316, curve 31
Gamma correction may be performed as shown in Nos. 7 and 318.

In FIG. 21, reference numeral 319 denotes sampling signals and switching signals A and B to be supplied to the analog data drivers 312 and 313 based on the vertical synchronizing signal VS and horizontal synchronizing signal HS, and to the scan driver 314. It is a timing controller that outputs a timing signal.

That is, in the fifth embodiment, in the odd frame, the data signal is applied to the odd data bus lines and the reference voltage Vref is applied to the even data bus lines.
In the even-numbered frame, the reference voltage Vref is applied to the odd-numbered data bus lines, and the data signal is applied to the even-numbered data bus lines to perform AC driving.

Also in the fifth embodiment, for example, in the R pixel 290, the liquid crystal cells 269 and 270 forming one pixel are electrically connected via the common electrode 285 which is electrically independent from other pixels. In this configuration, the voltage is applied between the data bus lines 294 and 295 between the display electrodes 277 and 278 through the TFTs 303 and 304.

As a result, the scan bus lines 302 and T
The shift of the voltage of the display electrodes 277 and 278 due to the parasitic capacitance between the sources of the FTs 303 and 304 can be substantially canceled. The same applies to other pixels.

Therefore, according to the fifth embodiment as well,
Similar to the case of the first embodiment, even when the same pattern is continuously displayed by the AC drive, the symmetry between the positive drive and the negative drive can be secured, the afterimage and the flicker can be eliminated, and Quality images can be displayed. In addition, the provision of the auxiliary capacitance does not cause problems such as a reduction in aperture ratio and a reduction in yield.

Sixth Embodiment FIG. 23, FIG. 24 FIG. 23 shows an essential part of a sixth embodiment of the present invention, that is, an example of an example of a scan driver 53 (see FIG. 2) provided in the second invention. It is a figure which shows a circuit structure.

In the figure, reference numeral 320 denotes a serial input / parallel output type shift register for sequentially shifting the start signal ST1 in synchronization with the clock signal SCLK1, 321 ₁ , 321 _2.
... 321 _n is a 1-bit portion of the shift register 320.

Reference numeral 322 denotes a serial input / parallel output type shift register 323 ₁ 323 ₂ which sequentially shifts the start signal ST2 in synchronization with the clock signal SCLK2.
.. 323 _n is a 1-bit portion of the shift register 322.

Further, 324 ₁ , 324 _2, ..., 324 _n perform OR processing on the signals output from the same bit of the shift registers 320, 322, and scan signals 325 ₁ , 325 _2, ... Of each scan bus line. This is an OR circuit that generates 325 _n .

FIG. 24 is a waveform diagram showing the operation of the scan driver shown in FIG. 23. FIG. 24A shows the clock signal SCLK1 supplied to the shift register 320, and FIG.
(B) shows the clock signal SCLK2 supplied to the shift register 322.

Further, FIG. 24C shows the shift register 32.
24 shows the start signal ST1 supplied to 0, and FIG. 24 (D) shows the start signal ST2 supplied to the shift register 322.

FIG. 24E shows the shift register 32.
Signal output from the first bit 321 ₁ 0, 24
25F shows the signal output from the first bit 323 ₁ of the shift register 322, and FIG. 25G shows the scanning signal 325 ₁ output from the OR circuit 324 ₁ .

Further, FIG. 24H shows the shift register 32.
Signal output from the second bit 321 ₂ 0, 24
(I) shows the signal output from the second bit 323 ₂ of the shift register 322, and FIG. 25 (J) shows the scanning signal 325 ₂ output from the OR circuit 324 ₂ .

Thus, as representatively shown by the scan signals 325 ₁ and 325 ₂ , according to this scan driver,
A scan signal for supplying the ON voltage by continuous first and second square waves is generated, and the scan signal of one scan bus line and the scan signal of the next scan bus line are combined into one scan bus. While matching the falling timing of the first square wave of the scan signal of the line and the rising timing of the first square wave of the scan signal of the next scan bus line, Second
Each scan signal can be applied to each scan bus line so that the falling timing of the square wave of and the rising timing of the second square wave of the scanning signal of the next scan bus line are matched, The second invention can be implemented.

Therefore, according to the sixth embodiment, a liquid crystal including an active matrix liquid crystal display panel of so-called one pixel, two display electrodes and three transistors type, as shown in the circuit configuration 38 of one pixel portion in FIG. In the display device, the shift amount of the voltage of the display electrodes 41 and 42 can be suppressed to 1/2 of that in the conventional case. Therefore, even when the same pattern is continuously displayed by AC drive, afterimages and flicker can be prevented. It is possible to display a high-quality image with a reduction in the number of cases.

[0177]

According to the first aspect of the present invention, the first and second liquid crystal cells (25, 26) constituting one pixel are provided with a common electrode (electrically independent from other pixels). 29) electrically connected in series via the first and second display electrodes (2
7, 28) between the first and second transistors (34, 3)
5) via the first and second data bus lines (31, 3)
By adopting the configuration of applying the voltage between 2), the parasitic capacitance (3) between the scan bus line (33) and the sources of the first and second transistors (34, 35).
6, 37) first and second display electrodes (27, 28)
Since it is possible to substantially cancel the voltage shift of, even when the same pattern is continuously displayed by AC driving, it is possible to ensure symmetry between positive driving and negative driving, and to prevent afterimages and , It is possible to eliminate flicker and display a high quality image. In addition, the provision of the auxiliary capacitance does not cause problems such as a reduction in aperture ratio and a reduction in yield.

According to the second aspect of the present invention, an active matrix type liquid crystal display panel of so-called one-pixel two-display-electrode three-transistor type, as shown in FIG. 2 showing a circuit configuration (38) of one pixel portion. In a liquid crystal display device including: a scan signal for supplying an ON voltage by continuous first and second square waves, and a scan signal of one scan bus line and a next scan bus. The scan signal of the line is the first scan signal of the scan bus line
And the rising timing of the first square wave of the scan signal of the next scan bus line is matched, and the rising edge of the second square wave of the scan signal of one scan bus line is matched. A scan driver (53) adapted to apply each scanning signal to each scan bus line so as to match the falling timing with the rising timing of the second square wave of the scanning signal of the next scan bus line. By adopting the configuration of including, it is possible to suppress the shift amount of the voltage of the display electrodes (41, 42) to half that in the conventional case. Therefore, when the same pattern is continuously displayed by AC driving. Also in the above, afterimages and flicker can be reduced as compared with the conventional case, and a high quality image can be displayed.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the first invention of the present invention.

FIG. 2 is a diagram illustrating the principle of the second invention of the present invention.

FIG. 3 is a diagram showing a circuit configuration of a part of an active matrix type liquid crystal display panel included in the first embodiment of the present invention.

FIG. 4 is a diagram showing an overall configuration of a first embodiment of the present invention.

FIG. 5 is a diagram showing characteristics of a data processing unit which constitutes the first embodiment of the present invention.

FIG. 6 is a waveform chart showing the operation of the first embodiment of the present invention.

FIG. 7 is a diagram showing a circuit configuration of a part of an active matrix type liquid crystal display panel provided in a second embodiment of the present invention.

FIG. 8 is a diagram showing an overall configuration of a second embodiment of the present invention.

FIG. 9 is a diagram showing a circuit configuration of a data processing unit included in the second embodiment of the present invention.

FIG. 10 is a diagram showing characteristics of an RGB signal amplification section in a data processing section which constitutes a second embodiment of the present invention.

FIG. 11 is a diagram showing an example of transmittance-voltage characteristics of liquid crystal.

FIG. 12 is a waveform chart showing the operation of the second embodiment of the present invention.

FIG. 13 is a waveform chart for explaining the operation of the second embodiment of the present invention.

FIG. 14 is a diagram showing a circuit configuration of a part of an active matrix type liquid crystal display panel provided in a third embodiment of the present invention.

FIG. 15 is a diagram showing an overall configuration of a third embodiment of the present invention.

FIG. 16 is a diagram showing characteristics of a data processing unit which constitutes a third embodiment of the present invention.

FIG. 17 is a diagram showing a circuit configuration of a part of an active matrix type liquid crystal display panel provided in a fourth embodiment of the present invention.

FIG. 18 is a diagram showing an overall configuration of a fourth embodiment of the present invention.

FIG. 19 is a diagram showing characteristics of a data processing unit included in the fourth embodiment of the present invention.

FIG. 20 is a diagram showing a circuit configuration of a part of an active matrix type liquid crystal display panel provided in a fifth embodiment of the present invention.

FIG. 21 is a diagram showing an overall configuration of a fifth embodiment of the present invention.

FIG. 22 is a diagram showing characteristics of a data processing unit included in the fifth embodiment of the present invention.

FIG. 23 is a diagram showing a circuit configuration of a main part of a sixth embodiment of the present invention, that is, a main part of an example of a scan driver included in the second invention.

FIG. 24 is a waveform chart showing an operation of the scan driver shown in FIG. 23.

FIG. 25 is a diagram showing a circuit configuration of one pixel portion of an active matrix liquid crystal display panel included in an example of a conventional liquid crystal display device (first conventional example).

FIG. 26 is another example of a conventional liquid crystal display device (second conventional example).
FIG. 3 is a diagram showing a circuit configuration of one pixel portion of an active matrix type liquid crystal display panel included in FIG.

27 is a waveform chart showing a part of a scan signal output by a scan driver included in a conventional liquid crystal display device (second conventional example) including the active matrix liquid crystal display panel shown in FIG. 26.

FIG. 28 is a waveform diagram for explaining problems with a liquid crystal display device (first conventional example) including the active matrix liquid crystal display panel shown in FIG. 25.

FIG. 29 is a diagram showing a circuit configuration of one pixel portion of an example of an active matrix type liquid crystal display panel including a storage capacitor.

FIG. 30 is a waveform diagram for explaining problems with a liquid crystal display device (second conventional example) configured to drive the active matrix liquid crystal display panel shown in FIG. 26 by the driving method shown in FIG. 27. is there.

[Explanation of symbols]

 (Fig. 1) 34, 35 Transistors 36, 37 forming switch elements (Fig. 2) 48, 49 Transistors 51, 52 forming switch elements Parasitic capacitance

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Michiya Oura 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Keizo Morita 1015, Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Hiroshi Yoshioka 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa within Fujitsu Limited (72) Inventor Kazuhiro Takahara 1015, Kamedotaka, Nakahara-ku, Kawasaki, Kanagawa Inside Fujitsu Limited

Claims (7)

[Claims] 1. A first and second liquid crystal cell (25, 26) is formed by facing a common electrode (29) to a first and a second display electrode (27, 28) via a liquid crystal (30). Along with
The first display electrode (27) is connected to the first transistor (3
4) connected to the source of this first transistor (3
The drain and gate of 4) are connected to the first data bus line (31) and the scan bus line (33), respectively, and the second display electrode (28) is connected to the source of the second transistor (35). , The drain and gate of the second transistor (35) are connected to the second data bus line (32) and the scan bus line (3), respectively.
3), which is provided with an active matrix type liquid crystal display panel formed by connecting one pixel portion to each other, and the first and second liquid crystal cells (between the first and second data bus lines (31, 32)). 25, 26) is configured to apply a voltage for driving the liquid crystal display device. 2. The first and second data bus lines (3
1 and 32) are applied with first and second data signal voltages having a symmetrical relationship with respect to a predetermined reference voltage, respectively, so that the first and second data bus lines (31, 3) are applied.
The liquid crystal display device according to claim 1, wherein a voltage for driving the first and second liquid crystal cells (25, 26) is applied between 2). 3. The pixels adjacent to each other in the horizontal line direction with the first data bus line (31) interposed therebetween have the first data bus line (31) as the second data bus line (32). , The pixels adjacent to each other with the second data bus line (32) interposed therebetween are connected to the second data bus line (3
2. The liquid crystal display device according to claim 1, wherein 2) is the first data bus line (31). 4. The second data bus line (32) is connected to a scan bus line other than the scan bus line (33), and the voltage of the second data bus line (32) is set to the scan bus line (32). By fixing the off voltage of the scan signal of the scan bus lines other than 33) and applying the data signal voltage to the first data bus line (31), the first and second data bus lines (31,
The liquid crystal display device according to claim 1, wherein a voltage for driving the first and second liquid crystal cells (25, 26) is applied between 32). 5. A reference voltage bus line to which a predetermined reference voltage is applied is provided, and the second data bus line (32) is connected to the reference voltage bus line, and the second data bus line (32). Is fixed to the predetermined reference voltage, and a data signal voltage is applied to the first data bus line (31), so that the data signal voltage is applied between the first and second data bus lines (31, 32). The liquid crystal display device according to claim 1, wherein the liquid crystal display device is configured to apply a voltage for driving the first and second liquid crystal cells (25, 26). 6. A frame in which the voltage of the second data bus line (32) is fixed to a predetermined reference voltage and a data signal voltage is applied to the first data bus line (31).
The voltage of the first data bus line (31) is fixed to the predetermined reference voltage, and the second data bus line (3) is fixed.
By repeating the frame of applying the data signal voltage to 2), the first and second data bus lines (3
1, 32) between the first and second liquid crystal cells (25, 2).
The liquid crystal display device according to claim 1, wherein the liquid crystal display device is configured to apply a voltage for driving 6). 7. A first and second liquid crystal cell (39, 40) is constructed by facing a common electrode (43) to the first and second display electrodes (41, 42) with a liquid crystal (44) in between. And the first
The display electrode (41) of the first transistor (48) is connected to the source of the first transistor (48), and the drain and gate of the first transistor (48) are connected to the data bus line (45) and the scan bus line (46), respectively. , The second display electrode (42) is connected to the source of the second transistor (49), and the drain and gate of the second transistor (49) are connected to the data bus line (45) and the scan bus line, respectively. While connecting to (46),
The first and second display electrodes (41, 42) are connected to the drain and the source of the third transistor (50), and the gate of the third transistor (50) is connected to the next scan bus line (47). A liquid crystal display device comprising an active matrix type liquid crystal display panel which is connected to and forming one pixel portion, wherein a scanning signal for supplying an on-voltage with continuous first and second square waves. Produces
Further, the scan signal of the one scan bus line and the scan signal of the next scan bus line are the timing of the falling edge of the first square wave of the scan signal of the one scan bus line, and the scan signal of the next scan bus. First line scan signal
Of the second square wave of the scan signal of the one scan bus line and the second square wave of the scan signal of the next scan bus line. A liquid crystal display device comprising a scan driver (53) configured to apply each scan signal to each scan bus line so as to match the rising timing of the scan driver.