JPH06253347A - Atm switch and multiplexing circuit - Google Patents

Abstract

(57) [Summary] [Purpose] To reduce the power consumption of ATM switches. An ATM switch for exchanging cells between a plurality of input highways (1-1 to 1-4) and output highways (3-1 to 3-4) is provided corresponding to the output highway. Has multiple input ports, and
Multiple input memories (6-1 to 6-4) in which each input port is independently writable are used, and the plurality of input ports are connected to each of the input highways (1-1 to 1-4) to provide a plurality of inputs. The output ports of the memories (6-1 to 6-4) are connected to the output highways (3-1 to 3-4). [Effect] By using a multi-input FIFO memory as the multi-input memory, the multiplexing mechanism is omitted and an increase in power consumption is suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM switch and a multiplexing circuit, and more particularly to an ATM switch and a plurality of input highways for exchanging cells between a plurality of input highways and a plurality of output highways. The present invention relates to an ATM cell multiplexing circuit that multiplexes ATM transmission cells.

[0002]

2. Description of the Related Art Conventionally, ATMs used in ATM exchanges
In the switch, as shown in FIGS. 11 and 12, ATM cells (hereinafter, abbreviated as cells) on a plurality of input highways 1-1 to 1-4 are multiplexed and multiplexed by a multiplexing unit 15. The signal is commonly applied to the FIFO memories 12-1 to 12-4 provided corresponding to the plurality of output highways 3-1 to 3-4 via the lines 2-1 to 2-4. The multiplexed cells are latched by the header latch units 5-1 to 5-4, and the write control unit 13-1 is used.
~ 13-4. The write control unit determines whether or not to output to each output highway 3-1 to 3-4 by looking at the output destination written in the transmitted header unit, and the FIFO
The write address and the write enable signal are output to the memories 12-1 to 12-4. Read control unit 14-1 to 14-1
14-4 reads out cells in the order in which they are stored in the respective FIFO memories 12-1 to 12-4, and outputs the highways 3-1 to 3-1.
Output to 3-4.

As a document describing such a technique, Proceedings of the Eye E-E 78th
Volume 1 January (1990) (PROCEEDING
OFTHE IEEE, VOL. 78, NO. 1, JA
NUARY 1990) pages 133-149.

[0004]

One of the important things in the ATM switch is to reduce the power consumption as much as possible. In the conventional ATM switch configuration described above, the multiplexing unit 15 is an essential requirement. Therefore, the multiplexing unit 1
5 and the circuit elements forming the buffer memory are required to operate at high speed, resulting in an increase in power consumption. Further, there is a possibility that the limit operation speed of the circuit component element such as the LSI is exceeded. Therefore, an object of the present invention is to realize an ATM switch that consumes less power by eliminating the multiplexing unit.

[0005]

In order to achieve the above object, an ATM switch of the present invention has a buffer memory having a plurality of input ports, capable of simultaneous writing, and capable of reading independently from the above writing. A plurality of input highways are used for each of the plurality of output highways, and a plurality of input highways are added to the respective plurality of input ports of the plurality of buffer memories, and a header latch provided for each of the plurality of input highways. A write control unit is provided to control writing of cell signals from a plurality of input ports of the plurality of buffer memories by a signal such as an identification number of an output highway from the unit. Note that the number of input highways and the number of input ports do not necessarily match.

Further, in consideration of the capacity and speed of the multi-input memory, a plurality of ATM switches having the above configuration are arranged in parallel, cell information is divided into each of the plurality of input highways, and the plurality of ATM switches are arranged in parallel. It is also possible to provide a cell dividing section to be added to the ATM switch, and to provide a cell coupling section for coupling the cells from the plurality of ATM switches arranged in parallel to each of the plurality of output highways. As the buffer memory, a conventionally known multi-input FIFO memory (for example, Japanese Patent Application No. 3-244
"Multi-port RAM" described in No. 851) or the like can be used. Further, in the present invention, by selecting one of the plurality of buffer memories of the ATM switch of the present invention,
It constitutes a multiplexing circuit of TM cells.

[0007]

In the ATM switch of the present invention, the cell signals of a plurality of input highways are added to the plurality of input ports of the buffer memory provided corresponding to the output highways without passing through the multiplexer, and A cell is recorded on the input highway by using outputs of a plurality of header latch units provided in each of the plurality of input highways to control writing of cell signals from a plurality of input ports of the plurality of buffer memories. The embedded controller can simultaneously write a plurality of cells input from a plurality of input highways to different areas (addresses) in the memory. A write enable signal from the write control unit records only cells to be output to the output highway, thereby switching between a plurality of input highways and output highways, that is, switching.

Therefore, the operation speed of recording from the plurality of input highways to the buffer memory may be equal to or lower than the individual cell transmission speed of the plurality of input highways. That is, conventional A
The switch can be configured by omitting the high-speed operation circuit required for the TM switch. Further, the above-mentioned multiple input buffer memory can also be used as a multiplexing circuit.
That is, by connecting the input highway to the input port of the multi-input buffer memory and connecting the output port of the multi-input buffer memory to the output highway, the multiplexing circuit can be easily realized.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of an ATM switch according to the present invention. In this embodiment, there are four input highways 1-1 to 1-4 and input highways 1-1 to 1-1.
It has 4 input ports for inputting each cell signal of 1-4, and 4
Buffer memories 6-1 to 6-1 each having one output port provided corresponding to each output highway 3-1 to 3-4
6-4, and write control units 7-1 to 7-4 and read control unit 8-provided in the buffer memories 6-1 to 6-4, respectively.
1 to 8-4 and input highways 1-1 to 1-4, and header latch circuits for transmitting the identification numbers of the output highways included in the cells to the write controllers 7-1 to 7-4, respectively. 5-1 to 5-4 and header latch circuit 5-
1 to 5-4 have timing generators 9-1 to 9-4 that generate timing signals by using the cell top signals 10-1 to 10-4 for extracting the identification number.

The buffer memories 6-1 to 6-4 have the above-mentioned 4
It is composed of a multi-input FIFO memory in which cells input from the input highway of the book can be simultaneously written in different areas (addresses) in the 4-input FIFO memory and can be read independently of writing.

The write control units 7-1 to 7-4 will be described later with reference to FIG.
The output HWI of the cells on the respective highways sent from the header latch circuits 5-1 to 5-4, as will be described later.
D is checked and the above-mentioned cell is set to 4-input FIFO memory 6-1 to 6
-4, that is, output highway 3-1 to
It is determined whether to output to 3-4. When writing to the FIFO memories 6-1 to 6-4, a write enable signal corresponding to the input port and a cell to be written are generated and added to the FIFO memories 6-1 to 6-4.

FIG. 2 shows the structure of a cell transmitted on the input / output highway of the above embodiment. The cell length is 64 bytes. The cell length according to the CCITT recommendation is 53 bytes, but 11 bytes are added as a header in order to give the cell control information and the like used in the device. In the header portion, the identification number of the highway from which the cell is output (output HW
ID) is included.

FIG. 3 is a block diagram showing the structure of an ATM switch using the ATM switch according to the present invention. A
Each of the input highways 1-1 to 1-4 of the TM switch 23 has a receiving side interface section 21-1 to 21-4.
Is provided, and each receiving side interface unit is the receiving unit 2
Output HWID adding units 25-1 to 25-4 for converting the transfer destination control information included in the output headers of the output units 4-1 to 24-4 and the receiving unit 24 into the output HWID are provided. That is, the output HWID is written in the header portion of the cell before being input to the switch unit 23. The output highways 3-1 to 3-4 of the ATM switch 23 are provided with transmission-side interface units 21-1 to 21-4, respectively. The transmission side interface units 21-1 to 21-4 are
The transmitters 26-1 to 26-4 are provided for removing the output HWID and the like and converting the output HWID and the like into a signal form (header or the like) suitable for transmission.

FIG. 4 shows the 4-input FIF in the above embodiment.
It is a figure which shows the write timing of O memory 6-1.
In FIG. 4, the time phases of the cells input from the four input highways 1-1 to 1-4 are aligned, and the input highway 1
-1, 1-2, 1-4 show the case where cells heading for the output highway 3-1 have arrived. Input highway 1-3
Is an invalid cell (for example, a cell output to another output highway). That is, in this embodiment, the cells on the input highways 1-1, 1-2, and 1-4 are written in the 4-input FIFO memory 6-1. At this time, among the input enable signals of the 4-input FIFO memory 6-1, the input highway 1
The input enable signals corresponding to -1, 1-2, and 1-4 are turned on. In addition, input highways 1-1, 1-2, 1
The write address signals corresponding to -4 are given consecutive values (3, 4, 5 in the case of the present embodiment).
In this embodiment, the cells arriving from the input highways 1-1, 1-2, and 1-4 are written in the 4-input FIFO memory 6-1 even in the next write cycle. At this time, the addresses given to the cells arriving from the respective input highways are 6, 7, and 8, respectively.

FIG. 5 shows the 4-input FIF in the above embodiment.
3 is a block diagram showing the configurations of an O memory 6 and a write control unit 7. FIG. The cells input from the input highways 1-1 to 1-4 are stored in continuous areas via the four input ports Di1, Di2, Di3 and Di4 of the 4-input FIFO memory 6, respectively. The maximum number of cells that can be stored is 256. The 4-input FIFO memory 6 has write enable signals WE1, WE2, WE3 and W for driving the four input ports Di1, Di2, Di3 and Di4.
It has a port for supplying E4 and the aligned write addresses WA1, WA2, WA3, and WA4 (the read side configuration is omitted in this figure).

The write controller 7 includes a write counter 70 and
One of the adders 71, 72, 73 and 78 for adding 1, 2, 3 and 4 to the output value of the counter 70, one of the output value of the counter 70 (line 60) and the output value of the adder 71 (line 61) Output of the counter 74, the output value of the counter 70 (line 60), the output value of the adder 71 (line 61) or the output value of the adder 72 (line 62), the output of the counter 70 Of the selector 76 and the counter 70 for selecting one of the numerical value (line 60), the output numerical value of the adder 71 (line 61), the output numerical value of the adder 72 (line 62) or the output numerical value of the adder 73 (line 63). Output value, adder 71, 72, 73, or 7
Selector 77 for selecting one of the output numerical values of 4 and enable signals WE1, WE2, WE3 and WE4 are inputted and a selector control circuit 79 and a header latch circuit 5-for generating drive signals for the selectors 74, 75, 76 and 77. 1, 5
-2, 5-3 and 5-4, and has an enable signal generation circuit 80 which inputs the output highway identification signals and produces enable signals WE1, WE2, WE3 and WE4. The output numerical value of the counter 70 and the output numerical values of the selectors 74, 75 and 76 are all represented by 8 bits, and which area of the 4-input FIFO memory 6 is used to store the next cell arriving at the input ports Di1, Di2, Di3 and Di4, respectively. Write addresses WA1 and WA indicating whether to store in (address)
2, WA3 and WA4 are given.

FIG. 6 is a table for explaining the operation of the write controller 7 of FIG. For example, in the second row of the table, when a cell arrives only at the input highways 1-4, only the enable signal WE4 is turned on, only the selector 76 selects the output value of the counter 70 (line 60), and the write address WA4 is generated and given to the FIFO memory 6. Further, in the 13th row of the table, when the cells arrive at the input highways 1-1 and 1-2, the enable signals WE1 and WE2 are turned ON, and the output value of the counter 70 (line 60) indicates the write address WA1. The selector 74 selects the output value (line 61) of the adder 71, and the write address WA
2 is generated and given to the input FIFO memory 6. In this way, the continuous input is used as a write address and 4-input FI is set.
It is given to the FO memory 6.

Selectors 74 to 76 and enable signal WE
1 to WE4 store a plurality of cells simultaneously input from the input highways 1-1 to 1-4 at consecutive addresses. Further, the selector 77 selects the address value to be indicated by the counter in the next cell input cycle. For example, in a certain cycle, n cells (n is 0 or more and is an integer less than or equal to the number of input highways (4 in this example)) are 4-input FI.
When stored in the FO memory, the selector 77 stores in the counter 70 a value obtained by adding n to the current counter value.

FIG. 7 is a block diagram showing the configuration of another embodiment of the ATM switch according to the present invention. In this embodiment, cells are divided (hereinafter, each of the divided cells is abbreviated as a divided cell), a plurality of divided cell switch units perform switching for each divided cell, and after the switching is completed, each divided cell is output to the same output highway. It is configured to be connected for each. In the figure, cells are divided into eight by cell division units 31-1 to 31-4 provided for the respective input highways 1-1 to 1-4, and eight divided cell switches are provided for each divided cell. Switching is performed in the parts 32-1 to 32-8. The outputs of the divided cell switch units 32-1 to 32-8 are combined in the cell combining units 33-1 to 33-4 and output to the output highways 3-1 to 3-4 as switched cells (64 bytes). It

FIG. 8 shows a cell structure before division and a cell structure after division in the cell division unit. Input highway 1-
As shown in (a), the cell above 1 (ie, the cell before cell division) is 64 bytes as in FIG. The 64-byte cell is divided into eight 1 × 8-byte divided cells in the cell dividing unit 31-1, as shown in (b). A header including the identification number of the output highway is also added to each of the divided cells. Writing of the identification number of the output highway is performed in the cell division unit 31-1. The header of each divided cell has the same output highway identification number. The eight divided cells output from the cell division unit 31-1 are input to the divided cell switch units 32-1 to 32-8, respectively. The same applies to the cell division units 31-2 to 31-4.

FIG. 9 shows the structure of an embodiment of the divided cell switch section 32. The configuration of the divided cell switch unit 32 is basically the same as that of the ATM switch of FIG. In the figure, the divided cells from the divided cell portions 31-1 to 31-4 of FIG. 5 are added to the four input lines 41-1 to 41-4, respectively. The 4-input FIFO memories 54-1 to 54-4 connected to the input lines 42-1 to 42-4 are multi-input FIFO memories having four input ports, and the four input lines 41-1 to 41-1 described above. The divided cells input from 41-4 are simultaneously input to 4-input FIFO memories 54-1 to 54-4.
Writing to different areas (addresses) in the
Read out independently.

The header latch sections 52-1 to 52-4 latch the header sections of the divided cells input from the input lines 41-1 to 41-4 to which they belong, and the write control section 5 respectively.
5-1 to 55-4. Write control units 55-1 to 5
5-4 checks the headers of the divided cells sent from the header latch units 52-1 to 52-4, and the four input lines 41-
1-41-4 divided cells on 4 input FIFO memory 54
Whether to write to -1 to 54-4, that is, the output line 43
It is determined whether to output to -1 to 43-4. When writing to the 4-input FIFO memory 54-1 to 54-4,
The write enable signals corresponding to the input lines 41-1 to 41-4 are turned on.

FIG. 10 shows a timing chart for explaining the operation of the write controller 55. 4 input lines 41-1
The time phases of the divided cells on ˜41-4 are aligned. In FIG. 10, the divided cells arriving at the output highway 43-1 have arrived at the input lines 41-1, 41-2, 41-4.
An invalid divided cell has arrived at the input line 41-3.
That is, in this embodiment, the input lines 41-1, 41-2, 41
-4 input FIFO memory 5
Write to 4-1. At this time, the 4-input FIFO memory 54
-1 input enable signals, input lines 41-1 and 4
The signals corresponding to 1-2 and 41-4 are turned on. Further, the write address signals corresponding to the input lines 41-1, 41-2, 41-4 have consecutive values (in the case of the present embodiment,
3, 4, 5) are given respectively. In this embodiment, the input lines 41-1, 41-2, 41-2,
The divided cells arriving from 41-4 are written in the 4-input FIFO memory 54-1. At this time, each input line 41
The addresses given to the divided cells arriving from -1, 41-2 and 41-4 are 6, 7 and 8, respectively. The write controller 55 is realized by a circuit similar to the circuit shown in FIG.

4-input FIFO memory 54-1 to 54-4
The divided cells output from the output port of the cell connecting unit 3 shown in FIG. 7 are output via output lines 43-1 to 43-4.
3-1 to 33-4 are combined. The structure of the cell after combination is the same as the structure of the cell before division shown in FIG. 7, and is further converted into a header suitable for highway transmission, and is transmitted on the output highways 3-1 to 3-4.

Although the above embodiment describes the ATM switch, the present invention can constitute a multiplexing circuit. That is, FIG.
In the configuration of the ATM switch, the output highway 3-
It suffices to provide a single number of 1 to 3-4 and to provide a 4-input FIFO memory 6, a write control unit 7 and a read control unit 8 corresponding to a single output highway 3. In the case of the multiplexing circuit, the output highway identification number addition units 25-1 to 25-4 of the reception interfaces 21-1 to 21-4 of FIG. 3 are unnecessary.

For the sake of convenience of explanation, the above-mentioned embodiment has explained the 4-input highway and 4-input port FIFO memory, but the present invention is not limited to the above-mentioned embodiment.
For example, the number of input highways may not match the number of input ports of the memory.

[0027]

EFFECTS OF THE INVENTION It is possible to omit the multiplexing means required in the conventional switch, and as a result, it is possible to reduce the power consumption without increasing the operating speed.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a first embodiment of an ATM switch according to the present invention.

FIG. 2 is a diagram showing the structure of a cell used in the first embodiment of the present invention.

FIG. 3 is a diagram showing the overall configuration of an ATM switch using an ATM switch according to the present invention.

FIG. 4 is a diagram showing write timing to a 4-input FIFO memory in the first embodiment of the ATM switch according to the present invention.

FIG. 5 is a configuration diagram of a write control unit in the first embodiment of the ATM switch according to the present invention.

FIG. 6 is a diagram for explaining the operation of the write control unit of FIG.

FIG. 7 is a diagram showing a configuration of a second embodiment of an ATM switch according to the present invention.

FIG. 8 is a diagram showing the structure of a cell used in the second embodiment of the present invention.

FIG. 9 is a diagram showing a configuration of a divided cell switch unit in a second embodiment of the ATM switch according to the present invention.

FIG. 10 is a diagram showing a write timing to a 4-input FIFO memory in the second embodiment of the ATM switch according to the present invention.

FIG. 11 is a diagram showing a configuration of a conventional ATM switch section.

FIG. 12 is a diagram showing states of cells before and after multiplexing in a multiplexer of a conventional ATM switch.

[Explanation of symbols]

1-1 to 1-4: Input highway, 2-1 to 2-
4: highway, 3-1 to 3-4: output highway,
5-1 to 5-4: Header latch part, 6, 6-1 to 6-
4: FIFO memory, 7, 7-1 to 7-4: write control unit, 8-1 to 8-4: read control unit, 9: timing generation unit, 9-1 to 9-4: timing generation unit, 1
0-1 to 10-4: cell head signals 12-1 to 12-
4: FIFO memory, 13-1 to 13-4: write control unit, 14-1 to 14-4: read control unit, 15: multiplexing unit, 21-1 to 21-4: reception side interface,
22-1 to 22-4: transmitting side interface, 23:
Switch, 24-1 to 24-4:
Receiving unit, 25-1 to 25-4: output HWID adding unit,
26-1 to 26-4: Transmission unit, 31-1 to 31-4: Cell division unit, 32-1 to 32-4: Division cell switch unit,
33-1 to 33-4: Cell coupling part, 8-1 to 8-
4: read control unit, 41-1 to 41-4: input line of divided cell switch unit, 43-1 to 43-4: output line of divided cell switch unit, 44-1 to 44-4: head of divided cell Indicating a signal (divided cell top signal), 52-1 to 52-
4: header latch unit, 53-1 to 53-4: timing generation unit, 54-1 to 54-4: FIFO memory, 55-
1-55-4: write control unit, 56-1 to 56-4:
Read control unit, 60: output of counter 70, 70: counter, 71: adder (add 1), 72: adder (add 2), 73: adder (add 3), 74: selector,
75: selector, 76: selector,
Reference numeral 77: selector, 78: adder (adding 4), 79: selector control unit.

Claims (13)

[Claims] 1. An ATM switch for exchanging cells between a plurality of input highways and a plurality of output highways, wherein the ATM switch is provided corresponding to the plurality of output highways, has a plurality of input ports, and Using a plurality of buffer memories in which each of the plurality of input ports can be independently written, a plurality of header latch units provided in each of the plurality of input highways, and outputs of the plurality of header latch units A write control unit that controls writing of cell signals from a plurality of input ports of the plurality of buffer memories, and a write controller that is provided corresponding to each of the plurality of buffer memories and is provided for a cell from an output port of the buffer memory. And a read control unit for performing read control, wherein each of the plurality of input ports of the plurality of buffer memories has the plurality of input ports. Connected to each of the force highways, ATM switch, characterized in that each of the output ports of the plurality of buffer memory is configured by connecting to a corresponding said plurality of output highways. 2. The ATM switch according to claim 1, wherein:
The write control unit receives the cell headers obtained from the plurality of input highways as inputs, generates a write enable signal and a write address signal for each input port, and outputs the write enable signals and the write address signals from the plurality of input highways. Of the cells, the write enable signal is turned on only for the cells output to the output highway corresponding to each of the plurality of buffer memories, and the area where the cells to be written to the buffer memory from the plurality of input ports is continuous. An ATM switch having means for generating an address signal to be stored in the ATM switch. 3. The ATM switch according to claim 1, wherein:
Each of the plurality of input highways has means for creating an identification number of the output highway to be output from the header of the receiving cell and adding it to the receiving cell.
TM switch. 4. An ATM switch for exchanging cells between a plurality of input highways and a plurality of output highways, wherein each of the plurality of input highways is provided and the ATM cell is divided into divided cells of a certain number of bytes. A plurality of cell division units, a plurality of division cell switch units that receive division cells from the plurality of cell division units, and an output division cell of the plurality of division cell switch units that should be transmitted to the same output highway And a plurality of cell combining units that combine output divided cells and output to a corresponding output highway among a plurality of output highways, each of the plurality of divided cell switch units corresponding to the plurality of output highways. A plurality of buffers that are provided and have a plurality of input ports, and that each input port of the plurality of input ports can be independently written Memory, a plurality of header latch units provided in each of the input lines for inputting divided cells from the plurality of cell dividing units to the plurality of input ports, and the plurality of header latch units using outputs of the plurality of header latch units. Write control section for controlling the writing of cell signals from a plurality of input ports of the buffer memory, and the control of reading cells from the output port of the buffer memory provided corresponding to each of the plurality of buffer memories. An ATM switch comprising: a read control unit for performing the read operation; and an output line connected to the plurality of cell coupling units corresponding to the respective output ports of the plurality of buffer memories. 5. The ATM switch according to claim 4, wherein:
The write control unit generates a write enable signal and a write address signal for each input port, and outputs a write enable signal and a write address signal to the plurality of buffer memories among the plurality of divided cells to which the divided cells are input. Means for turning on the write enable signal only for the divided cells to be output to the corresponding output highway and for generating an address signal for storing the cells to be written in the buffer memory from the plurality of input ports in a continuous area ATM switch characterized by. 6. The ATM switch according to claim 4, wherein:
An ATM switch, wherein each of the plurality of cell division units has means for adding the same output highway identification number to each of the division cells. 7. A according to claim 1, 2, 3, 4, 5 or 6.
In the TM switch, the means for generating the address signal of the write control unit includes a memory, a plurality of adders that add mutually different integer values to the output of the memory, an output of the memory and an output of the plurality of adders. A plurality of selectors provided for each write address input terminal of the buffer memory for selecting any one of the input highways or the plurality of input highways for the write address input terminals of the buffer memory corresponding to the selectors. A selector that drives the plurality of selectors so that the write addresses given to the plurality of cells or the divided cells to be written in the buffer memory have consecutive values among the cells or the divided cells input simultaneously from the plurality of cell divisions. An ATM switch having a control means. 8. The ATM switch according to claim 7, wherein:
An ATM switch, wherein the output of the memory is directly applied to one of the write address input terminals of the buffer memory. 9. The ATM switch according to claim 7, wherein the memory used for generating the write address comprises a counter. 10. An ATM according to any one of claims 1 to 9.
In the switch, an ATM switch in which time phases of cells or divided cells input from the respective input ports of the buffer memory are aligned. 11. The AT according to any one of claims 1 to 10.
In the M switch, the buffer memory is a FIFO
An ATM switch characterized by being a memory. 12. A plurality of input highways for transmitting ATM cells and a plurality of input ports to which cells from the plurality of input highways are added, and each of the plurality of input ports has an independent input port. A plurality of writable buffer memories, a plurality of header latch units provided in each of the plurality of input highways, and a plurality of the plurality of buffer memories using the outputs of the plurality of header latch units. A write control unit for controlling writing of a cell signal from the input port; and a read control unit for controlling reading of cells from the output ports of the plurality of buffer memories to an output highway. ATM cell multiplexing circuit. 13. The multiplexing circuit according to claim 12,
An ATM cell multiplexing circuit, wherein the buffer memory is a FIFO memory.