JPH06253202A - Memory circuit and image pickup device - Google Patents

Abstract

PURPOSE:To reduce the memory capacity of a memory circuit used for the image pickup device or the like. CONSTITUTION:A signal compression circuit 1004 applies band split to two field signals S1, S2 forming a frame signal and obtains synthesis signals S3, S4 from the band split signals. The memory capacity of field memory circuits 1005, 1006 is reduced by making the frequency band of at least one of the synthesis signals S3, S4 narrower than that of the field signal S1 or S2. Then band split is applied to memory output signals of the field memory circuits 1005, 1006 to obtain the synthesis signal S5 nearly equal to the field signal S1 and the synthesis signal S6 nearly equal to the field signal S2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory function in an image pickup device such as a video camera, and more particularly to a memory circuit and an image pickup device for performing arithmetic processing for reducing the memory capacity when storing a frame video signal in the memory. It is about.

[0002]

2. Description of the Related Art In recent years, image pickup devices such as video cameras have become smaller, lighter and more multifunctional, and image pickup devices having various functions using a memory have been developed and commercialized. A memory function in a conventional image pickup device such as a video camera will be described.

As an image pickup apparatus using a conventional memory,
There is Japanese Patent Application No. 4-195096 “Imaging Device with Horizontal Line Interpolation Function” filed earlier by the applicant of the present application. less than,
The image pickup apparatus with the horizontal line interpolation function will be described.

FIG. 18 is a block diagram of an image pickup apparatus using a pseudo frame signal. In FIG.
Reference numeral 801 denotes two types of luminance signals Y1, Y from R, G, B signals.
Digital signal processing circuits for obtaining two and two types of color signals C1 and C2, 1802 to 1805 are field memories for storing respective signals, 1806 is field memories 1802 to 1802
A field memory control circuit for controlling the 1805;
Reference numeral 7 is an electronic zoom circuit that performs interpolation and enlargement using signals Y1, Y2, C1 and C2, and 1808 is a system control circuit that comprehensively controls the digital signal processing circuit 1801, field memory control circuit 1806, and electronic zoom circuit 1807. is there.

FIG. 19 is a block diagram showing the internal structure of the digital signal processing circuit 1801 shown in FIG. In the figure, 1901 is a line memory for storing signals in the 1H period, 1902 is an adder, 1903 is a 1/2 amplifier circuit for gain adjustment, and 1904 is 3 signals to 2 signals R.
1 and R2 are selector circuits for selecting information from the system control circuit 1808, 1905, 1906, and 1907 are signal selection circuits composed of components 1901 to 1904,
Reference numeral 1908 represents a Y1 matrix circuit that creates a luminance signal Y1, 1909 represents a Y2 matrix circuit that creates a luminance signal Y2, 1910 represents a C1 matrix circuit that creates a color signal C1, 1911 represents a C2 matrix circuit that creates a color signal C2, and 1912 represents It is a matrix circuit composed of components 1908 to 1911.

The operation of the image pickup apparatus having the horizontal line interpolation function configured as described above will be described below. In FIG. 19, in the signal selection circuits 1905 to 1907,
First, three signals are created from signals of two consecutive lines. Next, the selector 1904 selects 2 signals from 3 signals. In this way, the interpolation signal is created at an arbitrary position by selecting the two signals necessary for creating the interpolation line from the three signals created from the signals of the continuous two lines. The selector circuit 1904 selects these two signals under the control of the system control circuit 1808, and the matrix calculation of the luminance signal is performed by the Y1 matrix circuits 1908 and Y2.
The matrix circuit 1909 performs this. Similarly, the C1 matrix circuit 1910 and the C2 matrix circuit 1911 perform color signal matrix calculation. Next, the output signals of the digital signal processing circuit 1801 in FIG. 18 are stored in the field memories 1802-1805 under the control of the field memory control circuit 1806, respectively, and then in the electronic zoom circuit 1807, the field memories 1802-1.
Interpolation calculation is performed using the signal from 805. The interpolation calculation is performed using signals of two lines that are in the positional relationship of the frame signals.

[0007]

However, the conventional image pickup device with a memory function has the following problems. That is, recording a frame signal in the memory requires twice as much memory capacity as recording a field signal, resulting in an increase in cost and the number of parts.

The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a memory circuit and an image pickup apparatus which can realize memory recording of a frame signal with a small memory capacity.

[0009]

In order to achieve this object, a memory circuit and an image pickup device of the present invention have a means for obtaining two field signals S1 and S2 constituting a frame signal, and a method for the field signal S1. A first band division circuit that performs band division, a second band division circuit that performs band division for the field signal S2, and a composite signal S3 and S4 from the band-divided S1 and the band-divided S2 signals. A first signal synthesizing circuit for obtaining a signal, a first memory circuit for storing the S3, a second memory circuit for storing the S4, and a band division for the output signal of the first memory circuit. 3 band division circuit, 4th band division circuit for performing band division on the second memory circuit output signal, 1st memory circuit output signal subjected to the band division and 2nd band division And it has a configuration of the second signal combining circuit for obtaining a synthetic signal S5 and S6 signal from the memory circuit output signal.

Further, means for obtaining three different color signals C1, C2 and C3, and a first vertical phase shift section for shifting the phase of the color signal C2 in the vertical direction with respect to the color signal C1 by a constant pitch p1. A second vertical phase shifter for shifting the phase of the color signal C3 in the vertical direction by a fixed pitch p2; and the pseudo frame signal S1 from the color signals C2, C3 vertically phase-shifted with the color signal C1.
A frame operation circuit for obtaining S2, a first band division circuit for performing band division on the signal S1, a second band division circuit for performing band division on the signal S2, and the band-divided S1. A first signal combining circuit for obtaining combined signals S3 and S4 signals from the band-divided S2 signal, and said S3
A second memory circuit for storing S4, a second memory circuit for storing S4, a third band division circuit for performing band division on the output signal of the first memory circuit, and the second memory A fourth band-dividing circuit for band-dividing the circuit output signal, and a composite signal S5 and S6 signal from the band-divided first memory circuit output signal and the band-divided second memory circuit output signal. It has a configuration of a second signal combining circuit to be obtained.

Further, means for obtaining two field signals S1 and S2 constituting a frame signal, and a first band division circuit for band-dividing the field signal S1.
A second band-dividing circuit for band-dividing the field signal S2, and a first signal for obtaining a combined signal S3 and S4 signal from the band-divided S1 and band-divided S2 signals.
Signal combining circuit, a first memory circuit for storing S3, a second memory circuit for storing S4, and a third band division for performing band division on the output signal of the first memory circuit. A circuit, a fourth band division circuit for performing band division on the second memory circuit output signal, and a band division second for the band divided first memory circuit output signal
The second signal synthesizing circuit that obtains the synthesized signals S5 and S6 signals from the memory circuit output signal and the interpolating arithmetic circuit that obtains the interpolating signal by performing the interpolating operation from the S5 and S6 signals.

[0012]

According to the present invention, the two field signals S1 and S2 forming the frame signal are band-divided by the above-mentioned configuration, and the composite signals S3 and S4 are obtained from the band-divided signals. And S4 have a frequency band narrower than that of the field signal S1 or S2 to reduce the memory capacity, and the memory output signal is band-divided to obtain a composite signal S5 and a field signal S2 that are substantially equal to the field signal S1. A composite signal S6 approximately equal to is obtained.

Further, the first and second vertical phase shifters change the vertical phases of the three color signals obtained from the plurality of solid-state image pickup devices, and band the pseudo frame signals generated by the frame arithmetic circuit. By performing division, a combined signal S3 and S4 signal is obtained from the band-divided signal, and at least one of the combined signals S3 and S4 is made narrower in frequency band than the field signal S1 or S2 to reduce the memory capacity and output the memory. Band division is performed on the signal to obtain a combined signal S5 that is substantially equal to the field signal S1 and a combined signal S6 that is substantially equal to the field signal S2.

Band division is performed on the two field signals S1 and S2 forming the frame signal, and the combined signals S3 and S4 are obtained from the band-divided signals. At least one of the combined signals S3 and S4 is obtained. The memory capacity is reduced by making the frequency band narrower than that of the field signal S1 or S2, and the memory output signal is band-divided.
5 and a composite signal S6 approximately equal to the field signal S2 are obtained, and an interpolation signal is created from these composite signals S5 and S6 to reduce deterioration due to memory reduction.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a memory circuit and an image pickup device according to the first embodiment of the present invention. In FIG. 1, 101 is an image pickup device unit having a photoelectric conversion function, 102 is an image pickup device drive circuit for the image pickup device unit 101, 103 is a drive control circuit for controlling the image pickup device drive circuit 102, and 104 is an output signal of the image pickup device 101. Analog signal processing circuit for processing such as sampling and amplification, 10
Reference numeral 5 denotes an analog-digital conversion circuit (hereinafter referred to as A / D conversion circuit) for the output signal of the analog signal processing circuit 104, 1
Reference numeral 06 is a digital signal processing circuit for generating a luminance signal, color signal, color difference signal or the like from an A / D converted digital signal or RGB signal processing, and 107 is suitable for storing the output signal of the digital signal processing circuit 106 in a field memory. A signal compression circuit for performing signal compression, 108 to 111 are Y3 field memory, Y4 field memory, C3 field memory and C4 field memory for storing the output signal of the signal compression circuit 107, and 112 controls each field memory 108 to 111. A memory control circuit, 113 is a signal restoration circuit that restores the output signals of the field memories 108 to 111, 114 is a memory output processing circuit that performs electronic zoom processing and still image output processing using the output signal of the signal restoration circuit 113, and 115 is digital Signal processing circuit 106 or memory output processing An encoder for converting the output signal of the circuit 114 into a television signal such as an NTSC signal, 116
Is a system control circuit that comprehensively controls the drive control circuit 103 and the memory control circuit 112.

The operation of the memory circuit and the image pickup device of the present embodiment having the above-described configuration will be described below. The plurality of R, G, and B output signals output from the image sensor unit 101 are converted into digital signals by analog signal processing and A / D conversion processing. This digital signal is processed by the digital signal processing circuit 106 to obtain luminance signals (Y1, Y
2) and color signal (C1, C2) processed signal compression circuit 1
It is input to 07. The signal compression circuit 107 performs compression processing on the input signal and compresses the luminance signal (Y3, Y4).
And color signals (C3, C4) are output, and these signals are input to the respective field memory circuits 108 to 111 controlled by the memory control circuit 112. The output signals from the field memory circuits 108 to 111 become the luminance signals (Y5, Y6) and the color signals (C5, C6) restored by the signal restoring circuit 113, and the memory output processing circuit 114 uses the pseudo frame signal to generate an electronic signal. The zoom processing or the still image output processing is performed, and the encoder 115 outputs the television signal. Also, the encoder 11
Since the output signal of the digital signal processing circuit 106 is input to the circuit 5, the system of the memory circuit unit including the signal compression circuit 107, each field memory 108 to 111, the signal decompression circuit 113, and the memory output processing circuit 114 is connected. It is also possible to output a television signal using a signal that does not pass.

FIG. 2 shows the frame accumulation drive control of the image sensor by the drive control circuit 103. FIG. 2 (a) shows a normal interlace read drive control of the image sensor, and FIG. 2 (b) shows R, G, which are configuration examples of the image sensor unit 101 in this embodiment.
An outline of read drive control of the R, G, and B image pickup devices for obtaining B signals will be described. As shown in FIG. 2A, in the frame accumulation mode, the signals of pixels in the odd-numbered lines in the vertical direction among the pixels in the photosensitive area are read during the field shift in the odd field, and then in the even field in the even field. Inter-line transfer is realized by reading out the signal of the pixel on the second line. In the present embodiment, as shown in FIG. 2B, in the odd field, the signals of the pixels of the odd-numbered lines in the vertical direction in the R.B.
The image pickup device reads out the signal of the pixel of the even-numbered line, and then, in the even field, the R / B image pickup device of the R, G, B image pickup devices outputs the signal of the pixel of the even-numbered line in the vertical direction. , G image sensors read the signals of the pixels in the odd-numbered lines. In this way, in frame accumulation drive control, the odd / even reading of the R, G, and B image sensors is performed by R
-The B image sensor and the G image sensor are reversed.

Next, FIG. 3 shows field accumulation drive control of the image pickup device. FIG. 3A shows a normal image sensor interlaced read drive control, and FIG. 3B shows another configuration example of the image sensor unit 101 according to this embodiment, in which R, G, and B signals are obtained. An outline of read drive control of the G and B image pickup devices will be shown. In the field accumulation mode, as shown in FIG.
In the dd field, the signals of the odd-numbered lines and the signals of the next even-numbered lines are simultaneously added (PDmix) from the pixels of the lines near the horizontal transfer CCD (not shown) and read out,
Next, by changing the combination of addition in the even field, the signal of the even-numbered line from the bottom and the signal of the next odd-numbered line are simultaneously added and read out to realize inter-line transfer. In this embodiment, in the odd field as shown in FIG. 3B, the odd field reading shown in FIG. The even field reading is performed in the element, and then in the even field, the e in the R / B image sensor out of the R / G / B image sensors.
The ven field reading is performed, and the G image sensor performs odd field reading. In this way, in field accumulation drive control, the odd / even PDmix reading of the R, G, and B image sensors is reversed for the R, B, and G image sensors.

As shown in FIGS. 2 and 3, odd / ev
The spatial position (phase) of the R, B and G signals obtained by reversing the reading of en between the R and B image sensors and the G image sensor is 1/2 line (line spacing in one field). It will be shifted.

As described above, the present embodiment shows the case where the drive control circuit is provided to shift the phases of the three color signals R, G, and B, respectively. Other than this, the three color signals R, G, and B can also be obtained by shifting the position of the solid-state image pickup device in the vertical direction to the three-color separation prism or the two-color separation prism for obtaining the three color signals, and fixing them. It is possible to shift the phase of each.

Next, the signal processing method for the obtained R, G, and B color signals will be described below. FIG. 4 shows an outline of signal processing. Figure 4 (a) shows G in phase with the R and B signals.
A process for obtaining a signal, FIG. 4B shows an outline of a process for obtaining an R signal and a B signal in phase with the G signal. As shown in FIG. 4, the R, B signals and the G signal are out of phase with each other by 1/2 line (line interval in one field), so that it is necessary to match the phase in the vertical direction for signal processing. Therefore, in FIG. 4 (a), by performing averaging processing of two consecutive lines (interpolation processing of interpolation coefficient 1/2 · 1/2) on the G signal, R,
It is possible to match the phases of the G and B signals, and in FIG. 4 (b), the averaging process of two consecutive lines (interpolation process of 1/2/1/2 interpolation coefficient) is performed for the R and B signals. By doing
The phases of the R, G and B signals can be matched. This is shown in (Equation 1).

[0023]

[Equation 1]

2, 3 and 4 (a), the case of control (C1) for spatially shifting the position of the G signal will be described.
In (b), control for spatially shifting the positions of the R and B signals (C
The case of 2) was explained. Also, only the position of the R signal (C3)
It is also possible to spatially shift (C4) only by the position of the B signal. The spatial position control will be described below.
The luminance (Y) signal is created by the R, G, B signals, which is shown in (Equation 2).

[0025]

[Equation 2]

Here, the spatially offset signal (Ya) and the spatially offset signal (Yb) contained in the luminance signal are expressed by the following equations (Equation 3) for C1 to C4.

[0027]

[Equation 3]

The color difference signals (R-Y and B-Y) are created from the R, G, B signals, which is expressed by (Equation 4).

[0029]

[Equation 4]

Here, the spatially displaced signal (Ca) and the non-displaced signal (Cb) contained in each color difference signal are expressed by the following equations (Equation 5) for C1 to C4.

[0031]

[Equation 5]

In order to obtain a pseudo frame video signal from the entire video signal, it is necessary that Ya and Yb are substantially equal and Ca and Cb are approximately equal in (Equation 3) and (Equation 5). This shows that C1 or C2 is suitable for spatial position control. Therefore, hereinafter, only the case where the spatial position control is C1 and C2 will be described.

Next, FIG. 5 shows a circuit configuration example of the signal processing outline shown in FIG. In FIG. 5A, the spatial position control is C1, and FIG.
(b) is the case of C2. In FIGS. 11A and 11B, the same reference numerals are given to those showing the same effect and omitted.
FIG. 5 (a) shows 1 for delay of one horizontal line period of G signal.
H memory 501, adder 502, for gain adjustment
It has a 1/2 amplifier circuit 503, a luminance signal matrix 504 for performing the arithmetic processing shown in (Equation 2), and a color signal matrix 505 for performing the arithmetic processing shown in (Equation 4).
Similarly, FIG. 5B shows a 1H memory 501 and an adder 502 for delaying one horizontal line period of the R signal and the B signal.
And a 1/2 amplifier circuit 503 for gain adjustment, and a luminance signal matrix 5 for performing the arithmetic processing shown in (Equation 3) above.
04, and a color signal matrix 505 that performs the arithmetic processing shown in (Equation 4). In the digital signal processing circuit configured as described above, the phase of the color signal can be matched by providing the vertical direction interpolation function having the 1H memory, that is, the averaging circuit of the 2H line. Perform processing. Moreover, FIG. 5 (a), (b)
It can be seen from FIG. 9A that the spatial position control C1 (shifting the G signal) is more suitable for reducing the circuit scale.

Further, the phase matching for the color signals whose spatial positions (phases) shown in FIG. 5 are displaced is L in the vertical direction.
Since the PF process is performed, the high frequency characteristic deteriorates. The video signal is the entire three color signals (for example, G, R, B
When viewed from a luminance signal synthesized from a signal by a matrix operation), the frequency characteristic shows the phase of the R and B signals as shown in (Equation 3) in the luminance signal matrix performing the arithmetic operation shown in (Equation 2). The space position control C2 to shift is
It has better high frequency characteristics than C1 which shifts G signal. Also in the color signal matrix for performing the arithmetic processing shown in (Equation 4), the spatial position control C2 is superior to C1 in the high frequency characteristics as shown in (Equation 5). As described above, it is understood that the spatial position control C2 is more suitable for the high frequency characteristic in the signal processing when the interpolation processing is not performed.

Further, in the color signal matrix for producing the color difference signal, a false signal is generated in the high frequency band because the high frequencies of the color signals are different. For example, when white is photographed, the color difference signals RY and BY need to be at zero level. However, in the case of the above spatial position control C2,
In the high frequency band, G signal exists (G ≠ 0), but R and B
Since there is no signal (R = B = 0), the color difference signal R-
As for Y and BY, as shown in (Equation 6), a false color signal is generated instead of the zero level. A detailed description of this problem is given in Japanese Patent Application No. 4-195096, which has been described as a prior art, and therefore the description thereof will be omitted below.

[0036]

[Equation 6]

Next, the digital signal processing circuit 1 shown in FIG.
The circuit configuration of No. 06 will be described with reference to FIG. In the figure, 601 is a line memory for storing signals in the 1H period, 602 is an adder, 603 is a 1/2 amplifier circuit for gain adjustment, 604 is a signal interpolation circuit composed of the constituent elements 601 to 603, and 605 is Y1 for creating luminance signal Y1
Matrix circuit, 606 is Y2 which creates a luminance signal Y2
A matrix circuit, 607 is a C1 matrix circuit that creates a color signal C1, 608 is a C2 matrix circuit that creates a color signal C2, 609 is a matrix circuit composed of components 605 to 608, and 610 is an aperture for the luminance signals Y1 and Y2. , A luminance signal processing circuit for performing processing such as coring, a white balance 611 for the color signals C1 and C2,
A color signal processing circuit that performs processing such as color reproduction.

The operation of the memory circuit and the image pickup device configured as described above will be described below with reference to FIGS. 7, 8 and 9. In FIG. 6, the signal interpolation circuit 604 creates an interpolation signal from the signals of two consecutive lines.
This is shown in FIG. FIG. 7 shows a signal created from the R, G, B signals in which the R, B signals are out of phase with the G signal in the vertical direction of 1/2 line. For example, in the R and B signals, from the signals of the (n-2) line and the n line, (m
The interpolated signal of line -1) is generated from the signals of line n and line (n + 2) and the interpolated signal of line (m + 1) is generated. Similarly, the signal of line (n-1) and line (n + 1) of the signal G is m The line interpolation signal is generated from the (n + 1) line signal and the (n + 3) line signal as the (m + 2) line interpolation line signal. In this way, an interpolation signal is created from the signals of two consecutive lines. Next, the matrix circuit 609 in FIG. 6 performs matrix signal processing using the R, G, and B signal interpolation circuit output signals. In FIG. 8, similar to FIG. 7, the luminance signals Y _m-1 , Y _m , which are created from the R, G, B signals in which the R, B signals are out of phase with the G signal in the vertical direction of 1/2 line, ... and color difference signal (RY) _m-1 ,
(RY) _m , ... and (BY) _m-1 , (B-
Y) _m , ... As shown in FIG. 8, the color signals R _m-1 , G _m-1 , B _m-1 and R _m , G _m , B _m are expressed by (Equation 7).
, The luminance signals Y _m-1 and Y _m and the color difference signal (R-
Y) _m-1 , (RY) _m and (BY) _m-1 , (BY) _m
Is shown in (Equation 8).

[0039]

[Equation 7]

[0040]

[Equation 8]

The Y1 matrix circuit 605 performs the Y _m-1 matrix calculation, and the Y 2 matrix circuit 606 performs the Y _m matrix calculation. Similarly, (R-
The C1 matrix circuit 607 performs the matrix operation of Y) _m-1 and (BY) _m-1 and the C2 matrix circuit 608 performs the matrix operation of (RY) _m and (BY) _m . Also, C
In 1 and C2 matrix, (RY) signal and (BY)
The signals are thinned out and then output in a time division manner. FIG. 9 shows an output signal of the digital signal processing circuit 106 of FIG. 1 which performs the above operation. For example, (Y _m-1,1 ) in FIG. 9 represents the luminance signal of the first pixel on the (m-1) line. In FIG. 9, the color signals show the case where the color difference signals are chronologically thinned out every two pixels. In the figure, the (m-1) line is output as the Y1 signal and the m line signal is output as the Y2 signal.

Further, in FIG. 1, the system control circuit 11
6 and the drive control circuit 103 control the image sensor drive circuit 102 to perform normal read drive (drive in which the vertical phases of R, G, and B match) on the image sensor unit 101, and obtain R, By processing the G and B output signals, the digital signal processing circuit 106 outputs the field signals (Y0, C0) that have not been pseudo-framed. This signal is directly input to the encoder and output as a television signal.

Digital signal processing circuit 10 in FIG.
The output signals 6 (Y1, Y2, C1, C2) are subjected to signal compression, field memory control, and signal decompression.

This will be described with reference to FIG. Figure 10
1A shows the signal compression circuit 107 and each field memory (Y3 field memory, Y4 field memory, C3 field memory, C4 field memory) 1 in FIG.
08-111, the memory control circuit 112, and the processing of the memory unit configured by the signal restoration circuit 113 are processed by two signals (see FIG.
Is a block diagram for explaining S ₁ and S ₂ ), and these two signals may be frame position signals, and even if the pseudo frame signal by the vertical pixel shift of the RGB image pickup element described above, another frame signal such as a mechanical frame signal is used. Since a still image frame signal using a shutter may be used, it will be described below as an independent memory circuit. In the figure, 100
1 low frequency signal S ₁ signal S _1L and high frequency signal S
Band division filter (hereinafter referred to as FLT) circuit for dividing into _1H , 1
002 is a band division FLT circuit that divides the S ₂ signal into a low frequency signal S _{2 L} and a high frequency signal S _2H, and 1003 is S.
₁ , S _1L , S _1H , S ₂ , S _2L , S _2H signals are combined to form S ₃ ,
A signal synthesizing circuit for generating the S ₄ signal, 1004 is a signal compression circuit including a band division FLT circuit 1001, a band division FLT circuit 1002, and a signal synthesizing circuit 1003.
Reference numeral 05 denotes a field memory circuit 1 for storing / reading the S ₃ signal, 1006 denotes a field memory circuit 2 for storing / reading the S ₄ signal, 1007 denotes a field memory circuit 10.
05 and the field memory circuit 1006 to control the memory control circuit 1008, the field memory circuit 1005
Band division FLT circuit 3, 1009 for dividing the output signal (S _3F ) of the above into a low frequency signal S _3L and a high frequency signal S _3H.
Is a band division FLT circuit for dividing the output signal (S _4F ) of the field memory circuit 1006 into a low frequency signal S _4L and a high frequency signal S _4H , 1010 is S _3F , S _3L , S _3H , S
_The signal combining circuits B and 1011 for combining the _4F , S _4L and S _4H signals to create the S ₅ and S ₆ signals are the band division FLT circuit 100.
8 and band division FLT circuit 1009 and signal synthesis circuit 101
It is a signal restoration circuit composed of 0s.

The operation of the memory circuit of this embodiment having the above structure will be described below. In the signal compression circuit, the S ₁ signal, which is one of the two field signals constituting the frame signal, is band-divided FLT.
The circuit 1001 includes a low frequency signal S _1L and a high frequency signal S _1.
The signal is divided into _1H and the other signal, S ₂ signal, is divided into a low-frequency signal S _2L and a high-frequency signal S _2H by the band-division FLT circuit 1002.
_{The 1} , S _1L , S _1H , S ₂ , S _2L and S _2H signals are combined to combine the S ₃ and S ₄ signals stored in the field memory circuits 1005 and 1006. Field memory circuit 1005
And 1006 are controlled by the memory control circuit 1007 to output the output signals S _3F and S _4F, respectively. Next, in the signal restoration circuit 1011, the band division FLT circuit 1008 divides this S _3F signal into a low-frequency signal S _3L and a high-frequency signal S _3H , and the S _4F signal is divided by the band-division FLT circuit 1009 into a low-frequency signal. Signal S _4L and high frequency signal S _4H
, And then the signal combining circuit 1010 divides the signal into S _3F ,
The S _3L , S _3H , S _4F , S _4L , and S _4H signals are combined to create an S ₅ signal that is approximately equal to the S ₁ signal and an S ₆ signal that is approximately equal to the S ₂ signal.

FIG. 10B shows another example of the structure of the memory section composed of the signal compression circuit 1004, the field memories 1005 and 1006, the memory control circuit 1007, and the signal decompression circuit 1011. The difference between FIG. 2B and FIG. 3A is that the signal synthesis circuit 1003 is S ₁ , S _1L ,
S _1H , S ₂ , S _2L , S _2H signals are combined to create S ₃ signal,
The memory control circuit 1007 is the field memory circuit 100.
5, the signal synthesis circuit 1010 synthesizes the S _3F , S _3L , and S _3H signals to create the S ₅ and S ₆ signals, and the signal restoration circuit 101.
1 is a band division FLT circuit 1008 and a signal synthesis circuit 101.
It is a point composed of zero.

The operation of the memory circuit configured as described above will be described below. Signal compression circuit 10
In 04, the band division FLT circuit 1001 converts the S ₁ signal which is one of the two field signals constituting the frame signal into the low frequency signal S _1L and the high frequency signal S _1H.
And the other signal, the S ₂ signal, is divided into bands F
The LT circuit 1002 divides into a low frequency signal S _2L and a high frequency signal S _2H , and then a signal synthesis circuit 1003 synthesizes the S ₁ , S _1L , S _1H , S ₂ , S _2L and S _2H signals. The S ₃ signal stored in the field memory circuit 1005 is synthesized. The field memory circuit 1005 is the memory control circuit 1
It is controlled by 007 and outputs the output signal S _3F signal.
Next, in the signal restoration circuit 1011, the band division FLT circuit 1008 divides this S _3F signal into a low frequency signal S _3L and a high frequency signal S _3H , and then the signal synthesis circuit 1010 outputs the above S _3F , S _3L , The S _3H signals are combined to create an S ₅ signal that is approximately equal to the S ₁ signal and an S ₆ signal that is approximately equal to the S ₂ signal. Here, the difference between FIG. 10 (a) and FIG. 10 (b) is whether the signal combining circuit 1003 outputs the S ₃ and S ₄ signals after combining,
Whether to output only the S ₃ signal, an example of the configuration of (b) is shown in FIG.
This will be described with reference to 0 (c). In FIG. 7C, the S ₃ signal is S ₁ ,
A sampled signal S ₂ alternately, the sampling after LPF processing again each with the same clock (CLK1, CLK2) with respect to S ₃ signals can be configured by adding the S ₃ and HPF processing signals. As described above, according to the methods (a) and (b), the field memory circuit 1006 and the band division FLT are
The presence or absence of the circuit 1009 is determined. Hereinafter, the case of FIG. 10A will be described in detail.

Next, a circuit configuration example of the field memory circuit will be described with reference to FIG. In the figure, (a) shows the case where the input signal is an analog signal, and (b) shows the case where the input signal is a digital signal. In FIG. 11A, reference numeral 1101 denotes an analog / digital conversion circuit (hereinafter referred to as A / D conversion circuit), 1
102 is a field memory, 1103 is a digital / analog conversion circuit (hereinafter referred to as D / A conversion circuit), 1104 is the entire field memory circuit, 1105 is a memory control circuit for controlling the field memory circuit 1104, and FIG.
In (b), 1106 is a sub-sampling circuit, 11
Reference numeral 07 is a field memory circuit, 1108 is an oversampling circuit, 1109 is the entire field memory circuit, 1
A memory control circuit 110 controls the field memory circuit 1109.

The operation of the field memory circuit configured as above will be described below. In FIG. 11A, the analog input signal becomes a digital signal by the A / D conversion circuit 1101, and is stored / read in the field memory 1102 by the memory control circuit 1105, and the output signal becomes an analog signal by the D / A conversion circuit 1103. Is output. In this way, when the input signal is an analog signal, sampling (quantization) is performed using a clock with a frequency that matches the signal band, and the data is stored in the field memory.
It is configured with a minimum memory capacity by performing reading and returning to an analog signal again. In FIG. 11B, the digital input signal is the sub-sampling circuit 1106.
Is sampled at a low frequency (thinning sampling), resulting in a small amount of data and the memory control circuit 111.
0 is stored / read out in the field memory 1107, and the output signal thereof is oversampling circuit 1108.
Is sampled at the original higher frequency. In this way, when the input signal is a digital signal, it is sampled by the sub-sampling process with a clock having a frequency that matches the band of the signal, stored in and read from the field memory, and then the original signal is restored again to match the next process. Oversampling is performed at high frequencies.

Next, the subsampling process and the oversampling process will be described with reference to FIGS.

FIG. 12 is a schematic explanatory view showing the frequency characteristic of the sub-sampling processing. FIG. 12 (1) is a frequency characteristic diagram of the input signal, where the sampling frequency is f _ck and the signal band is 1/2 f _ck . (The dotted line indicates the harmonic component generated by the sampling process). FIG. 2B is a characteristic diagram of the digital filter that limits the frequency band of the input signal, and is intended to limit the band of the input signal to 1/2. FIG. 3C is a frequency characteristic diagram of the filter output signal. (4) is a frequency characteristic diagram of the signal obtained by sampling the filter output signal again at 1/2 f _ck . By limiting the band of the input signal to 1/2 with the filter shown in (2), Sampling frequency is 1/2 as in (4)
A signal having f _ck and a signal band of 1/4 f _ck is obtained, and the signal has no deterioration due to the aliasing signal.

Next, FIG. 13 shows the oversampling process.
FIG. 12 is a schematic explanatory diagram showing frequency characteristics, and FIG.
Sampling frequency shown in (4) is 1 / 2f_ck, The signal band
1 / 4f _ckIs the input signal of
Shows the harmonic components generated by the processing.) Figure (2) is
Input signal f_ckFrequency characteristics of the signal sampled again with
FIG. Figure (3) is a characteristic diagram of the digital filter.
Yes, filter band is 1 / 4f_ckIs. Figure 2 (2)
Filter the pulling signal as shown in (3) in the figure.
Signal bandwidth is 1 / 4f_ckBecomes Figure (4) is the same figure
The band shown in (3) is 1 / 4f_ckThe filtered signal that is
The frequency characteristics of the signal to be combined with are shown in this figure (3).
The band to be added with the filtered signal shown in is 1 / 4f
_ck~ 1 / 2f_ckThe case of the high frequency component signal of is shown.
In the figure (5), the band shown in the figure (3) is 1 / 4f._ckIs Phil
Signal and the band shown in (4) in the figure is 1 / 4f_ck~ 1 /
2f_ckFIG. 6 is a frequency characteristic diagram of a signal after addition with the synthesized signal of
The resampling signal shown in (2) of the figure is shown in (3) of the figure.
Signal band 0f_ck~ 1/2
f_{c k}It is possible to obtain a signal that is not degraded by the aliasing signal of
it can. In this way, when the input signal is a digital signal
Is a filter to remove the deterioration caused by the aliasing signal.
The sub-sampling process with
Sampling with a clock of a certain frequency,
Field memory.
Oversampling process with filter on read signal
By doing so again the original
Performs sampling processing at high frequency.

Next, FIG. 14 shows a block diagram of the above subsampling processing and oversampling processing in the field memory circuit. In FIG. 1A, 140
1, 1403, 1406 and 1408 are latch circuits for sampling an input signal, 1402 is a low-pass filter (hereinafter referred to as LPF) for band limiting signals, 1404 is a sub-sampling circuit composed of latch circuits 1401, 1403 and LPF 1402, 1405. Is a field memory that stores / reads digital signals, 1407 is an LPF that limits the band of signals, and 1409 is a latch circuit 1.
This is an oversampling circuit composed of 406, 1408 and LPF 1407.

In the field memory circuit configured as described above, the input signal is sampled at the f _ck frequency and then L
The signal band is limited to 1/2 by PF1402, and 1 / 2f _ck
Sampling at frequency. The signal sampled at this 1/2 f _ck frequency is 1/2 in the field memory 1405.
Store / read at _fck frequency. After that, the field memory output signal is sampled at the f _ck frequency, subjected to LPF processing for removing frequencies in an unnecessary band, and sampled and output at the f _ck frequency. As described above, after the amount of signal information is limited by the subsampling circuit 1404, the memory capacity is reduced by storing / reading in the field memory 1405, and the oversampling circuit 1409 is used.
Output to the signal restoration circuit 1011 shown in FIG.

Next, in FIG. 14 (2), 1401-1
Reference numeral 409 is the same as (1) in the figure, and 1410 is an upper / lower bit division circuit for dividing the upper bit and the lower bit of the signal, 1411, 1413, 1415, 1417 and 14
18 is a latch circuit for sampling an input signal, 141
2 is an inverting circuit, 1414 is a selector circuit for switching two input signals, 1416 is latch circuits 1411, 1413,
1415, a high bit-> low bit conversion circuit composed of an upper / lower bit division circuit 1410, an inversion circuit 1412 and a selector circuit 1414, and 1419 an upper / lower bit combination circuit 1420 for combining the divided upper bits and lower bits. Is a low bit-> high bit conversion circuit composed of latch circuits 1417 and 1418 and an upper / lower bit combination circuit 1419.

The field memory circuit configured as described above will be described focusing on the points different from FIG. 14 (1). LPF after sampling the input signal at f _ck frequency
The signal band is limited to 1/2 by 1402 and sampling is performed at the 1/2 f _ck frequency. The signal sampled at this 1/2 f _ck frequency is a high bit-> low bit conversion circuit 141.
It is divided by 6 into upper bits and lower bits. For example, when the input signal is 8 bits, it is divided into a signal of upper 4 bits and a signal of lower 4 bits, sampled at a 1 / 2f _ck frequency with an inverted phase, and a 8-bit 1 signal is 4-bit time series 2 by a selector circuit 1414. Become a signal (8->
4 conversion). This time series 2 signal is sent to the field memory 140.
5 is stored / read at the f _ck frequency. After that, the field memory output signal is low bit-> high bit conversion circuit 1
At 420, the divided high-order bits and low-order bits are combined. Continuing the example above, a 4-bit time series 2
The signal becomes an 8-bit signal again by the latch circuits 1417 and 1418 of the f _ck frequency and the upper / lower bit synthesizing circuit 1419 (4-> 8 conversion). After that, the LP is sampled at the f _ck frequency to remove the frequency in the unnecessary band.
F processing is performed, and sampling output is performed at the f _ck frequency. In this way, after limiting the information amount of the signal by the sub-sampling circuit 1404, the high bit-> low bit conversion circuit 141
It is divided into upper bits and lower bits by 6 and stored / read in the field memory 1405. As a result, in the field memory 1405, the number of addresses is the same as that before the memory reduction process, the number of bits is reduced, and the entire memory capacity is reduced. After that, the oversampling circuit 1409
Output to the signal restoration circuit 1011 shown in FIG. As described above, by performing bit conversion after band limitation, a memory with a normal number of addresses can be used as a field memory, and the memory control unit can be used without changing the circuit design. It will be easier. In particular, in the field memory of an image, a 4-bit memory is often cheaper than an 8-bit memory, which enables cost reduction.

Next, FIG. 15 shows the signal compression circuit shown in FIG.
Path 1004 and field memory circuits 1005 and 100
6. Memory circuit component composed of signal restoration circuit 1011
An example of body constitution is shown. In FIG. 15, 1501 is an input signal
LPF that limits the frequency band of
The difference signal between the processed signal and the signal that has not been LPF processed.
The subtractor 1503 is composed of an FLT circuit and a subtractor.
Low frequency signal component (S_1L) And high frequency signal components (S
_1H), A band division FLT circuit for obtaining
S with the same configuration_2LAnd S_2HBand division FLT circuit for obtaining
05 is S_1HAnd S _2HIs an adder for adding
Issue (S_1H+ S_2H) 1/2 gain circuit, 1507
S_1LAnd (S_1H+ S_2H) / 2 and adder, 1508 is
S₃1505 and 1507 and 1/2 gain circuit 1 for obtaining
506 and a signal combining circuit, 1509 is S₃To
Memory, S_3FField memory for reading out data, 1510
Is S_Four(= S_2L) Sub-sampling circuit, 151
1 stores / reads the output signal of the sub sampling circuit 1510
Field memory to be projected, 1512 is a field memory
Memory 1511 output signal oversampling times
, 1513 is a subsampling circuit 1510 and
Field memory 1511 and oversampling circuit 1512
S composed of and_4FA field memory circuit that outputs
1514 is a field memory 1509 and a field memo
1515 is a memory control circuit that controls the re-circuit 1513.
S with the same configuration as 1503_3FHFrequency division FLT times
Road, 1516 is S_3FHAnd S_4FAnd add S₆An adder,
1517 is S_Five(= S_3F) And S₆Signal synthesis circuit that outputs
Is.

The memory circuit configured as described above will be described below. Input signal S having equal frequency band
₁ and S ₂ are the band division FLT circuit 1503 and the band division F
The LT circuit 1504 produces S _1L , S _1H and S _2L , S _2H , and the signal synthesis circuit 1508 produces S ₃ (= S _1L + (S _1H + S _2H ).
/ 2) and S ₄ (= S _2L ) are output. Here, the frequency band of S ₃ is equal to the input signals S ₁ and S ₂ , but the frequency band of S ₄ is limited and narrower than the input signals S ₁ and S ₂ .
Next, S ₃ is stored / read out in the field memory 1509, S ₄ is processed in the field memory circuit 1511 and stored / read out in the field memory 1511. As shown in FIG.
Can be realized with a structure having a smaller memory capacity than the field memory 1509. Next, the output signal S _3F of the field memory 1509 is the band division FLT circuit 1515.
S _3F and S _3FH are generated by the field memory 151.
The output signal of 1 is processed by the oversampling circuit 1512 and becomes S _4F . After that, the signal synthesizing circuit 1517
Outputs ₅ (= S _3F ) and S ₆ (= S _3FH + S _4F ). here,
S ₅ and S ₆ are given by (Equation 9), and when S ₁ and S ₂ are signals at consecutive frame positions, S _1L ≈S _2L , so S ₅ ≈
It becomes substantially equal to S ₁ , S ₆ ≈S ₂ .

[0059]

[Equation 9]

As described above, the band division FLT circuit 1503
And band division FLT circuit 1504 and signal combining circuit 1508
, And a band division FLT circuit 1515
By providing the signal restoration circuit including the signal synthesis circuit 1517 and the signal synthesis circuit 1517, it is possible to reduce the memory capacity of the field memory 1511 and then create S ₅ and S ₆ that are substantially equal to S ₁ and S ₂ again. Is.

Next, the signal compression circuit 1004 and field memory circuits 1005 and 100 shown in FIG.
6 shows a second specific configuration example of the memory circuit configured by the signal restoration circuit 1011. In FIG. 16, 1601 limits the frequency band of the input signal to limit the low frequency signal component (S _2L
= S ₄ ), 1602 is a field memory for storing S ₁ / reading out S _3F , 1603 is a sub-sampling circuit for S _2L , 1604 is a field memory for storing / reading an output signal of the sub-sampling circuit 1603, 1605 is An oversampling circuit for the output signal of the field memory 1604, 1606 is a field memory circuit which outputs S _4F composed of the subsampling circuit 1603, the field memory 1604 and the oversampling circuit 1605, and 1607 is the field memory 1602 and the field memory circuit 1606. A memory control circuit for controlling, 1608 is an LPF for limiting the frequency band of an input signal, 1609 is an LPF processed signal and an LPF.
Subtractor 1610 for obtaining difference signal from unprocessed signal
Is a band division FLT circuit configured by an FLT circuit 1608 and a subtractor 1609 to obtain a high frequency signal component (S _3FH ), and 1611 is an adder that adds S _3FH and S _4F to obtain S ₆ .
Reference numeral 1612 is a signal combining circuit for outputting S ₅ (= S _3F ) and S ₆ .

Regarding the memory circuit configured as described above,
Will be described below. Input signal S having equal frequency band
₁And S₂Out of S₂Is a band division FLT circuit and signal synthesis
S by LPF1601 which constitutes a circuit_2L(= S_Four)When
Become. Where S_FourOf the input signal S₁And S₂
It is limited and narrower than. Then S₁Feel
Stored in / read from the memory 1602, S_FourFeel
Field memory 1606
It is stored / read out in 604, but it is shown in Fig. 14 etc.
The field memory 1604 is the field memory 16
It can be realized with a configuration that has a smaller memory capacity than the 02.
is there. Next, the output signal S of the field memory 1602_3F
Is S by the band division FLT circuit 1610._3F, S_3FHWhen
And the output signal of the field memory 1604 is oversized.
S processed by sampling circuit 1605_4FBecomes That
After that, the signal synthesizing circuit 1612_Five(= S_3F) And S₆(= S
_3FH+ S _4F) Is output. Where S_FiveAnd S₆Is (Equation 10)
And S₁And S₂Is a signal of consecutive frame positions
Case S_1L≒ S_2LTherefore, S₆≒ S₂Is almost equal to.

[0063]

[Equation 10]

As described above, the signal compression circuit having the LPF configuration, the band division FLT circuit 1610 and the signal synthesis circuit 16 are provided.
By providing the signal restoration circuit consisting of 12, it is possible to reduce the memory capacity of the field memory 1604, and then again create S ₅ equal to S ₁ and S ₆ approximately equal to S ₂ .

As described above, according to this embodiment, by providing the signal compression circuit and the signal decompression circuit, the memory circuit reduces the capacity of one of the two field memories to half. Therefore, the memory capacity can be reduced to 3/4.

Further, the image pickup section for generating the pseudo frame signal shown in FIG. 1, the memory circuit section including the signal compression circuit 107, each of the field memories 108 to 111, and the signal restoration circuit 113 has a luminance (Y) or color. Half the capacity of one of the two field memories in (C)
Since the memory capacity can be reduced to 3/4, the memory capacity can be reduced to 3/4 as a whole, and the high frequency characteristic of the pseudo frame signal is deteriorated as compared with the signal without the pseudo frame processing. Therefore, the memory reduction processing can realize the memory reduction without causing a difference in the high frequency components.

FIG. 17 is a block diagram of a memory circuit showing a second embodiment of the present invention, and the output signals (Y5, Y6, C5, C6) of the signal restoration circuit 113 in FIG. 1 are the memory output processing circuit 114. FIG. 7 is a block diagram showing a process utilizing the fact that the signal is a pseudo frame signal. In the figure, 1701 is a signal compression circuit, 1702 is a field memory circuit, 1703 is a signal decompression circuit, 1704 is a memory circuit composed of a signal compression circuit 1701, a field memory circuit 1702 and a signal decompression circuit 1703, 17
Reference numeral 05 is a memory control circuit for controlling the field memory circuit 1702, 1706 is a luminance signal electronic zoom circuit for performing an interpolation operation using Y5 and Y6 signals which are luminance output signals of the signal restoration circuit 1703, and 1707 is a signal restoration circuit 1703.
A color signal electronic zoom circuit for performing an interpolation operation using the C5 and C6 signals which are the color output signals, and a memory output processing circuit 1708 including a luminance signal electronic zoom circuit 1706 and a color signal electronic zoom circuit 1707.

The operation of the memory circuit configured as described above will be described below, focusing on the difference from the first embodiment. The memory circuit 1704 receives the input signals Y1, Y
2 and C1 and C2 frame signals in FIG. 1 of the first embodiment.
The required field memory capacity is reduced by compressing the band of one signal with the circuit configurations shown in FIGS. That is, the output signal Y of the signal compression circuit 1701
3, Y4 and C3, C4, one signal, for example Y
4 and C4 have a band 1 compared to the other signals Y3 and C3.
/ 2. The field memory circuit 17
The output signal of 02 becomes Y5, Y6 and C5, C6 which are substantially equal to the input signals Y1, Y2 and C1, C2 by the signal restoration circuit 1703. Here, it can be understood from (Expression 9) in the case of FIG. 15 and (Expression 10) in the case of FIG. 16 that the output signal of the signal restoration circuit 1703 has a difference in the high frequency component as compared with the input signal. This difference is shown in (Equation 11) for the case of FIG. 15 and (Equation 12) for the case of FIG. Further, the brightness signal electronic zoom circuit 1706 and the color signal electronic zoom circuit 1707 obtain an interpolation signal by interpolation calculation processing. An example of this interpolation calculation is shown in (Equation 13). This interpolation signal Y7
Is equivalent to performing LPF processing on Y5 and Y6 that create Y7, so that the high frequency component of the frequency characteristic deteriorates. Similarly, the interpolation signal C7 is C5 and C6 that create C7.
The LPF process is equivalent to the LPF process, and the high frequency component of the frequency characteristic is deteriorated. Therefore, by using the output signal of the memory circuit 1704 for the electronic zoom circuit, the output signals Y7 and C7 of the memory output processing circuit 1708 using the output signal of the memory circuit (= signal restoration circuit) are converted into the input signal Y1.
Compared with the output signal of the memory output processing circuit which is an interpolation signal using Y2 and Y2 and C1 and C2, the difference in the high frequency components is smaller than the differences shown in (Equation 11) and (Equation 12). .

[0069]

[Equation 11]

[0070]

[Equation 12]

[0071]

[Equation 13]

As described above, according to this embodiment, by providing the memory circuit 1704 and the memory output processing circuit 1708 including the luminance signal electronic zoom circuit 1706 and the color signal electronic zoom circuit 1707, the memory circuit 1704 is realized. It is possible to reduce the difference in the high frequency component that occurs.

In the above embodiment, the drive control of the image pickup device is performed in order to shift the phases of the three color signals R, G, B. In addition to the drive control, for example, 3 for obtaining three color signals. When the solid-state image sensor is fixedly bonded to the color separation prism, the position of the solid-state image sensor is shifted in the vertical direction, which is different from the conventional case, or the refractive index inside the three-color separation prism is manipulated to bend the light path of the color signal. It is also possible to shift the phase of.

In the above embodiment, the case where the three color signals are solid-state image pickup device output signals has been described, but the same applies to signals stored in a field memory, a frame memory or the like. Memory read control can be performed as a means for shifting the phase.

Further, in the above-mentioned embodiment, only the output of the R, G, B signals is shown for the image pickup device section, but the configuration has three solid-state image pickup devices, each of which has an R
A three-plate type image pickup device for obtaining G / B signals or a two-plate type image pickup device having two image pickup elements, one image pickup element for G signal and the other image pickup element for R signal and B signal, can be considered.

In the above embodiment, the three color signals are R, G and B, but the present invention is not limited to this. For example, three color signals of yellow, cyan and magenta can be used. .

Further, in the above-mentioned embodiment, Y is used as a pseudo frame signal (frame position signal created by interpolation).
Although the case where the 1, Y2 signal and the C1, C2 signal are output has been described, the present invention is not limited to this, and the R, G, and B signals can be used for the R1.
In some cases, pseudo frame signals of R2, G1, G2, B1, and B2 may be output. At this time, more memory capacity can be reduced by similar memory reduction processing, or sensitivity to the resolution of the human eye can be reduced. Considering this, the Y signal may output a pseudo frame signal, and the C signal may output a normal field signal.

In the above embodiment, two circuit configurations of the signal compression circuit and the signal decompression circuit are shown. However, the present invention is not limited to this, and a synthesized signal in which the frequency band is limited to the input signal is created. It is also possible to realize it with another configuration that restores after that.

Further, in the above embodiment, the description has been given of the case of the memory circuit alone, the image pickup apparatus constituted by the pseudo frame image pickup section + memory circuit, and the image pickup apparatus constituted by the memory circuit + interpolation interpolation circuit. However, the configuration is not limited to these, and it is possible to further reduce the difference in the high frequency components due to the memory reduction by the configuration of the pseudo frame imaging unit + memory circuit + interpolation interpolation circuit.

[0080]

As described above, according to the present invention, by providing the signal compression circuit and the signal decompression circuit, the memory circuit can reduce the capacity of one of the two field memories to half. Therefore, it is possible to reduce the memory capacity.

Further, the image pickup section for generating the pseudo frame signal and the memory circuit section composed of the signal compression circuit and the signal decompression circuit are one of the two field memories of luminance (Y) or color (C). The memory capacity can be reduced to 1/2, and the memory capacity can be reduced. In addition, the high frequency characteristics of the pseudo frame signal are degraded compared to the signal without pseudo frame processing. Therefore, it is possible to realize memory reduction without causing a difference in high frequency components by the memory reduction processing.

Further, by providing the memory circuit section and the memory output processing circuit composed of the luminance signal electronic zoom circuit and the color signal electronic zoom circuit, it is possible to reduce the difference in the high frequency components caused by the memory circuit. It is possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an image pickup apparatus according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of frame accumulation drive control of an image pickup element of the image pickup apparatus according to the first embodiment.

FIG. 3 is an explanatory diagram of field accumulation drive control of an image pickup element of the image pickup apparatus according to the first embodiment.

FIG. 4 is an explanatory diagram of signal processing of the image pickup apparatus according to the first embodiment.

FIG. 5 is a block diagram showing an internal configuration of a digital signal processing circuit of the image pickup apparatus according to the first embodiment.

FIG. 6 is a block diagram showing an internal configuration of a digital signal processing circuit of the image pickup apparatus according to the first embodiment.

FIG. 7 is an explanatory diagram for explaining signal processing of a digital signal processing circuit of the image pickup apparatus according to the first embodiment.

FIG. 8 is an explanatory diagram for explaining signal processing of a digital signal processing circuit of the image pickup apparatus according to the first embodiment.

FIG. 9 is an explanatory diagram of an output signal of the digital signal processing circuit of the image pickup apparatus according to the first embodiment.

FIG. 10 is a block diagram showing a configuration of a memory circuit according to the first embodiment.

FIG. 11 is a block diagram showing another configuration of the memory circuit according to the first embodiment.

FIG. 12 is an explanatory diagram for explaining the operation of the memory circuit according to the first embodiment.

FIG. 13 is an explanatory diagram for explaining the operation of the memory circuit according to the first embodiment.

FIG. 14 is a field memory circuit configuration diagram of the memory circuit according to the first embodiment.

FIG. 15 is a circuit configuration diagram of a memory circuit according to the first embodiment.

FIG. 16 is another circuit configuration diagram of the memory circuit according to the first embodiment.

FIG. 17 is a block diagram showing a configuration of a memory circuit according to a second embodiment of the present invention.

FIG. 18 is a block diagram showing the configuration of a conventional imaging device with a memory function.

FIG. 19 is a block diagram showing an internal configuration of a digital signal processing circuit of a conventional image pickup device with a memory function.

[Explanation of symbols]

101 image sensor part 102 image sensor drive circuit 103 drive control circuit 104 analog signal processing circuit 105,1101 analog-digital conversion circuit 106 digital signal processing circuit 107,1004,1701 signal compression circuit 108-111,1005,1006,1104,11
09, 1513, 1606, 1702 field memory circuit 112, 1007, 1105, 1110, 1514, 1
607, 1705 Memory control circuit 113, 1011, 1703 Signal restoration circuit 114, 1708 Memory output processing circuit 115 Encoder circuit 116 System control circuit 501, 601 1H line memory 502, 602, 1505, 1507, 1516, 16
11 adder 503, 603 1/2 amplifier circuit 504 luminance signal matrix circuit 505 color signal matrix circuit 604 signal interpolation circuit 605 Y1 matrix circuit 606 Y2 matrix circuit 607 C1 matrix circuit 608 C2 matrix circuit 609 matrix circuit 610 luminance signal processing circuit 611 Color signal processing circuit 1001, 1002, 1008, 1009, 1503
1504, 1515, 1610 Band division FLT circuit 1003, 1010, 1508, 1517, 1612
Signal combining circuit 1102, 1107, 1405, 1509, 1511,
1602, 1604 Field memory 1103 Digital / analog conversion circuit 1106, 1404, 1510, 1603 Subsampling circuit 1108, 1409, 1512, 1605 Oversampling circuit 1401, 1403, 1406, 1408, 1411,
1413, 1415, 1417, 1418 Latch circuit 1402, 1407, 1501, 1601, 1608
LPF 1410 Upper / lower bit division circuit 1412 Inversion circuit 1414 Selector circuit 1416 High bit-> low bit conversion circuit 1419 Upper / lower bit combination circuit 1420 Low bit-> high bit conversion circuit 1502,1609 Subtractor 1506 1/2 gain circuit 1704 Memory Reduction circuit 1706 Luminance signal electronic zoom circuit 1707 Color signal electronic zoom circuit

Claims (22)

[Claims] 1. A means for obtaining two field signals S1 and S2 constituting a frame signal, a first band division circuit for band-dividing the field signal S1, and a band division for the field signal S2. And a first band division circuit output signal, the first band division circuit output signal, and the second band division circuit output signal to obtain combined signals S3 and S4 signals. A signal combining circuit and a first memory circuit for storing the combined signal S3; a second memory circuit for storing the combined signal S4; and a third memory circuit for performing band division on the output signal of the first memory circuit. A band division circuit, a fourth band division circuit for performing band division on the second memory circuit output signal, the first memory circuit output signal and the second memory circuit output signal, The third band dividing circuit output signal of the second
A second signal synthesizing circuit for obtaining synthesized signals S5 and S6 from the output signal of the band splitting circuit, and at least one of the synthesized signals S3 and S4 has a narrower frequency band than the field signal S1 or the field signal S2. . 2. A means for obtaining two field signals S1 and S2 constituting a frame signal, a first band division circuit for performing band division on the field signal S1, and a band division for the field signal S2. A second band division circuit for performing the above, and a first signal combination circuit for obtaining a combination signal S3 from the two field signals S1 and S2, the first band division circuit output signal, and the second band division circuit output signal. And a memory circuit that stores the combined signal S3, a third band division circuit that performs band division on the memory circuit output signal, a combined signal from the memory circuit output signal and the third band division circuit output signal A second signal combining circuit for obtaining S5 and S6, wherein the information amount of the combined signal S3 is smaller than the information amount obtained by adding the field signal S1 and the field signal S2. No memory circuit. 3. The memory circuit according to claim 1, wherein the band division circuit is composed of at least one of a high-frequency pass filter and a low-frequency pass filter. 4. The low-frequency signal of the band-divided field signal S1 is S1L and the high-frequency signal is S1H, and the low-frequency signal of the band-divided field signal S2 is S1L.
2L, when S2H is the high frequency signal, S3 = S1L + (S1
H + S2H) / 2, S4 = S2L, S5 = S1L + (S1H + S2H) /
2. The memory circuit according to claim 1, wherein S6 = S2L + (S1H + S2H) / 2. 5. When the low frequency signal of the band-divided field signal S2 is S2L, S3 = S1, S4 = S2L
4. The memory circuit according to claim 1, wherein S5 = S1 and S6 = S2L + S1H. 6. A means for obtaining two field signals S1 and S2 constituting a frame signal, a first band division circuit for performing band division on the field signal S1, and a band division for the field signal S2. A second band division circuit for performing the above, a first signal combination circuit for obtaining combined signals S3 and S4 signals from the band-divided S1 and band-divided S2 signals, and a first memory circuit for storing the S3 , A second memory circuit for storing S4, a third band division circuit for performing band division on the first memory circuit output signal, and a band division for the second memory circuit output signal. A fourth band division circuit for performing, and a second signal combining circuit for obtaining a combined signal S5 and S6 signal from the band-divided first memory circuit output signal and the band-divided second memory circuit output signal. And an interpolation calculation circuit for obtaining an interpolation signal by performing an interpolation calculation from the S5 and S6 signals, and at least one of the S3 and S4 is S1 or S2.
Memory circuit with a narrower frequency band. 7. Three different color signals C1, C2 and C3.
A first vertical phase shifter for shifting the vertical phase of the color signal C2 with respect to the color signal C1 by a constant pitch p1, and the vertical phase of the color signal C3 with a constant pitch p2. A second vertical phase shifter that shifts the color signal C1 and a color signal C that is vertically phase-shifted with the color signal C1.
A frame operation circuit for obtaining pseudo frame signals S1 and S2 from C2 and C3; and a first band division for the pseudo frame signal S1.
And a second band division circuit for dividing the pseudo frame signal S2.
Band division circuit, a first signal combination circuit for obtaining combined signals S3 and S4 from the pseudo frame signals S1 and S2, the first band division circuit output signal, and the band division circuit output signal, and the combined signal A first memory circuit for storing S3; a second memory circuit for storing the combined signal S4; a third band division circuit for performing band division on the output signal of the first memory circuit; A fourth band division circuit for performing band division on the second memory circuit output signal, the first memory circuit output signal, the second memory circuit output signal, the third band division circuit output signal, and the third band division circuit output signal. Fourth
A second signal combining circuit for obtaining combined signals S5 and S6 from the output signal of the band dividing circuit, and at least one of the combined signals S3 and S4 has a narrower frequency band than the pseudo frame signal S1 or S2. 8. Three different color signals C1, C2 and C3.
8. The image pickup apparatus according to claim 7, wherein the means for obtaining is obtained from a plurality of solid-state image pickup elements. 9. The plurality of solid-state image pickup devices include a first solid-state image pickup device that obtains a color signal C1, a second solid-state image pickup device that obtains a color signal C2, and a third solid-state image pickup device that obtains a color signal C3. The image pickup apparatus according to claim 8. 10. The image pickup apparatus according to claim 8, wherein the plurality of solid-state image pickup elements include a first solid-state image pickup element that obtains a color signal C1 and a second solid-state image pickup element that obtains color signals C2 and C3. 11. Three different color signals C1, C2 and C
The image pickup device according to claim 7, 8, 9 or 10, wherein 3 is three color signals R, G and B. 12. Three different color signals C1, C2 and C
3. The three color signals R, G and B, and C1 = G.
The imaging device described. 13. The pitch p1 and the pitch p2 are defined as p1 = p
2. The method according to claim 7, 8, 9, 1 characterized in that 2 = p.
The imaging device according to 0, 11 or 12. 14. The values of the pitch p1 and the pitch p2 are as follows:
The imaging device according to claim 7, 8, 9, 10, 11, 12 or 13, wherein 0 ≤ p1 <1 and 0 ≤ p2 <1. 15. The pitches p1 and p2 are amounts corresponding to 1/2 line of one field image, according to claim 7, 8, 9, 10, 11, 12, 13, or 14. Imaging device. 16. The first vertical phase shift unit and the second vertical phase shift unit are configured to include a drive control circuit that controls a drive circuit that drives a plurality of solid-state image pickup devices. 7, 8, 9, 10, 11, 12, 13,
The imaging device according to 14 or 15. 17. The first vertical phase shift unit and the second vertical phase shift unit are arranged such that the mounting positions of the plurality of solid-state image pickup devices are spatially shifted in the vertical direction by a fixed pitch p1 and p2. Claims 7, 8, 9, 1
The imaging device according to 0, 11, 12, 13, 14 or 15. 18. The first vertical phase shift unit and the second vertical phase shift unit space a drive control circuit that controls a drive circuit that drives a plurality of solid-state image pickup devices, and a mounting position of the plurality of solid-state image pickup devices. 7. A structure including a step of vertically displacing in the vertical direction by a constant pitch. 7. The structure according to claim 7, 8, 9, 10, 11, 12, 13, 14, or 1.
5. The imaging device according to item 5. 19. The drive control circuit performs frame accumulation drive control, performs odd field reading on a part of the plurality of image sensors at the same time, and performs even field reading on the remaining image sensors. The image pickup device according to claim 16, wherein 20. The drive control circuit performs field accumulation drive control, performs odd field reading on a part of the plurality of imaging elements at the same time, and performs even field reading on the remaining imaging elements. The image pickup device according to claim 16, wherein 21. The frame operation circuit comprises three phase difference circuits.
9. A plurality of signals are created from one color signal C1, C2 and C3, and the plurality of signals are in a positional relationship of a frame signal.
13, 14, 15, 16, 17, 18, 19 or 20
The imaging device described. 22. The frame arithmetic circuit comprises three phase difference circuits.
A luminance signal or a color difference signal is created from two color signals C1, C2, and C3, and at least the luminance signal is a plurality of signals, and the plurality of luminance signals have a positional relationship with a field signal forming a frame signal. Claims 7, 8, 9, 10, 11, 12, 13, 14, 15, 1
The imaging device according to 6, 17, 18, 19, 20 or 21.