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JPH06252148A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPH06252148A
JPH06252148A JP3569593A JP3569593A JPH06252148A JP H06252148 A JPH06252148 A JP H06252148A JP 3569593 A JP3569593 A JP 3569593A JP 3569593 A JP3569593 A JP 3569593A JP H06252148 A JPH06252148 A JP H06252148A
Authority
JP
Japan
Prior art keywords
conductive particles
bumps
hardness
wiring
fine conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3569593A
Other languages
Japanese (ja)
Other versions
JP3283947B2 (en
Inventor
Miki Mori
三樹 森
Masayuki Saito
雅之 斉藤
Nobuo Iwase
暢男 岩瀬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP3569593A priority Critical patent/JP3283947B2/en
Publication of JPH06252148A publication Critical patent/JPH06252148A/en
Application granted granted Critical
Publication of JP3283947B2 publication Critical patent/JP3283947B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To provide a semiconductor device which has a low connection resistance and provides reliable connections in oxidation-prone wiring, such as aluminum wiring. CONSTITUTION:A semiconductor element 11 having bumps 14 of HA in height and A in hardness, is connected to a wiring substrate 12 to be mounted, with conductive microparticles 15 of PHIB (HA<=PHIB) in particle size and B (A<B) in hardness in-between. For the purpose, the semiconductor element chip is heated and compressed with the bumps, HA in height and A in hardness, covered with the conductive microparticles 15, PHIB (HA<=PHIB) in particle size and B (A<B) in hardness, abut on the connection regions on the wiring substrate 12.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置およびその
製造方法に係り、特に半導体素子と基板間のフェイスダ
ウンボンディング接続に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to face-down bonding connection between a semiconductor element and a substrate.

【0002】[0002]

【従来の技術】近年、半導体装置をより薄く、より高密
度に実装する方法として、実装用基板上に樹脂を用いて
半導体素子を載置接続し、ワイヤを用いて電気的接続を
行うようにしたいわゆるワイヤボンディング実装に代わ
り、半導体素子にバンプを形成して直接基板に接続して
実装するフェイスダウン実装技術が開発されてきてい
る。フェイスダウン実装はスーパーコンピュータなどに
適用するフリップチップと呼ばれる実装技術と、液晶デ
ィスプレイなどに適用するCOG(Chip on g
lass)とにわけることができる。
2. Description of the Related Art In recent years, as a method of mounting a semiconductor device thinner and with higher density, a semiconductor element is mounted and connected on a mounting substrate by using a resin, and an electrical connection is performed by using a wire. Instead of the so-called wire bonding mounting, face-down mounting technology has been developed in which bumps are formed on a semiconductor element and directly connected to a substrate for mounting. Face-down mounting is a flip-chip mounting technology applied to supercomputers and COG (Chip on chip) applied to liquid crystal displays.
It can be divided into

【0003】このCOG実装では、半導体素子と基板を
接続する際の電気的接続はバンプと呼ばれる突起によっ
て行い、機械的接続は樹脂によって行うという方法が一
般的であった。COG実装の1手法として、図10に示
すように半導体素子1を基板2上の配線4に対し、半導
体素子上に形成された低融点で硬度の低い半田バンプ3
を圧接することにより接続用樹脂を介することなく初期
接続を行う技術も提案されているが、この方法では、半
田バンプを溶融し基板上の配線と合金化することで接続
をとるため、配線としてはアルミニウムなどの半田に濡
れにくい金属が用いられている場合には、バンプ自身で
は十分な機械的接続をとることができず接続には必ず樹
脂が必要となる。
In this COG mounting, it has been a general method to electrically connect a semiconductor element and a substrate with a projection called a bump and mechanically connect with a resin. As one method of COG mounting, as shown in FIG. 10, the semiconductor element 1 is connected to the wiring 4 on the substrate 2 with solder bumps 3 formed on the semiconductor element and having a low melting point and a low hardness.
Although a technique has been proposed in which the initial connection is performed by pressing the resin without using a connecting resin, in this method, the solder bumps are melted and alloyed with the wiring on the substrate to make the connection. When a metal such as aluminum which is hard to be wetted by solder is used, the bump itself cannot make a sufficient mechanical connection, and a resin is always required for the connection.

【0004】また、この方法では、基板側の配線がアル
ミニウムなどの強固な酸化膜を形成し易い金属である場
合には、接続に際し配線表面が酸化膜で覆われているこ
とになり、その酸化膜を十分に破壊することができない
ため接続信頼性が低いという問題があった。
Further, in this method, when the wiring on the substrate side is made of a metal such as aluminum that easily forms a strong oxide film, the surface of the wiring is covered with the oxide film at the time of connection, and the oxidation thereof occurs. There is a problem that the connection reliability is low because the film cannot be sufficiently destroyed.

【0005】酸化膜を破壊する方法として微小導電粒子
を介して接続する方法があるがこの方法においても微小
導電粒子が接続時にアルミニウムの酸化膜を破壊して接
続を行っているものの微小導電粒子は電気的接続を得る
ためのみであり、機械的接続は樹脂によって得なければ
ならず、許容電流値が小さい、接続抵抗が高いという問
題があった。またこのCOB実装では樹脂の硬化時に電
気的接続が達成されるため、不良が生じた場合にも修復
が困難であるという問題もあった。
As a method of destroying the oxide film, there is a method of connecting via fine conductive particles. In this method as well, although the fine conductive particles destroy the aluminum oxide film at the time of connection to make the connection, It was only for obtaining electrical connection, and mechanical connection had to be obtained by resin, and there were problems that the allowable current value was small and the connection resistance was high. Further, in this COB mounting, since electrical connection is achieved when the resin is cured, there is also a problem that even if a defect occurs, it is difficult to repair.

【0006】[0006]

【発明が解決しようとする課題】このように、従来のフ
ェイスダウン接続では、配線がアルミニウムなどの酸化
されやすい材料である場合、接続に際し配線表面が酸化
膜で覆われていることになり、酸化膜を十分に破壊する
ことができず、良好な接続を行うことができないという
問題があった。
As described above, in the conventional face-down connection, when the wiring is made of a material such as aluminum which is easily oxidized, the surface of the wiring is covered with an oxide film at the time of connection. There was a problem that the film could not be sufficiently broken and good connection could not be made.

【0007】本発明は前記実情に鑑みてなされたもの
で、アルミニウムなどの酸化されやすい配線において
も、接続抵抗が小さく、信頼性の高い接続を達成するこ
とのできる半導体装置の実装構造および実装方法を提供
することを目的とする。
The present invention has been made in view of the above circumstances, and a mounting structure and a mounting method of a semiconductor device capable of achieving a highly reliable connection with a small connection resistance even in an easily oxidized wiring such as aluminum. The purpose is to provide.

【0008】[0008]

【課題を解決するための手段】そこで本発明では、実装
用の配線基板上に、高さHA 硬度Aのバンプを有する半
導体素子を粒径ΦB (HA ≦ΦB )、硬度B(A<B)
の微小導電粒子を介して接続したことを特徴とする。
Therefore, in the present invention, a semiconductor element having bumps of height H A hardness A is formed on a wiring board for mounting with a grain size Φ B (H A ≦ Φ B ), a hardness B ( A <B)
It is characterized in that they are connected via the minute conductive particles.

【0009】また本発明の方法では、実装用の配線基板
上の接続領域に、粒径ΦB (HA ≦ΦB )、硬度B(A
<B)の微小導電粒子で覆われた、高さHA 硬度Aのバ
ンプが当接するようにして半導体素子チップを加熱加圧
するようにし、半導体素子を配線基板上に微小導電粒子
を介して接続する工程とを含むことを特徴とする。
In the method of the present invention, the grain size Φ B ( HA ≦ Φ B ), hardness B (A
The semiconductor element chip is heated and pressed so that the bumps of height H A hardness A covered with the minute conductive particles of <B) come into contact with each other, and the semiconductor element is connected to the wiring board via the minute conductive particles. And a step of performing.

【0010】[0010]

【作用】本発明によれば、バンプ上に形成された微小導
電粒子からなるパターンを介して配線との接続を行うよ
うにしているため、配線表面に酸化膜が形成されている
場合にも、バンプよりも硬度の高い微小導電粒子を用い
ているため、微小導電粒子は押しつぶされることなく酸
化膜を破壊し、バンプに微小導電粒子が囲まれた状態で
良好な接続を達成することができる。
According to the present invention, since the connection with the wiring is made through the pattern composed of the fine conductive particles formed on the bump, even when the oxide film is formed on the wiring surface, Since the fine conductive particles having a hardness higher than that of the bumps are used, the fine conductive particles can destroy the oxide film without being crushed, and good connection can be achieved in a state where the fine conductive particles are surrounded by the bumps.

【0011】また接続界面に絶縁性の樹脂残渣がなく、
許容電流値が高く接続抵抗の低い接続が可能となる。
Further, there is no insulating resin residue at the connection interface,
Connection with high allowable current and low connection resistance is possible.

【0012】さらにまた、微小導電粒子が接続領域に選
択的に形成されているため、微細ピッチの配線に対して
も信頼性の高い接続を行うことができる。
Furthermore, since the fine conductive particles are selectively formed in the connection region, highly reliable connection can be performed even for fine pitch wiring.

【0013】[0013]

【実施例】以下、本発明の実施例について図面を参照し
つつ詳細に説明する。
Embodiments of the present invention will now be described in detail with reference to the drawings.

【0014】図1は本発明実施例の半導体装置を示す説
明図である。
FIG. 1 is an explanatory view showing a semiconductor device according to an embodiment of the present invention.

【0015】この半導体装置は、半導体チップ11を配
線基板12上に形成されたアルミニウム配線13に接続
したもので、半導体チップ11のボンディングパッドと
配線13との間がボンディングパッドに形成されたイン
ジウム(In)/鉛(Pb)からなるバンプ14および配線
13の接続領域にパターン形成された樹脂ボールをニッ
ケル(Ni)めっき層で被覆した粒径13μm の微小導電
粒子15とを介して接続されるようにしたことを特徴と
する。
In this semiconductor device, a semiconductor chip 11 is connected to an aluminum wiring 13 formed on a wiring substrate 12, and indium (bonding pad between the semiconductor chip 11 and the wiring 13 is formed as a bonding pad). In order to connect via bumps 14 made of (In) / lead (Pb) and resin balls patterned in the connection area of wiring 13 with minute conductive particles 15 of 13 μm in diameter coated with nickel (Ni) plating layer It is characterized by having done.

【0016】次に、この半導体装置の製造工程について
説明する。
Next, the manufacturing process of this semiconductor device will be described.

【0017】この方法は図2にフローチャートを示すよ
うに、配線基板の形成プロセス100と,半導体チップ
の形成プロセス200と、微小導電性粒子パターンを形
成するための転写用基板の形成プロセス300と、これ
らを用いて実装する実装プロセス400との4つのプロ
セスから構成される。
As shown in the flow chart of FIG. 2, this method includes a wiring substrate forming process 100, a semiconductor chip forming process 200, a transfer substrate forming process 300 for forming a fine conductive particle pattern, It is composed of four processes including a mounting process 400 for mounting using these.

【0018】配線基板の形成プロセスは図3(a) に示す
ように、ガラス基板20に真空蒸着法により酸化アルミ
ニウム薄膜を形成しこれをフォトリソグラフィによりパ
ターニングし図3(b) に示すようにアルミニウムからな
る配線パターン21を形成する。
As shown in FIG. 3 (a), the wiring board is formed by forming an aluminum oxide thin film on the glass substrate 20 by a vacuum deposition method, patterning it by photolithography, and then using aluminum as shown in FIG. 3 (b). A wiring pattern 21 made of is formed.

【0019】また半導体チップの形成プロセス200は
図4(a) に示すように所望の素子領域の形成されたシリ
コン基板31表面に形成されたアルミニウムパターンか
らなるボンディングパッド32上に真空蒸着法によりバ
リアメタル層33としてのチタン/銅層を形成する(図
4(b) )。
Further, as shown in FIG. 4A, the semiconductor chip forming process 200 is performed by vacuum deposition on a bonding pad 32 formed of an aluminum pattern formed on a surface of a silicon substrate 31 on which a desired element region is formed. A titanium / copper layer is formed as the metal layer 33 (FIG. 4 (b)).

【0020】そして図4(c) に示すようにこの上層にレ
ジストRを塗布しこれをパターニングしたのち、めっき
液に浸漬し、バリアメタル層を電極として電気めっきを
行いレジストから露呈するバリアメタル層33表面に選
択的にインジウム(In)/鉛(Pb)層のバンプ14を形
成する(図4(d) )。
Then, as shown in FIG. 4 (c), a resist R is coated on this upper layer, patterned, and then immersed in a plating solution and electroplated using the barrier metal layer as an electrode to expose the barrier metal layer from the resist. Bumps 14 of indium (In) / lead (Pb) layer are selectively formed on the surface 33 (FIG. 4 (d)).

【0021】最後に図4(e) に示すように、レジストR
を剥離し、バンプ14をマスクとしてバリアメタル層を
エッチング除去し、バンプを供えた半導体チップが完成
するる。
Finally, as shown in FIG. 4 (e), the resist R
Is removed, the barrier metal layer is removed by etching using the bumps 14 as a mask, and the semiconductor chip provided with the bumps is completed.

【0022】さらに転写用基板の形成プロセス300
は、図5(a) に示すように転写用基板40上にスクリー
ン41を介して、樹脂ボールをニッケル(Ni)めっき層
で被覆した粒径13μm の微小導電粒子15を散布し、
スキージ42を用いて微小導電粒子15を転写用基板上
にほぼ均一に揃える(図5(b) ) 。なおここでは微小導
電粒子15のみを印刷形成したが、微小導電粒子15に
樹脂ペーストを混ぜたものを用いるようにしてもよい。
Further, a transfer substrate forming process 300.
As shown in FIG. 5 (a), fine conductive particles 15 having a particle diameter of 13 μm in which resin balls are coated with a nickel (Ni) plating layer are dispersed on a transfer substrate 40 through a screen 41,
The squeegee 42 is used to uniformly arrange the fine conductive particles 15 on the transfer substrate (FIG. 5 (b)). Although only the fine conductive particles 15 are formed by printing here, a mixture of the fine conductive particles 15 with a resin paste may be used.

【0023】実装に際してはまず、このようにして形成
された転写用基板40上の微小導電粒子15のパターン
上にバンプが当接するように(図6(a) )バンプを形成
した半導体チップ11を接触させ、インジウム/鉛の融
点以下に加熱しつつ加圧して微小導電粒子をバンプ上に
埋没させたのち、図6(b) に示すように上方に引き上
げ、図6(c) に示すようにバンプ上にのみ選択的に微小
導電粒子15を付着させる。ここでは数層程度の微小導
電粒子15が形成されているものとする。この方法では
バンプの高さを利用して微小導電粒子15をバンプ上に
のみ選択的に形成するようにしているため、微細パター
ンが容易に形成される。
In mounting, first, the semiconductor chip 11 on which bumps are formed so that the bumps come into contact with the pattern of the fine conductive particles 15 on the transfer substrate 40 thus formed (FIG. 6A). After making contact, and applying pressure while heating below the melting point of indium / lead to bury the fine conductive particles on the bumps, pull them up as shown in FIG. 6 (b), and as shown in FIG. 6 (c). The fine conductive particles 15 are selectively attached only on the bumps. Here, it is assumed that the fine conductive particles 15 of about several layers are formed. In this method, since the fine conductive particles 15 are selectively formed only on the bumps by utilizing the height of the bumps, a fine pattern can be easily formed.

【0024】このようにして、バンプ14に微小導電粒
子15が埋没してなる半導体チップを図7(a) に示すよ
うに配線基板のアルミニウム配線パターン13の接続領
域にフェイスダウンで当接させ、加熱加圧することによ
り図7(b) に示すように圧接により接合させる。このと
きの圧力は転写時の圧力より高く設定される。
In this way, the semiconductor chip in which the fine conductive particles 15 are buried in the bumps 14 is brought into face-down contact with the connection area of the aluminum wiring pattern 13 of the wiring board as shown in FIG. 7 (a). By applying heat and pressure, they are joined by pressure welding as shown in FIG. 7 (b). The pressure at this time is set higher than the pressure at the time of transfer.

【0025】そして最後に図7(c) に示すように、樹脂
封止を行い、半導体装置が完成する。 このようにして
形成された半導体装置は、微小導電粒子を圧接すること
によってアルミニウム配線上に形成された酸化膜を破壊
し、また微小導電粒子をバンプが包み込む構造で接続さ
れるため、許容電流値が増大し、接続抵抗の低減をはか
るとともに放熱性の向上をはかることが可能となる。
Finally, as shown in FIG. 7C, resin sealing is performed to complete the semiconductor device. Since the semiconductor device formed in this way is connected in such a structure that the oxide film formed on the aluminum wiring is destroyed by pressure contact with the fine conductive particles, and the bumps surround the fine conductive particles, the allowable current value is increased. It is possible to reduce the connection resistance and improve the heat dissipation.

【0026】なお、前記実施例では、バンプをインジウ
ム/鉛で形成するとともに微小導電粒子をニッケルめっ
きで形成したが、これらの組み合わせに限定されること
なく、硬度と粒径およびバンプ高さが HA ≦ΦB A<B HA :バンプ高さ,A:バンプ硬度,ΦB :粒径、B:
微小導電粒子硬度 の関係を満たす組み合わせであれば良い。例えばバンプ
として銅、ニッケル、金、すず/鉛,インジウム/鉛,
インジウム/錫,ビスマス/すず/鉛等でも良い。また
微小導電粒子としては銅、ニッケル、すず/鉛の金属粒
子,あるいは樹脂ボールにニッケルや金などのめっき層
を形成したものなどでもよい。
Although the bumps are formed of indium / lead and the fine conductive particles are formed of nickel in the above embodiment, the combination is not limited to these, and the hardness, the grain size, and the bump height are H. A ≤ Φ B A <B H A : bump height, A: bump hardness, Φ B : grain size, B:
Any combination that satisfies the relationship of the hardness of the fine conductive particles may be used. For example, bumps such as copper, nickel, gold, tin / lead, indium / lead,
Indium / tin, bismuth / tin / lead, etc. may be used. The fine conductive particles may be copper, nickel, tin / lead metal particles, or resin balls on which a plating layer of nickel or gold is formed.

【0027】半導体素子や実装の歩留まりが高ければ、
実装に先立ちあらかじめ樹脂をポッティングしておき、
配線とバンプとの接続と同時に硬化させるようにしても
よい。 また、微小導電粒子を転写用基板に塗布する場
合、接着用樹脂と微小導電粒子を混在させた状態で塗布
し、これを半導体基板に転写し、基板と圧接するように
してもよい。さらには、転写をすることなく基板上や半
導体素子上に直接微小導電粒子を塗布するようにしても
よい。塗布を行う際、樹脂の粘着性を利用したり、印刷
によって選択的に微小導電粒子を配置することもでき
る。また、図8(a) に示すようにさらに樹脂と混在させ
た微小導電粒子15を塗布することによって図8(b) に
示すように強固に固着されるため、実装後の樹脂封止工
程を省くことができ、実装後の樹脂封止工程を省くこと
ができる。この構造では、微小導電粒子の硬度BがA<
Bを満たすように硬いため、容易に酸化膜を破壊し良好
な接続を達成することができる。
If the yield of semiconductor elements and mounting is high,
Resin is potted in advance before mounting,
You may make it harden | cure simultaneously with the connection of a wiring and a bump. When the fine conductive particles are applied to the transfer substrate, the adhesive resin and the fine conductive particles may be applied in a mixed state, transferred to the semiconductor substrate, and pressed against the substrate. Further, the fine conductive particles may be directly applied onto the substrate or the semiconductor element without transferring. When applying, it is possible to utilize the adhesiveness of the resin or to selectively arrange the fine conductive particles by printing. Further, as shown in FIG. 8 (a), by applying the fine conductive particles 15 mixed with resin further, it is firmly fixed as shown in FIG. 8 (b), so that the resin sealing step after mounting is performed. It can be omitted, and the resin sealing step after mounting can be omitted. In this structure, the hardness B of the fine conductive particles is A <
Since it is hard so as to satisfy B, the oxide film can be easily destroyed and good connection can be achieved.

【0028】次に本発明の第2の実施例として図面を参
照しつつ詳細に説明する。
Next, a second embodiment of the present invention will be described in detail with reference to the drawings.

【0029】この例では図9に示すようにバンプを第1
のバンプ14aと第2のバンプ14bの2層構造で形成
したことを特徴とする。ここで第1のバンプ14aは金
からなり第2のバンプ14bはインジウム/錫からなる
ものとする。金バンプ/インジウム/錫バンプの2段バ
ンプ構造をとることにより、バンプ高さを高くし、熱衝
撃に強い構造とすることができるとともに、さらに第1
のバンプ14aの存在により、接続の際に第2のバンプ
の広がりを抑制することができショートの発生を抑制す
ることができるため、微細ピッチの接続を達成すること
ができる。他部については前記第1の実施例と同様であ
る。
In this example, first bumps are formed as shown in FIG.
The bumps 14a and the second bumps 14b have a two-layer structure. Here, the first bump 14a is made of gold and the second bump 14b is made of indium / tin. By adopting a two-step bump structure of gold bump / indium / tin bump, the bump height can be increased and the structure is resistant to thermal shock.
Due to the presence of the bumps 14a, the spread of the second bumps can be suppressed at the time of connection and the occurrence of a short circuit can be suppressed, so that fine pitch connection can be achieved. Other parts are the same as those in the first embodiment.

【0030】すなわちこの半導体装置は、半導体チップ
11を配線基板12上に形成されたアルミニウム配線1
3に接続したもので、半導体チップ11のボンディング
パッドと配線13との間がボンディングパッドに形成さ
れた金からなる第1のバンプ14aおよびインジウム/
錫からなる第2のバンプ14bおよび配線13の接続領
域にパターン形成されたニッケルの微小導電粒子15S
とを介して接続されるようにし、さらに半導体チップと
配線基板との間を樹脂16で封止したことを特徴とす
る。
That is, in this semiconductor device, the aluminum wiring 1 in which the semiconductor chip 11 is formed on the wiring substrate 12 is used.
The first bump 14a made of gold and formed on the bonding pad between the bonding pad of the semiconductor chip 11 and the wiring 13 and indium /
Nickel fine conductive particles 15S patterned in the connection region between the second bump 14b made of tin and the wiring 13
And the semiconductor chip and the wiring board are sealed with resin 16.

【0031】ここで第1のバンプの硬度Aと第2のバン
プの硬度Cと微小導電粒子の硬度Bとの間にはC<A,
C<Bの関係あるいは、C<A<Bの関係がなりたつこ
とが望ましい。また第1のバンプは接合温度で溶融しな
いものを選択するのが望ましい。
Here, between the hardness A of the first bump, the hardness C of the second bump and the hardness B of the fine conductive particles, C <A,
It is desirable that the relationship of C <B or the relationship of C <A <B be satisfied. Further, it is desirable to select the first bump that does not melt at the bonding temperature.

【0032】また前記実施例では、第1のバンプを金、
第2のバンプをインジウム/錫としたが、金バンプをさ
らに硬い銅バンプとし、第2のバンプを錫/鉛としたと
きにも安定した接続を得ることが可能となる。なおバン
プは連続して電気めっきで形成するようにしてもよい。
In the above embodiment, the first bump is gold,
Although the second bump is made of indium / tin, a stable connection can be obtained even when the gold bump is made of a harder copper bump and the second bump is made of tin / lead. The bumps may be continuously formed by electroplating.

【0033】さらに、微小導電粒子は酸化膜を破壊する
目的から、球形よりも破砕状をなすものであることが望
ましい。さらに、微小導電粒子の粒径を変えることによ
り酸化膜を破壊するものと電気的接続をつかさどるもの
とにわけることもできるさらに酸化膜を破壊するために
微小導電粒子としてより硬いダイヤモンド粉末を混ぜた
り、ダイヤモンド粉末に金属めっきをした粒子を用いる
ことによってより効果を発揮せしめることが可能とな
る。また配線材料と微小導電粒子との接触電位など化学
的性質によって酸化還元反応が起こり、配線表面の酸化
膜を除去し、接続を安定化するような材料系を選ぶこと
も効果的である。
Furthermore, it is desirable that the fine conductive particles have a crushed shape rather than a spherical shape for the purpose of destroying the oxide film. Furthermore, by changing the particle size of the fine conductive particles, it can be divided into those that destroy the oxide film and those that control the electrical connection.To further destroy the oxide film, mix harder diamond powder as the fine conductive particles. Further, it is possible to exert the effect more by using the particles obtained by metal-plating the diamond powder. It is also effective to select a material system that stabilizes the connection by removing an oxide film on the surface of the wiring and causing an oxidation-reduction reaction due to a chemical property such as a contact potential between the wiring material and the fine conductive particles.

【0034】[0034]

【発明の効果】以上説明してきたように、本発明によれ
ば、酸化されやすい材料からなる配線パターンを形成し
た配線基板との接続も確実でかつ信頼性の高いものとな
り、微細ピッチの接続を有する半導体装置を提供するこ
とができる。
As described above, according to the present invention, the connection with the wiring board on which the wiring pattern made of a material that is easily oxidized is formed is reliable and highly reliable. A semiconductor device having the semiconductor device can be provided.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例の半導体装置を示す図FIG. 1 is a diagram showing a semiconductor device according to a first embodiment of the present invention.

【図2】同半導体装置の製造工程を示すフローチャート
FIG. 2 is a flowchart showing manufacturing steps of the semiconductor device.

【図3】同半導体装置の製造工程を示す図FIG. 3 is a view showing a manufacturing process of the same semiconductor device.

【図4】同半導体装置の製造工程を示す図FIG. 4 is a view showing a manufacturing process of the same semiconductor device.

【図5】同半導体装置の製造工程を示す図FIG. 5 is a view showing a manufacturing process of the same semiconductor device.

【図6】同半導体装置の製造工程を示す図FIG. 6 is a view showing a manufacturing process of the semiconductor device.

【図7】同半導体装置の製造工程を示す図FIG. 7 is a view showing a manufacturing process of the same semiconductor device.

【図8】本発明の他の実施例を示す図FIG. 8 is a diagram showing another embodiment of the present invention.

【図9】本発明の第2の実施例の半導体装置を示す図FIG. 9 is a diagram showing a semiconductor device according to a second embodiment of the present invention.

【図10】従来例の半導体装置を示す図FIG. 10 is a diagram showing a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 半導体素子 2 基板 3 バンプ 4 配線 11 半導体チップ 12 配線基板 13 アルミニウム配線 14 バンプ 15 微小導電粒子 1 Semiconductor Element 2 Substrate 3 Bump 4 Wiring 11 Semiconductor Chip 12 Wiring Board 13 Aluminum Wiring 14 Bump 15 Minute Conductive Particle

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 実装用の配線基板上に、高さHA 硬度A
のバンプを有する半導体素子を粒径ΦB (HA
ΦB )、硬度B(A<B)の微小導電粒子を介して接続
せしめられたことを特徴とする半導体装置。
1. A height H A hardness A on a mounting wiring board.
A semiconductor element having bumps of grain size Φ B (H A
Φ B ), hardness B (A <B), and a semiconductor device characterized by being connected via fine conductive particles.
【請求項2】 素子領域の形成された半導体素子に高さ
A 硬度Aのバンプを形成する工程と、 前記バンプ表面に、粒径ΦB (HA ≦ΦB )、硬度B
(A<B)の微小導電粒子層を形成する工程と、 実装用の配線基板上の接続領域に、この微小導電粒子層
で覆われたバンプが当接するようにして半導体素子を加
熱するとともに加圧することにより、半導体素子を配線
基板上に微小導電粒子を介して接続する工程とを含むこ
とを特徴とする半導体装置の製造方法。
2. A step of forming a bump having a height H A hardness A on a semiconductor element in which an element region is formed, and a grain size Φ B (H A ≦ Φ B ) and a hardness B on the bump surface.
The step (A <B) of forming the fine conductive particle layer is performed, and the semiconductor element is heated while the bumps covered with the fine conductive particle layer are brought into contact with the connection area on the wiring board for mounting. And a step of connecting the semiconductor element to the wiring board via the fine conductive particles by applying pressure.
JP3569593A 1993-02-24 1993-02-24 Semiconductor device and manufacturing method thereof Expired - Fee Related JP3283947B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3569593A JP3283947B2 (en) 1993-02-24 1993-02-24 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3569593A JP3283947B2 (en) 1993-02-24 1993-02-24 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPH06252148A true JPH06252148A (en) 1994-09-09
JP3283947B2 JP3283947B2 (en) 2002-05-20

Family

ID=12449035

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3569593A Expired - Fee Related JP3283947B2 (en) 1993-02-24 1993-02-24 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP3283947B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3805067A1 (en) * 1988-02-18 1989-09-21 Benecke Ag J H Process for producing thermoplastic polymers with a textured surface and thermoplastic polymers produced by an embossing roller
JPH10163270A (en) * 1996-11-29 1998-06-19 Ngk Spark Plug Co Ltd Wiring board with joining bump

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3805067A1 (en) * 1988-02-18 1989-09-21 Benecke Ag J H Process for producing thermoplastic polymers with a textured surface and thermoplastic polymers produced by an embossing roller
JPH10163270A (en) * 1996-11-29 1998-06-19 Ngk Spark Plug Co Ltd Wiring board with joining bump

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Publication number Publication date
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