JPH06250926A - Data processing system provided with cache memory of plural hierarchies - Google Patents

Abstract

PURPOSE:To register data copy for more than the capacity of a secondary cache memory from a main storage into whole cache memories by providing the cache memory with two hierarchies of primary and secondary cache memories and considerably or totally preventing the same data from being redundantly registered in the both cache memories. CONSTITUTION:When request data does not exist in the whole cache memories 10 and 11 against a data read access request from a data processor 100, the primary cache memory 10 registers data being the object of access, which is transferred from the main storage 103, and the secondary cache memory 11 does not register the data. The secondary cache memory 11 registers data only when invalidated data is generated when data is registered in the primary cache memory 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing system, and more particularly to a data processing system having a cache memory of two or more layers and a plurality of layers.

[0002]

2. Description of the Related Art In recent years, operating frequencies of microprocessors have been improved more and more, and microprocessors operating at 50 MHz and microprocessors having operating frequencies of 100 MHz or more are not uncommon. On the other hand, although DRAM (dynamic RAM) as a main memory is steadily increasing in capacity, its access time has not been improved so much. For this reason, the DRAM is currently unable to keep up with the processing speed of the microprocessor. Generally, in order to maximize the performance of a microprocessor, it is necessary to access data at a speed higher than the processing speed of a data processing device inside the microprocessor. Because of this,
A system including a cache memory between a data processing device and a main memory is widely used.

The cache memory is widely used as an effective means for filling the gap between the processing speed of the data processor and the access speed of the main memory. Specifically, the frequently accessed part of the main memory is copied from the main memory in advance to a relatively small capacity high-speed buffer memory (cache memory) arranged near the data processing device, and the memory is divided into two layers. The memory access is speeded up.
In recent years, not only has a two-layered memory configuration of a data processing device and a main memory been adopted, but a plurality of cache memories such as a primary cache memory and a secondary cache memory have been hierarchically arranged to improve memory access. A data processing system designed for high speed has also been put into practical use.

For example, 8K inside the microprocessor
Built-in primary cache memory, which has a small capacity of about bytes but enables high-speed access, and is external to the microprocessor
A system having a secondary cache memory of about 16 Kbytes to 128 Kbytes, or a microprocessor incorporating a primary cache memory of about 1 Kbyte and a secondary cache memory of about 8 Kbytes has been put into practical use.

The block diagram of FIG. 30 shows an example of the configuration of a conventional data processing system having a two-level cache memory. In FIG. 30, reference numeral 100 indicates a data processing device,
101 indicates a primary cache memory connected to the data processing device 100, 102 indicates a secondary cache memory connected to the primary cache memory 101, and 103 indicates a main memory connected to the secondary cache memory. .

Generally, the main memory 103 is composed of a memory having a capacity of several megabytes to several hundreds of megabytes and a relatively low access speed, whereas the secondary cache memory 102 is a memory of ten to several hundreds of kilobytes. The primary cache memory 101 is composed of several kilobytes of memory. Regarding the data access speed, the main memory 103 can generally access data in hundreds of tens of nanoseconds, whereas the secondary cache memory 102 can access data in tens of nanoseconds to tens of nanoseconds. The cache memory 101 is a few nsec to a dozen nsec
Data can be accessed with.

That is, the main memory 103 and the secondary cache memory
In the order of 102 and the primary cache memory 101, the capacity becomes smaller, but the data can be accessed at high speed. Therefore, a copy of a part of the data in the main memory 103 is copied to the cache memory 101,
By registering in the memory 102 in advance, data can be accessed at high speed without accessing the main memory 103. Further, when the data processing device 100 accesses the primary cache memory 101, it can be accessed at a higher speed than the processing speed of the data processing device 100.

In general, in such a data processing system, the primary cache memory 101 can exchange data only with the data processing device 100 and with the secondary cache memory 102, and the secondary cache memory 101 can exchange data. The cache memory 102 can access data only with the primary cache memory 101 and with the main memory 103. Further, the data processing device 100 cannot directly access the main memory 103.

Next, the operation of the conventional data processing system shown in FIG. 30 will be described. Generally, when a data read access request is issued in the data processing device 100, the data processing device 100 first sets the primary cache memory.
Data read access (104) is performed to 101. When a cache miss (a state in which requested data is not registered in the cache memory) occurs in the primary cache memory 101, the primary cache memory 10
Data read access (105) is performed from 1 to the secondary cache memory 102. Furthermore, if a cache miss also occurs in the secondary cache memory 102,
Data read access (106) is performed from the secondary cache memory 102 to the main memory 103.

From the secondary cache memory 102 to the main memory
Main memory by data read access (106) to 103
The data read from 103 is the secondary cache memory 10
It is transferred (112) to 2 and registered, and further transferred (111) to the primary cache memory 101 and registered, and then transferred (110) to the data processing device 100.

In this series of processing, if a cache hit (a state in which the requested data is registered in the cache memory) is made in the data read access (105) to the secondary cache memory 102, the requested data ( (Hereinafter referred to as hit data) is the primary cache memory 1
The data is transferred (01) to 01, registered, and then transferred (110) to the data processing device 100. When a cache hit occurs in the data read access (105) to the secondary cache memory 102 as described above, the data read access (106) to the main memory 103 is not performed.

When a cache hit occurs in the data read access (104) to the primary cache memory 101, the hit data is transferred (110) to the data processor 100 as it is. This primary cache memory 101
When a cache hit occurs in the data read access (104) to the secondary cache memory 102, neither the data read access (105) to the secondary cache memory 102 nor the data read access (106) to the main memory 103 is performed.

When a data write access request is issued in the data processing device 100, if both the primary and secondary cache memories 101 and 102 are write-through type cache memories, the primary cache memory 101 is always required. The main memory 103 is also used for the secondary cache memory 102.
The data write access (104, 105, 106) is also performed for.

At this time, the data written in the primary cache memory 101, the secondary cache memory 102 and the main memory 103 is the reference numeral 107 → 108 → from the data processor 100.
Transferred via route 109. Then, when a cache write hit occurs in the primary and secondary cache memories 101 and 102, and further in the main memory 103, the data is updated. In particular,
The hit data in the cache memory is the data processing device 10
It is overwritten by the data transferred from 0. By such processing, data consistency is maintained in the write-through cache memory.

Since such a conventional data processing system operates as described above, part of the data in the main memory 103
113 is copied and taken into the secondary cache memory 102, and a part of the data in the secondary cache memory 102 11
4 is copied and taken into the primary cache memory 101. That is, all the data contents stored in the primary cache memory 101 exist in the secondary cache memory 102. Therefore, it is possible to register a copy of data in an amount equal to the capacity of the secondary cache memory 102 in the maximum case in the entire cache memory (the combination of the primary and secondary cache memories 101 and 102). . However, since a part of the data 114 in the secondary cache memory 102 is also duplicated in the primary cache memory 101, the cache memory as a whole is larger than the capacity of the main memory 103 to the secondary cache memory 102. It is impossible to register the amount of data.

FIG. 31 is a block diagram showing a general structure of the primary and secondary cache memories 101 and 102 shown in FIG. 30, and both cache memories 101 and 102 have a common structure. There is. The configuration shown in FIG. 31 is a 4-way set associative cache memory.

In FIG. 31, reference numeral 33 is a data section for copying and storing a part of the data in the main memory 103, and 31 is a tag section for storing a part of an address for the data stored in the data section 33. 32 indicates a valid bit indicating whether the data of the data section 33 is valid or invalid for each entry, and 30 indicates a decoder for selecting one of the entries. Input / output of data to / from the data section 33 is performed in entry units.

Further, reference numeral 36 is a cache hit / miss signal generating section for generating a cache hit / miss signal after comparing the input address with the tag information at the time of cache access, and 37 is a section for receiving data from the data section 33 at the time of cache hit. An output buffer to be read out and a line buffer 35 to receive data from the data bus DBB at the time of cache miss are shown.

Further, since the cache memory shown in FIG. 31 is a 4-way set associative system,
Tag unit 31, data unit 33, valid bit unit 32, decoder
Four sets of 30 and cache hit / miss signal generator 36 are provided for ways 0 to 3, respectively. Generally, when a cache miss occurs, the LRU (Least Recently Used) algorithm control circuit or the like selects which of the ways 0 to 3 the data fetched in the line buffer 35 is registered. The circuit of is not shown in FIG.

The data bus DBA connects the output buffer 37 to the upper cache memory or the data processor 100, and the data bus DBB connects the line buffer 35 to the lower cache memory or the main memory 103. The data bus DBA and the data bus DBB are connected by the bypass route BY. The input address bus ABIN and the output address bus ABOUT connect the cache hit / miss signal generation unit 36, the decoder 30 and the latch 34 to the upper and lower cache memories or the data processing device 100 or the main memory 103.

Next, the operation of the cache memory shown in FIG. 31 will be described. First, the data processing device 100
When a data read access request occurs at, an address for reading data is input to the cache memory from the input address bus ABIN. This address is input to the cache hit / miss signal generation unit 36, the decoder 30, and the latch 34 for tag registration at the time of cache miss.

The decoder 30 decodes several bits of the address and outputs an entry selection signal, and the tag unit 31,
One entry common to each of the valid bit section 32 and the data section 33 is selected. Then, in the cache hit / miss signal generation unit 36, the tag 90a of the selected entry
And valid bit 90b with tag unit 31, valid bit unit
Read from 32 respectively.

The cache hit / miss signal generator 36 compares the tag 90a with the address, and if the results match and the valid bit 90b is valid, it outputs the cache read hit signal 39. On the contrary, if the comparison result of the tag 90a and the address does not match or the valid bit 90b is invalid, the cache hit / miss signal generation unit 36 outputs the cache read miss signal 38. When the cache read / hit signal generation unit 36 outputs the cache read hit signal 39, the data of the entry 90c selected by the decoder 30 is output from the data unit 33 and stored in the output buffer 37. The data taken into the output buffer 37 is output from the data bus DBA to the outside of the cache memory as data (hit data) for the access request.

The cache hit / miss signal generation section
When the cache read miss signal 38 is output from 36, another address is output from the output address bus ABOUT to another cache memory or main memory 103.
Data read access to. The data transferred from the outside in response to this data read access request is taken into the line buffer 35 from the data bus DBB. Then, as soon as the data transfer to the line buffer 35 is completed, the data is registered in the selected entry 90a, 90c of the selected way together with the tag. At this time, the valid bit 90b corresponding to the same entry is also set.

At the time of registering the data, the decision of which way to register the data is controlled by the LRU algorithm or the like as described above. Further, the data input from the data bus DBB is taken into the line buffer 35 and simultaneously output to the data bus DBA through the bypass path BY. With such a cache memory, the conventional data processing system can transfer the requested data at a higher speed at the time of a cache miss.

When a data write access request is issued in the data processing device 100, an address for writing data is input from the input address bus ABIN. The address is input to the cache hit / miss signal generation unit 36, the decoder 30, and the tag registration latch 34 at the time of cache miss, as well as at the time of data read, and at the same time, the decoder 30 causes the tag unit 31 and the valid bit unit. 3
2. One of the entries in the data section 33 is selected. Then, the values of the selected tag unit 31 and valid bit unit 32 are read by the cache hit / miss signal generation unit 36 and used for the cache hit / miss determination.

When a cache write hit occurs, it is necessary to update the hit data in the cache memory. That is, the data transferred from the data bus DBA is output to the data bus DBB through the bypass path BY and taken into the line buffer 35. Then, the data held in the line buffer 35 by the cache write hit signal 40 is registered together with the tag. In the case of a cache write miss, there is no need to update the data in the cache memory, so no processing is executed in the cache memory.

In the block diagrams of FIGS. 32 and 33, the primary and secondary cache memories 101 and 1 configured as shown in FIG.
The configuration when 02 is connected is shown. The lower side of the primary cache memory 101 shown in FIG. 32 and the upper side of the secondary cache memory 102 shown in FIG. 33 are connected. The primary cache memory 101 connected between the data processing device 100 and the secondary cache memory 102 in FIG. 32 is connected between the main memory 103 and the primary cache memory 101 in FIG. The respective secondary cache memories 102 are shown.

32 and 33, the primary cache memory 101 and the secondary cache memory 102 have the same structure as the cache memory shown in FIG. However, the capacity of the secondary cache memory 102 is larger than that of the primary cache memory 10
Greater than 1 capacity.

32 and 33, reference numeral 60 is an address bus (input address bus ABIN of the primary cache memory 101) connecting the primary cache memory 101 and the data processor 100, and 67 is the primary cache memory. A data bus connecting 101 to the data processing device 100, an address bus 62 connecting the secondary cache memory 102 and the main memory 103 (output address bus AB of the secondary cache memory 102).
OUT), 63 is a data bus connecting the secondary cache memory 102 and the main memory 103, and 61 is the primary cache memory 10
Address bus that connects 1 to the secondary cache memory 102 (output address bus ABOU of the secondary cache memory 102
T is an input address bus ABIN) of the secondary cache memory 102, and 65 is a data bus connecting the primary cache memory 101 and the secondary cache memory 102.

The data bus 67 and the data 65 are connected in a bypass path 66 in the primary cache memory 101, and the data bus 63 and the data 65 are connected in a bypass path 64 in the secondary cache memory 102. There is.

Next, the primary and secondary shown in FIGS.
The operation of the configuration when the next cache memories 101 and 102 are connected will be described. First, when a data read access request is generated in the data processing device 100, the address for the data to be accessed is input from the input address bus 60 to the primary cache memory 101.

When a cache read miss occurs in the primary cache memory 101, the cache hit / miss signal generator 36 of the primary cache memory 101 outputs a cache read miss signal 38, thereby outputting an address from the output address bus 61. Secondary cache memory 10
Data read access is performed for 2. Similarly, when a cache read miss occurs in the secondary cache memory 102, the cache read / miss signal 38 is output from the cache hit / miss signal generator 36 of the secondary cache memory 102.
Is output, an address is output from the output address bus 62 and a data read access to the main memory 103 is performed.

Then, the data read from the main memory 103 in response to this data read access is transferred from the data bus 63 to the secondary cache memory 102 and taken into the line buffer 35 thereof, and the secondary cache memory 102 is selected. The bypass route is registered at the same time as the registered entry.
Output from 64 to data bus 65 and primary cache memory
Transferred to 101.

In the primary cache memory 101, the data transferred from the data bus 65 is registered in the selected entry via the line buffer 35, and at the same time, the data is sent from the bypass path 66 to the data bus 67 to output the data processing device 10.
Transfer to 0. In this way, when a cache read miss occurs in both the primary cache memory 101 and the secondary cache memory 102, the data read from the main memory 103 is registered in both the primary and secondary cache memories 101 and 102. Transferred to the data processing device 100 above.

Next, the operation when a cache read miss occurs in the access to the primary cache memory 101 but a cache read hit occurs in the access to the secondary cache memory 102 will be described. When a cache read hit occurs in the secondary cache memory 102, the data of the selected entry is the cache read hit signal.
The data is fetched from the data section 33 to the output buffer by 39.
Then, the data is transferred to the primary cache memory 101 via the data bus 65.

In the primary cache memory 101, the data taken into the line buffer 35 through the data bus 65 is registered in the selected entry, and at the same time, the data is output from the bypass path 66 to the data bus 67, and the data processing device 100
Transfer to. Also in the process of this processing, the data section 33 of the secondary cache memory 102 and the primary cache memory 101
The same data is redundantly registered in the data section 33 of.

Next, a case where a cache read hit occurs when accessing the primary cache memory 101 will be described. When a cache read hit occurs in the primary cache memory 101, the data of the selected entry is fetched from the data section 33 to the output buffer 37 by the cache read hit signal 39 and output to the data bus 67 to the data processing device 100. Transferred. In this case, the data read access from the primary cache memory 101 to the secondary cache memory 102 is not performed.

Next, a case where a data write access request is issued in the data processing device 100 will be described.

When both the primary and secondary cache memories 101 and 102 are of write-through type, data write access is executed to both the primary and secondary cache memories 101 and 102 regardless of cache write hit / miss. To be done.
Therefore, the address for the data write is the primary and secondary cache memory 10 via the route of the address bus 60 → 61 → 62.
It is input to both 1, 102. Also, both cache memory
The data for updating 10 and 11 is transferred through the data bus and the bypass path. That is, reference numeral 67 → 66 →
It is input through the route of 65 → 64 → 63 and is temporarily held in the line buffers 35 of both the primary and secondary cache memories 101 and 102.

Then, the primary and secondary cache memories 101, 1
If the cache write hit occurs in 02, the data held in the respective line buffers 35 are cached by the cache write hit signal 40 together with the tag in both cache memories 10,
Registered in 11. Further, the data write access is also executed to the main memory 103 by the address and the data output from the secondary cache memory 102.

FIG. 34 is a schematic diagram for explaining the details of the data access process when the 8-Kbyte primary cache memory 101 and the 256-Kbyte secondary cache memory 102 are connected. In FIG. 34, by using any bit of the address (32 bits) for data access,
It is shown whether the secondary cache memories 101 and 102 are being accessed.

These primary and secondary cache memories 101,
A 4-way set associative system 102 has a line size (capacity of one entry of each data part 33) of 32 bytes. The number of entries for one way in the primary and secondary cache memories 101 and 102 is 64 and 2048, respectively. Furthermore, both cache memories
The lower bits of the address are assigned to 101 and 102.

In the primary cache memory 101, the data section
The lower 5 bits (27:31) of the address are allocated to the line size 32 bytes of 33, and the 6 bits (21:26) of the address are allocated to the entry (64 entries). Therefore, the tag unit 31 of the primary cache memory 101
21 bits (0:20) of the address for each entry (that is, 32 bits of the address to 11 bits of the address (21: 3)
The rest except 1) is registered respectively. By allocating the addresses in this way, it is possible to register a data copy having a capacity of 8 Kbytes (32 bytes × 64 entries × 4 ways) in the primary cache memory 101.

In the secondary cache memory 102, the lower 5 bits (27:31) of the address are similarly allocated to the line size 32 bytes of the data section 33, and the entry (2048 entries) has 11 bits of the address. (16:26) is assigned. That is, in one way of the secondary cache memory 102 having this configuration, 6 bits (21:
26) Decoded 64-entry primary cache memory
32 101s are arranged side by side. Then, a memory having the same capacity as the 32 primary cache memories 101 is selected by decoding 5 bits (16:20) of the address.

In the tag section 31 of the secondary cache memory 102, 15 bits (0:15) of the address are registered for each entry. By allocating the addresses in this way, it is possible to register a data copy having a capacity of 256 Kbytes (32 bytes × 2048 entries × 4 ways) in the secondary cache memory 102.

Further, although data for addresses having the same lower 11 bits but different upper 21 bits can be registered in the primary cache memory 101, only 4 sets for 4 ways can be registered.
It is possible to register 128 sets (32 pieces × 4 ways) in the secondary cache memory 102. However, since 128 sets of the secondary cache memory 102 include 4 sets of the primary cache memory 101, only 128 sets can be registered in the cache memory as a whole.

Therefore, in the two-level cache memory having the structure as shown in FIG. 34, if the primary cache memory 101 and the secondary cache memory 102 do not have the same data, 132 sets are set. It is possible to register minute data. That is, it goes without saying that more data can be registered in the entire cache memory, which leads to an improvement in the cache hit rate.

[0049]

As described above, in the conventional data processing system having a plurality of layers of cache memory, the lower layer cache memory holds all the data held in the upper layer cache memory.
Considering the cache memory as a whole, it is impossible to register as the entire cache memory more data than the capacity of the cache memory closest to the main memory (generally, the cache memory having the largest capacity).

The present invention has been made in order to solve the above-mentioned problems, and avoids holding duplicated data in the cache memory as a whole as much as possible or eliminates it at all, so that more data can be stored. An object of the present invention is to provide a data processing system in which the cache memory as a whole can be registered to improve the utilization efficiency of the memory.

[0051]

In a data processing system having a plurality of levels of cache memory according to the present invention, when data is read or written in each cache memory, the data is stored in the main memory in each cache memory. It avoids keeping duplicate copies of the same data as much as possible, or does not keep duplicate copies at all.

According to the first aspect of the present invention, cache memories of n layers (where n ≧ 2) or more are arranged between the data processing device and the main memory, and the cache memory of the first layer closest to the data processing device. Is connected to the data processing device and the second-level cache memory by an address bus for data access and a data bus for data transfer, respectively, and the n-th level cache memory closest to the main memory is Another address bus and a data bus are respectively connected to the cache memory of the (n-1) th layer and the main memory, and the cache memory of the mth layer (where 2≤m <n) is the (m-1) th layer. -1) level cache memory and the (m)
In the data processing system in which the cache memory of the +1) th layer is connected to the other address bus and the data bus, respectively, in the mth layer (2 ≦ m ≦) from the second layer onward.
The n) cache memory makes a data read access request from the (m-1) th level cache memory,
When the access target data exists in itself, the access target data is transferred to the cache memory of the (m-1) th layer, and then the access target data existing in itself is invalidated. To do.

According to a second aspect of the present invention, cache memories of n levels (where n ≧ 2) or more are arranged between the data processing device and the main memory, and the cache memory of the first level closest to the data processing device. Is connected to the data processing device and the second-level cache memory by an address bus for data access and a data bus for data transfer, respectively, and the n-th level cache memory closest to the main memory is Another address bus and a data bus are respectively connected to the cache memory of the (n-1) th layer and the main memory, and the cache memory of the mth layer (where 2≤m <n) is the (m-1) th layer. -1) level cache memory and the (m)
In a data processing system in which a cache memory of the +1) th layer is connected to another address bus and a data bus, the cache memory of the kth layer (where 1 ≦ k ≦ n) is the (k−1) th layer. When a data read access request is made from the cache memory of, the presence or absence of the memory space in which data can be registered is detected when the data to be accessed does not exist in all cache memories of the layers after it, and the memory space in which data can be registered If there is any, the access target data transferred from the main memory is registered, and if there is no memory space in which the data can be registered, the registration is prohibited.

According to a third aspect of the present invention, cache memories of n layers (where n ≧ 2) or more are arranged between the data processing device and the main memory, and the cache memory of the first layer closest to the data processing device. Is connected to the data processing device and the second-level cache memory by an address bus for data access and a data bus for data transfer, respectively, and the n-th level cache memory closest to the main memory is Another address bus and a data bus are respectively connected to the cache memory of the (n-1) th layer and the main memory, and the cache memory of the mth layer (where 2≤m <n) is the (m-1) th layer. -1) level cache memory and the (m)
In the data processing system in which the address memory and the data bus are respectively connected to the cache memory of the +1) th layer, the cache memory of the mth layer is the (m-
1) At the time of a data read access request from the cache memory of the hierarchical layer, if the data to be accessed does not exist in all the cache memories of the hierarchical layers subsequent thereto, it is determined whether or not there is a memory space in which data can be registered in the (m-1) th layer When the above-mentioned cache memory detects the memory space in which the data can be registered does not exist in the cache memory of the (m-1) th layer or higher, the access target data is registered in itself.

According to a fourth aspect of the present invention, cache memories of n layers (where n ≧ 2) or more are arranged between the data processing device and the main memory, and the cache memory of the first layer closest to the data processing device. Is connected to the data processing device and the second-level cache memory by an address bus for data access and a data bus for data transfer, respectively, and the n-th level cache memory closest to the main memory is Another address bus and a data bus are respectively connected to the cache memory of the (n-1) th layer and the main memory, and the cache memory of the mth layer (where 2≤m <n) is the (m-1) th layer. -1) level cache memory and the (m)
In the data processing system in which the cache memory of the +1) layer is connected to the other address bus and the data bus respectively, the cache memory of the first layer has the access target data itself when the data read access request is made from the data processing device. If it does not exist, the data read access request is output to the cache memory of the second layer, and if the access target data does not exist in all the cache memories of the second layer and thereafter, the access target data transferred from the main memory is registered. , The cache memory of the m-th layer (2 ≦ m ≦ n) after the second layer is (m-
1) When a data read access request is made from the cache memory of the hierarchical layer, if the access target data does not exist in itself, registration of the access target data transferred from the cache memory of the (m + 1) th hierarchical layer is prohibited, In the cache memory of 1 ≦ k <n), unregisterable data is generated in the cache memory of the (k−1) th layer during the series of processing for registering the access target data from the main memory into the cache memory of the first layer. In that case, it is characterized in that the unregisterable data is registered in itself.

According to a fifth aspect of the present invention, cache memories of n levels (where n ≧ 2) or more are arranged between the data processing device and the main memory, and the cache memory of the first level closest to the data processing device. Is connected to the data processing device and the second-level cache memory by an address bus for data access and a data bus for data transfer, respectively, and the n-th level cache memory closest to the main memory is Another address bus and a data bus are respectively connected to the cache memory of the (n-1) th layer and the main memory, and the cache memory of the mth layer (where 2≤m <n) is the (m-1) th layer. -1) level cache memory and the (m)
In the data processing system in which the cache memory of the +1) th layer is connected to the other address bus and the data bus, respectively, in the mth layer (2 ≦ m ≦) from the second layer onward.
The n) cache memory makes a data read access request from the (m-1) th level cache memory,
When the access target data exists in itself, the access target data is transferred to the cache memory of the first layer, and the cache memory of the (k−1) th layer (where 1 ≦ k <n) is accessed from the main memory. When unregisterable data occurs in the series of processing for registering data in the first layer cache memory, the unregisterable data is transferred to the kth layer cache memory, and the kth layer cache memory The feature is that registration is made only when there is no unregisterable data in itself.

According to a sixth aspect of the present invention, cache memories of n levels (where n ≧ 2) or more are arranged between the data processing device and the main memory, and the cache memory of the first level closest to the data processing device. Is connected to the data processing device and the second-level cache memory by an address bus for data access and a data bus for data transfer, respectively, and the n-th level cache memory closest to the main memory is Another address bus and a data bus are respectively connected to the cache memory of the (n-1) th layer and the main memory, and the cache memory of the mth layer (where 2≤m <n) is the (m-1) th layer. -1) level cache memory and the (m)
In the data processing system in which the cache memory of the +1) th layer is connected to the other address bus and the data bus, respectively, in the mth layer (2 ≦ m ≦) from the second layer onward.
The n) cache memory makes a data read access request from the (m-1) th level cache memory,
When the access target data exists in itself, the access target data is transferred to the cache memory in the first layer, and the cache memory in the (k−1) th layer (where 1 ≦ k <n) stores the access target data in the first layer. In the series of processing for registering in the cache memory of one layer, if the unregisterable data occurs in itself, the unregisterable data is transferred to the cache memory of the kth layer, and the cache memory of the kth layer registers It is characterized in that it is designed to be registered in the portion where the access target data existed only when the impossible data does not exist in itself.

A data processing system having a plurality of levels of cache memory according to the seventh invention has both the functions of the first invention and the fourth invention.

A data processing system having a cache memory of a plurality of layers of the eighth invention has the functions of the fourth invention and the fifth invention together.

A data processing system having a plurality of levels of cache memory according to the ninth invention has both the functions of the fourth invention and the sixth invention.

According to a tenth aspect of the present invention, cache memories of n layers (where n ≧ 2) or more are arranged between the data processing device and the main memory, and all the cache memories are for data access to the data processing device. Is connected to an address bus for data transfer and a data bus for data transfer, and the cache memory of the nth layer closest to the main memory is a data processing system in which another address bus and data bus are connected to the main memory. In the above, in the case of the data read access request from the data processor, the cache memory of the first layer is the second layer if the access target data does not exist in itself.
The data read access request is output to the cache memory of the hierarchy, and if the access target data does not exist in all the cache memories of the second and subsequent layers, the access target data directly transferred from the main memory is registered. When the data read access request from the cache memory of the (m-1) th layer is made, the cache memory of the mth layer (however, 2≤m≤n) stores the data for the request when the access target data does not exist in itself. The cache memory of the k-th layer (where 1 ≦ k <n) is not fetched, and when the series of processing for registering the access target data from the main memory into the cache memory of the first layer,
1) When unregisterable data is generated in the hierarchical cache memory, the unregisterable data is registered in itself.

An eleventh aspect of the invention is that cache memories of n layers (where n ≧ 2) or more are arranged between the data processing device and the main memory, and the cache memory of the first layer closest to the data processing device. Are connected to the data processing device and the main memory by an address bus for data access and a data bus for data transfer, respectively, and the cache memory of the nth hierarchy closest to the main memory is the (n- 1)
Another address bus and data bus are connected to the cache memory of the hierarchy, and the m-th hierarchy (however, 2 ≦ m <n)
Is a data processing system in which the cache memory of the (m-1) th layer and the cache memory of the (m + 1) th layer are connected to other address buses and data buses, respectively. The cache memory outputs a data read access request to the cache memory of the second layer when the data read access request from the data processing device does not exist in the access target data itself, and even in all the cache memories of the second layer and thereafter. If the access target data does not exist, the access target data transferred directly from the main memory is registered, and the cache memory of the m-th layer (2 ≦ m ≦ n) after the second layer is (m−1) th. When the data read access request from the cache memory of the hierarchy is made, the access target data does not exist in itself. In this case, the data corresponding to the request is not fetched, and the k-th hierarchy (where 1 ≦ k <n) cache memory is stored in the cache memory of the first hierarchy when the access target data from the main memory is registered in the first ( k
-1) When unregisterable data is generated in the hierarchical cache memory, the unregisterable data is registered in itself.

According to a twelfth aspect of the present invention, cache memories of n layers (where n ≧ 2) or more are arranged between the data processing device and the main memory, and all the cache memories are for data access to the data processing device. Is connected to a data bus for data transfer, and the cache memory of the first layer, which is closest to the data processing device, has a main memory connected to another address bus and a data bus. In the system, the first level cache memory outputs a data read access request to the second level cache memory when the data read access request from the data processing device is not present in itself, and the second level cache memory outputs the data read access request. If the data to be accessed does not exist in all subsequent cache memories, it is transferred directly from the main memory. Register the access object data, the second
The cache memory of the m-th layer (2 ≦ m ≦ n) after the layer is requested when the data to be accessed does not exist in the data read access request from the cache memory of the (m−1) th layer. The cache memory of the k-th layer (where 1 ≦ k <n) does not fetch the data for (1)-(k <n) during the series of processing for registering the access target data from the main memory into the cache memory of the first layer. When unregisterable data is generated in the hierarchical cache memory, the unregisterable data is registered in itself.

A thirteenth aspect of the invention is that a cache memory of n layers (where n ≧ 2) or more is arranged between the data processing device and the main memory, and the cache memory of the first layer closest to the data processing device. Is connected to the data processing device and the second-level cache memory by an address bus for data access and a data bus for data transfer, respectively, and the n-th level cache memory closest to the main memory is Another address bus and a data bus are respectively connected to the cache memory of the (n-1) th layer and the main memory, and the cache memory of the mth layer (where 2≤m <n) is the (m-1) th layer. -1) A data processing system in which another address bus and a data bus are respectively connected to the cache memory of the (1) th layer and the cache memory of the (m + 1) th layer The cache memory of the layer registers the first data transferred from the main memory when the first data to be accessed does not exist in itself at the time of the data read access request from the data processing device, In the data read access from the first cache memory of the upper layer, the second cache memory stores the data for the second data in the third cache memory of the lower layer when the second data to be accessed does not exist in itself. The read access request and the data read access request for the third data following the second data are output, and the third data transferred from the main memory is written without writing the second data transferred from the main memory. It is characterized in that it is made to register.

A fourteenth aspect of the present invention is provided with a cache memory of n layers or more (where n ≧ 1) between the data processing device and the main memory, and at least one of the cache memories accesses the data read access request. First of target
If the data of the above does not exist in itself, a read access request of the first data is issued to the cache memory or the main memory of the lower layer, and even if there is no data read access request from the cache memory of the upper layer or the data processor. In a data processing system in which second data existing in the vicinity of the first data is read-accessed to a cache memory or a main memory in a lower hierarchy, the cache memory performs a read access to the second data. It is characterized in that a prefetch suppression circuit for determining whether or not it is provided.

The fifteenth aspect of the present invention is to provide m layers or more (where m ≧ 2) between n (where n ≧ 2) data processing devices and the main memory.
In the data processing system having the cache memory of ≧ 2), the cache memory of the first hierarchy of the i-th series closest to the i-th (where 1 ≦ i ≦ n) data processing device is the i-th data. The processor and the second-tier cache memory of the i-th series are connected by an address bus for data access and a data bus for data transfer, and the cache memory of the m-th hierarchy closest to the main memory is
The cache memory of the (m-1) th layer and the main memory are connected to another address bus and a data bus, and the cache memory of the kth layer (where 2 ≦ k <m) of the i-th series is The cache memory of the (k-1) th layer of the i-th series and the l-th layer of the j-th series (where 1≤j≤n) (however, 2≤
Another address bus and a data bus are connected to the cache memory of l <m−1) and the cache memory of the (k + 1) th layer, and the pth layer (2 ≦ p <m, p ≠).
The k) cache memory is a first layer cache in a data processing system in which the (p-1) th layer cache memory and the (p + 1) th layer cache memory are connected to other address buses and data buses. When the data read access request from the data processing device is made, the memory registers the access target data transferred from the lower level cache memory or the main memory when the access target data does not exist in itself, and the kth level cache memory stores When a data read access request is made from the cache memory of the upper layer, if the access target data does not exist in itself, the access target data transferred from the cache memory of the lower layer or the main memory is registered. Data read from the upper layer cache memory Upon access, the access target data is characterized in that if it does not exist in itself are no so as not to register the access target data to be transferred from the cache memory or the main memory of the lower layer.

The sixteenth aspect of the present invention is to provide m layers or more (where m ≧ 2) between n (where n ≧ 2) data processing devices and the main memory.
In the data processing system having the cache memory of ≧ 2), the cache memory of the first hierarchy of the i-th series closest to the i-th (where 1 ≦ i ≦ n) data processing device is the i-th data. The processor and the second-tier cache memory of the i-th series are connected by an address bus for data access and a data bus for data transfer, and the cache memory of the m-th hierarchy closest to the main memory is
The cache memory of the (m-1) th layer and the main memory are connected to another address bus and a data bus, and the cache memory of the kth layer (where 2 ≦ k <m) of the i-th series is The cache memory of the (k-1) th layer of the i-th series and the l-th layer of the j-th series (where 1≤j≤n) (however, 2≤
Another address bus and a data bus are connected to the cache memory of l <m−1) and the cache memory of the (k + 1) th layer, and the pth layer (2 ≦ p <m, p ≠).
The k) cache memory is a first layer cache in a data processing system in which the (p-1) th layer cache memory and the (p + 1) th layer cache memory are connected to other address buses and data buses. Memory
When the data read access request is issued from the data processing device, if the access target data exists in itself, the access target data is output to the data processing device, and the k-th layer cache memory reads the data from the upper layer cache memory. At the time of request, if the access target data exists in itself, the access target data is output to the data processing device or the cache memory of the upper layer,
The cache memory in the p-th layer outputs the access target data to the data processing device or the cache memory in the upper layer when the data to be accessed from the cache memory in the upper layer exists in the data read access from the cache memory in the upper layer. It is characterized in that the access target data existing in is deleted.

In a seventeenth aspect of the invention, a cache memory of n layers (where n ≧ 2) or more is provided between the data processing device and the main memory, and the cache memory of the first layer closest to the data processing device is An address bus for data access and a data bus for data transfer are connected to the processing device and the cache memory of the second hierarchy, and the cache memory of the nth hierarchy closest to the main memory is the (n-
1) The cache memory of the layer and the main memory are connected to other address buses and data buses, and the cache memory of the m-th layer (where 2 ≦ m <n) is the (m−1) th
In a data processing system in which the cache memory of the hierarchical layer and the cache memory of the (m + 1) th hierarchical layer are connected to each other by an address bus and a data bus, the cache memory of the first hierarchical layer causes the data read access request from the data processing device. If the access target data does not exist in itself, the access target data transferred from the lower layer cache memory or the main memory is registered, and the mth layer cache memory stores the data read access from the upper layer cache memory. When the access target data does not exist in itself, the access target data transferred from the lower layer cache memory or the main memory is not registered, but the write data from the upper layer cache memory is registered. ,
When a device other than the data processing device or the cache memory rewrites data in the main storage device, the cache memory of the nth layer (where 2 ≦ m <n) is the (m−1) th layer.
If the data is not registered in the cache memory of the hierarchy, it is searched whether the first data is registered in the cache memory of the nth hierarchy, and if it is not registered, the cache memory of the (m + 1) th hierarchy in the next stage. To search the first data, and when the first data is registered in the cache memory of the mth layer, the cache memory of the (m + 1) th layer of the next stage should not be searched for the first data. It is characterized by being.

The eighteenth invention comprises a cache memory of n layers (where n ≧ 2) or more between the data processing device and the main memory, and the cache memory of the first layer closest to the data processing device is the data An address bus for data access and a data bus for data transfer are connected to the processing device and the cache memory of the second hierarchy, and the cache memory of the nth hierarchy closest to the main memory is the (n-
1) The cache memory of the layer and the main memory are connected to other address buses and data buses, and the cache memory of the m-th layer (where 2 ≦ m <n) is the (m−1) th
The cache memory of the hierarchical layer and the cache memory of the (m + 1) th hierarchical layer are connected to each other by another address bus and a data bus. The cache memory of the first hierarchical layer is accessed by the data read access request from the data processor. If it does not exist in itself, the data transferred from the cache memory in the lower layer or the main memory is registered, and the cache memory in the mth layer stores the data to be accessed in itself in the data read access from the cache memory in the upper layer. If it does not exist, the data transferred from the lower layer cache memory or main memory is not registered, but the write data from the upper layer cache memory is registered, except for the data processing device or the cache memory. Is the main memory data When rewriting, the n-tier (where, 2 ≦ m <n) cache memory includes a first (m-
1) If the data is not registered in the cache memory of the layer, it is searched whether the data is registered in the cache memory of the nth layer, and if not registered, the data is stored in the cache memory of the (m + 1) th layer of the next stage. And the data is registered in the cache memory of the m-th layer, the cache memory of the (m + 1) -th layer of the next stage is not searched for the data.

[0070]

According to the data processing system of the present invention, which is provided with a plurality of layers of cache memory, the data in the main memory corresponding to the data read access request from the data processing device is not registered in all the cache memories, but as much as possible. Alternatively, it is completely registered in only one cache memory.
Therefore, the same data in the main memory is less likely to be registered in different cache memories in duplicate, and more data can be registered in the entire cache memory.

[0071]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing the embodiments thereof. FIG. 1 is a block diagram showing a configuration example of a data processing system having a two-level cache memory as a first embodiment of the first invention of the data processing system of the present invention.

In FIG. 1, reference numeral 100 is a data processor, 10 is a primary cache memory connected to the data processor 100, 11 is a secondary cache memory connected to the primary cache memory 10, 103 Indicate main memories connected to the secondary cache memory 11.

In the data processing system of the present invention, as in the above-described conventional example, the main memory 103 is composed of a memory having a capacity of several megabytes to several hundred megabytes and a relatively low access speed. The secondary cache memory 11 is composed of a memory of ten and several kilobytes to several hundreds of kilobytes, and the primary cache memory 10 is composed of a memory of several kilobytes.

Regarding the data access speed, the main memory 10
While 3 is generally capable of accessing data in hundreds of tens of nanoseconds, the secondary cache memory 11 is in the order of tens of nanoseconds to tens of ns.
Data can be accessed with ec, primary cache memory
Data of 10 can be accessed in a few nsec to a dozen nsec.
That is, in the order of the main memory 103, the secondary cache memory 11, and the primary cache memory 10, the capacity becomes smaller, but the data can be accessed at high speed. Therefore, by registering a copy of a part of the data in the main memory 103 in the cache memories 10 and 11 in advance, the data can be accessed at high speed without accessing the main memory 103. Furthermore, the data processing device
When 100 accesses the primary cache memory 10,
It can be accessed at a higher speed than the processing speed of the data processing device 100.

Generally, in such a data processing system, the primary cache memory 10 can exchange data only between the data processing device 100 and the secondary cache memory 11, and the secondary cache memory 11 Can access data only between the primary cache memory 10 and the main memory 103. Direct data access cannot be performed between the data processing device 100 and the main memory 103.

Next, the operation of the data processing system of the present invention shown in FIG. 1 will be described.

In the data access operation of the data processing system of the present invention, the operation different from that of the conventional data processing system shown in FIG.
Only when there is a cache read hit in.

When a data read access request is issued in the data processing device 100, the data processing device 100 first performs a data read access (104) to the primary cache memory 10. If a cache miss occurs in the primary cache memory 10 (a state in which the requested data is not registered in the cache memory), a data read access from the primary cache memory 10 to the secondary cache memory 11 (105 ) Is performed. Further, when a cache miss also occurs in the secondary cache memory 11, a data read access (106) is made from the secondary cache memory 11 to the main memory 103.

From the secondary cache memory 11 to the main memory 10
Main memory 103 by data read access request for 3
The data read from is transferred / registered (112) to the secondary cache memory 11, further transferred / registered (111) to the primary cache memory 10, and then transferred to the data processing device 100 (1
10) Will be done. However, when a cache hit occurs in the data read access (104) to the primary cache memory 10, the data (hereinafter referred to as hit data) is transferred (110) to the data processing device 100 as it is. In this case, the data read access (105, 106) to the secondary cache memory 11 and the main memory 103 is not performed.

When a data write access request is issued in the data processing device 100, if both the primary and secondary cache memories 10 and 11 are write-through type cache memories, the primary cache memory 10 must be accessed. Data write access (104, 105, 106) is performed for both the secondary cache memory 11 and the main memory 103.

At this time, the data written in the primary cache memory 10, the secondary cache memory 11 and the main memory 103 is the reference numeral 107 → 108 → 109 from the data processor 100.
Is transferred by the route. Then, when a cache write hit occurs in the primary and secondary cache memories 10 and 11, and further in the main memory 103, data update is executed. In particular,
The hit data in the cache memory is the data processing device 10
It is overwritten by the data transferred from 0. By such processing, data consistency is maintained in the write-through cache memory.

When a cache read hit occurs in the secondary cache memory 11 in response to a data read access request from the data processing device 100, the hit data (A) in the secondary cache memory 11 is the primary cache memory 10.
Invalidated after being transferred (14) to. That is, each time a cache hit occurs in the secondary cache memory 11, the hit data is transferred to the primary cache memory 10 and registered, and is invalidated in the secondary cache memory 11. Therefore, in the data processing system of the present invention,
Secondary cache memory 11
It is possible to register more data than the capacity. This improves the hit rate of the cache memory as a whole, and the improvement of the hit rate leads to speeding up of data access. That is, the data processing device 100 can access more data at high speed as compared with the conventional system.

FIGS. 2 and 3 are block diagrams showing examples of circuit configurations when the primary cache memory 10 and the secondary cache memory 11 of the data processing system of the present invention shown in FIG. 1 are connected. In addition, in FIG. 2, a data processing device
The primary cache memory 10 connected between 100 and the secondary cache memory 11 is the main memory 103 in FIG.
A secondary cache memory 11 connected between the primary cache memory 10 and the primary cache memory 10 is shown.

Both the primary cache memory 10 and the secondary cache memory 11 of the data processing system of the present invention have basically the same structure as the conventional general cache memory shown in FIG. 25 described above. However, the difference is that the cache hit / miss signal generator 36 of the secondary cache memory 11 outputs a valid bit invalidate signal 41.

Both cache memories 10 and 11 shown in FIGS. 2 and 3 are of the 4-way set associative system. However, the capacity of the secondary cache memory 11 is larger than that of the primary cache memory 10.

In FIGS. 2 and 3, the primary cache memory 10 and the secondary cache memory 11 are cache hits /
Only the configuration of the miss signal generator 36 is different. Reference numeral 33 is a part of the data in the main memory 103 (in addition to the primary cache memory 10, a part of the data in the secondary cache memory 11)
Is stored in the data section 33, 31 is a tag section that stores a part of the address for the data stored in the data section 33, and 32 is data that is valid or invalid for each entry. Reference numeral 30 indicates a valid bit indicating whether there is any, and 30 indicates a decoder that selects one of the entries. Input / output of data to / from the data unit 33 is performed in entry units.

Further, reference numeral 36 is a cache hit / miss signal generating section for generating a cache hit / miss signal after comparing the input address and the tag information at the time of cache access, and 37 is the data from the data section 33 at the time of cache hit. Reference numeral 35 denotes an output buffer to be read out, and 35 denotes a line buffer which takes in data from the data bus 63 or 65 at the time of a cache miss. However, the cache hit / miss signal generation unit 36 of the secondary cache memory 11 outputs the invalidate signal 41 when a read hit occurs.

Further, since the primary cache memory 10 and the secondary cache memory 11 shown in FIGS. 2 and 3 are all of the 4-way set associative system, the tag section 31, the data section 33, and the valid bit section are provided. 32, decoder 3
Four sets of 0 and cache hit / miss signal generators 36 are provided for ways 0 to 3, respectively. Generally, when a cache miss occurs, the LRU (Least Recently Used) algorithm control circuit or the like selects which of the ways 0 to 3 the data fetched in the line buffer 35 is registered. Circuit is not shown in FIGS.

Reference numeral 60 is a primary cache memory.
An address bus (1
Input address bus of the next cache memory 10), 67 is 1
A data bus connecting the output buffer 37 of the secondary cache memory 10 and the data processing device 100, and an address bus 62 connecting the secondary cache memory 11 and the main memory 103 (output address bus of the secondary cache memory 11). , 63 is a data bus connecting the line buffer 35 of the secondary cache memory 11 and the main memory 103, and 61 is the primary cache memory 10.
An address bus (an output address bus of the primary cache memory 10 and an input address bus of the secondary cache memory 11) connecting the secondary cache memory 11 and the secondary cache memory 11;
Indicates a data bus connecting the line buffer 35 of the primary cache memory 10 and the output buffer 37 of the secondary cache memory 11, respectively.

The data bus 67 and the data bus 65 are 1
The bypass path 66 is connected in the next cache memory 10 and the data bus 63 and the data bus 65 are connected in the bypass path 64 in the secondary cache memory 11.

Next, the basic operation of both cache memories 10 and 11 shown in FIGS. 2 and 3 will be described. First, the data processing device 100 or the primary cache memory 10
When a data read access request is generated at, the address for reading data is set to the input address bus 60 or
Input from 61. This address is input to the cache hit / miss signal generation unit 36, the decoder 30, and the latch 34 for tag registration at the time of cache miss.

The decoder 30 decodes several bits of the address and outputs an entry selection signal, and the tag unit 31,
One of the valid bit 32 and data 33 entries is selected. Then, the cache hit / miss signal generation unit 36 reads the tag 90a and the valid bit 90b of the selected entry from the tag unit 31 and the valid bit unit 32.

The tag 90a is compared with the address. If the results match and the valid bit 90b is valid, the cache hit / miss signal generator 36 of the primary cache memory 10 outputs the cache read hit signal 39 to 2 The cache hit / miss signal generator 36 of the next cache memory 11 receives the cache read hit signal 39 and the invalidate signal 41.
Is output. On the contrary, if the comparison result of the tag 90a and the address does not match or the valid bit 90b is invalid, the cache hit / miss signal generation unit 36 outputs the cache read miss signal 38.

When the cache read / hit signal generating unit 36 outputs the cache read hit signal 39, the data of the entry 90c selected by the decoder 30 is output from the data unit 33 and taken into the output buffer 37.
The data taken into the output buffer 37 is output to the outside of the respective cache memory 10 or 11 as data (hit data) for the access request.

The cache hit / miss signal generation section
When the cache read miss signal 38 is output from 36, the address is output from the output address bus 61 or 62 to the secondary cache memory 11 or the main memory 103 to perform read access to them. The data transferred in response to this data read access request is
Data bus 63 to line buffer 35 of secondary cache memory 11 or data bus 65 to primary cache memory 10
It is taken into the line buffer 35 of. Then, as soon as the data transfer to the line buffer 35 is completed, the data is registered in the selected entry 90a, 90c of the selected way together with the tag. At this time, the valid bit 90b corresponding to the same entry is also set.

At the time of registering this data, the decision of which way to register the data is controlled by the LRU algorithm or the like as described above. Further, the data input from the data bus 63 or 65 is taken into the line buffer 35 of the secondary cache memory 11 or the line buffer 35 of the primary cache memory 10 and at the same time to the data bus 65 via the bypass path 64 or the bypass. It is also directly output to the data bus 67 via the path 66. With such a cache memory, the data processing system of the present invention can transfer data to the request source at higher speed in the case of a cache miss.

When a data write access request is issued in the data processing device 100, an address for writing data is input from the input address bus 60 or 61. The address is input to the cache hit / miss signal generation unit 36, the decoder 30, and the tag registration latch 34 at the time of cache miss, as well as at the time of data read, and at the same time, the decoder 30 causes the tag unit 31 and the valid bit unit. 32, one of the entries in the data section 33 is selected. Then, the values of the selected tag unit 31 and valid bit unit 32 are read by the cache hit / miss signal generation unit 36 and used for the cache hit / miss determination.

When a cache write hit occurs, it is necessary to update the hit data in the cache memory. That is, the data transferred from the data bus 67 or 65 is output to the data bus 65 via the bypass path 66 or to the data bus 63 via the bypass path 64 and taken into the line buffer 35. Then, the data held in the line buffer 35 by the cache write hit signal 40 is registered together with the tag. In the case of a cache write miss, there is no need to update the data in the cache memory, so no processing is executed in the cache memory.

Next, the primary and secondary signals shown in FIGS.
The operation of the configuration when the next cache memories 10 and 11 are connected will be described. First, when a data read access request is generated in the data processing device 100, an address for the data is input to the primary cache memory 10 from the input address bus 60.

When a cache read miss occurs in the primary cache memory 10, the cache hit / miss signal generator 36 of the primary cache memory 10 outputs a cache read miss signal 38, thereby causing the output address bus 61
Then, an address is output from the memory and data read access is performed to the secondary cache memory 11. Similarly, in the case of the cache read miss in the secondary cache memory 11, the cache hit / miss signal generation unit 36 of the secondary cache memory 11 outputs the cache read miss signal 38 to output the address from the output address bus 62. Data read access (10
6) is performed.

The data read from the main memory 103 in response to this data read access is stored in the data bus 63.
From the secondary cache memory 11 to the line buffer 35, and is registered in the selected entry of the secondary cache memory 11 at the same time as the bypass path 64.
Output to the data bus 65 from the primary cache memory 10
Transferred to.

In the primary cache memory 10, the data bus
The data transferred from 65 is registered in the selected entry via the line buffer 35, and at the same time, the data is output from the bypass path 66 to the data bus 67 to be output to the data processing device 100.
Transfer to. In this way, the primary cache memories 10 and 2
When a cache read miss occurs in any of the secondary cache memories 11, the data read from the main memory 103 is transferred to the data processing device 100 after being registered in both the primary and secondary cache memories 10 and 11. It

Next, a case where a cache read miss occurs in the access to the primary cache memory 10 but a cache read hit occurs in the access to the secondary cache memory 11 will be described.

When a cache read hit occurs in the secondary cache memory 11, the hit data (A), that is, the data of the selected entry 90c is fetched into the output buffer 37 by the cache read hit signal 39. Then, the hit data (A) is transferred to the primary cache memory 10 through the data bus 65.

At the same time, the invalidate signal 41 from the cache hit / miss signal generator 36 of the secondary cache memory 11 is the hit data in the secondary cache memory 11.
(A) is output to invalidate the line 90c of the registered data part 33, and the valid bit 90b of the corresponding valid bit part 32 is negated. As a result, the hit data (A) exists only in the primary cache memory 10, and the hit data (A) in the data portion 33 of the secondary cache memory 11 exists in the portion 90c of the data portion 33 where the hit data (A) existed. It becomes possible to register new data from the main memory 103.

That is, when a cache read hit occurs in the secondary cache memory 11, the hit data (A) is registered only in the primary cache memory 10, and new data may be registered in the secondary cache memory 11. It will be possible. Therefore, in the data processing system of the present invention, more data can be registered in the entire cache memory as compared with the conventional data processing system.

As described above, the cache read hit in the secondary cache memory 11 causes the hit data (A).
Is transferred to the primary cache memory 10, the primary cache memory 10 registers the data in the selected entry via the line buffer 35, and at the same time, outputs the data from the bypass path 66 to the data bus 67 and outputs the data processing device. Transfer to 100.

Next, a case where a cache read hit occurs when accessing the primary cache memory 10 will be described. When there is a cache read hit in the primary cache memory 10, the data of the selected entry is taken into the output buffer 37 by the cache read hit signal 39 and transferred to the data processing device 100. In this case, data read access from the primary cache memory 10 to the secondary cache memory 11 is not performed.

Next, a case where a data write access request is generated in the data processing device 100 will be described.
When both the primary and secondary cache memories 10 and 11 are of the write-through type, data write access is executed to both the primary and secondary cache memories 10 and 11 regardless of cache write hit / miss.

Therefore, the address for data write is input to both the primary and secondary cache memories 10 and 11 via the route of the address bus 60 → 61 → 62. Further, the data for updating both cache memories 10 and 11 is transferred through the data bus and the bypass path. That is, the reference numerals 67, 66, 65, 65, 64, and 63 are transferred, and temporarily stored in the line buffers 35 of the primary and secondary cache memories 10 and 11, respectively.

The primary and secondary cache memories 10, 11
If a cache write hit occurs at, the data held in the respective line buffers 35 will be sent together with the tag by the cache write hit signal 40 to both cache memories 10, 11.
Be registered with. Further, the data write access is also executed to the main memory 103 by the address and the data output from the secondary cache memory 11.

The block diagram of FIG. 4 shows another embodiment for realizing the first invention of the data processing system of the present invention shown in FIG. In the data processing system of the present invention shown in FIG. 1, means for invalidating the data line of the data section 33 in which the hit data is registered when the cache read hit occurs in the secondary cache memory, that is, invalidate A cache hit / miss signal generator 36 for generating the signal 41 is built in the secondary cache memory itself.

On the other hand, in the embodiment shown in the block diagram of FIG. 4, in order to realize the same function as that of the data processing system shown in FIG. 1, an external circuit is provided in the secondary cache memory 102 similar to the conventional one. I have it. Specifically, Figure 24
In addition to the conventional data processing system shown in FIG. 4, in the second embodiment of the first invention of the present invention shown in FIG. 4, the secondary cache memory invalidate circuit 2
Is equipped with. Other configurations are similar to those of the conventional data processing system shown in FIG.

The secondary cache memory invalidate circuit 2 includes a primary cache memory 101 and a secondary cache memory.
The data bus 61 is connected to the data bus 101 by the data bus 3. The secondary cache memory invalidate circuit 2 receives the cache read / hit signal 39 from the secondary cache memory 102 as the hit signal 5 when the cache hit / miss signal generator 36 outputs the cache read / hit signal 39, and receives the invalid signal. 4 is output to the secondary cache memory 102.

The operation of the second embodiment of the first invention of the data processing system of the present invention shown in the block diagram of FIG. 4 will be described below.

The secondary cache memory invalidate circuit 2 shown in FIG. 4 operates only when the secondary cache memory 102 is hit. In other cases, the operation is similar to that of the conventional data processing system. When a data read access request is generated in the data processing device 100, a data read access (104) is first performed to the primary cache memory 101. When a cache miss occurs in the primary cache memory 101,
A data read access (105) is made to the secondary cache memory 102.

When the data read access (105) to the secondary cache memory 102 results in a cache read hit, the secondary cache memory invalidate circuit 2
Receives the hit signal 5 output from the cache hit / miss signal generation unit 36, and at the same time outputs the address output from the primary cache memory 101 to the secondary cache memory 102 via the data bus 61 to the address bus. Take in via 3. Then, after the secondary cache memory 102 transfers (111) the hit data (A) to the primary cache memory, the secondary cache memory invalidate circuit 2 sends the invalidate signal 4 and the address 3 to the secondary cache memory 102. Output.

By providing this invalidate signal 4 and address 3, the secondary cache memory 102
Invalidates the line registered with the hit data in its own data section 33. With such operations, the second embodiment of the first invention of the data processing system of the present invention shown in the block diagram of FIG. 4 performs the same operation as the embodiment shown in FIG. You can

In the first embodiment shown in FIGS. 1 and 2 and 3, the cache hit / miss signal generator 36 in the secondary cache memory 11 needs to have a configuration different from the conventional one. Although it is necessary to create a new cache memory as the secondary cache memory 11, the second invention of the first invention of the data processing system of the present invention shown in FIG.
In this embodiment, as the secondary cache memory itself, a cache memory having the same structure as the conventional secondary cache memory 102 can be used.

The block diagram of FIG. 5 shows a configuration example of a data processing system having a two-level cache memory as an embodiment of the second invention of the data processing system of the present invention. In FIG. 5, reference numeral 100 indicates a data processing device,
10 is a primary cache memory connected to the data processing device 100, 11 is a secondary cache memory connected to the primary cache memory 10, and 103 is a main memory connected to the secondary cache memory 11. There is.

The operation of the second embodiment of the data processing system of the present invention shown in the block diagram of FIG. 5 will be described below. When a data read access request occurs in the data processing device 100, first, a data read access (104) is performed to the primary cache memory 10. When a cache miss occurs in the primary cache memory 10, data read access from the primary cache memory 10 to the secondary cache memory 11 is performed.
(105) is performed. When a cache miss also occurs in the secondary cache memory 11, a data read access (1
06) is performed.

The data read from the main memory 103 by this data read access request is stored in the secondary cache memory.
Transferred to 11 and registered (112), and further primary cache memory
The data is transferred and registered (111) in 10 and then transferred (110) to the data processing device 100. Here, the operation of the second invention of the data processing system of the present invention shown in FIG. 5 is different from that of the conventional data processing system in that the primary cache memory 10
This is an operation when a memory space for registering new data does not exist in other words, in other words, when the access lines of all the ways in the primary cache memory 10 are filled.

That is, if the requested data is not registered in the entire cache memory, in other words, neither the primary cache memory 10 nor the secondary cache memory 11 and data is read from the main memory 103, 1 If there is no memory space in which data can be registered in the next cache memory 10, the data will not be registered.

When a cache hit is caused by the data read access (105) to the secondary cache memory 11, the hit data is the primary cache memory 10.
The data is transferred / registered (111) to and then transferred (110) to the data processing device 100. At this time, no data read access to the main memory 103 is performed. In addition, the primary cache memory 10
When there is a cache hit by the data read access (104) to the, the hit data is transferred (110) to the data processing device 100 as it is. In this case, data read access to the secondary cache memory 11 and the main memory 103 is not performed.

When a data write access request is issued in the data processing device 100, if both the primary and secondary cache memories 10 and 11 are write-through type cache memories, the primary cache memory 10 must be written. Data write access (104, 105, 106) is performed for both the secondary cache memory 11 and the main memory 103.

The data written at this time is transferred from the data processing device 100 through the route of reference numeral 107 → 108 → 109. Then, the primary and secondary cache memories 10, 11,
Further, when a cache write hit occurs in the main memory 103, data update, that is, the hit data in the cache memory is overwritten by the data transferred from the data processor 100 is executed. By such processing, data consistency is maintained in the write-through cache memory.

FIG. 6 and FIG. 7 show examples of circuit configurations when the primary cache memory 10 and the secondary cache memory 11 of the second invention of the data processing system of the present invention shown in FIG. 5 are connected. A block diagram is shown. The primary cache memory 10 connected between the data processing device 100 and the secondary cache memory 11 in FIG. 6 is connected between the main memory 103 and the primary cache memory 10 in FIG. The respective secondary cache memories 11 are shown.

The primary cache memory 10 and the secondary cache memory 11 shown in FIGS. 6 and 7 differ from the conventional configuration in that the data section 33 of the primary cache memory 10 is provided with the line full bit 42. That is the point. This line full bit 42 is used for the data section 33 of the primary cache memory 10.
It indicates whether or not each line is already filled with the registered data. If all the line full bits 42 are enabled, in other words, if one way of the data section 33 is completely filled with valid data registered, the enable line full signal 43 is the cache hit / miss signal. It is output to the generation unit 36.

In FIGS. 6 and 7, when a cache miss occurs in the secondary cache memory 11, the cache miss signal 38 output from the cache hit / miss signal generation unit 36 indicates that the cache hit / miss of the primary cache memory 10 It is input to the miss signal generation unit 36.

Next, the operation of the second embodiment of the data processing system of the present invention shown in FIGS. 5, 6 and 7 and particularly the operation of the cache memory will be described.

For the data read access (104) input from the data processing device 100, the primary cache memory 10
If the data is not registered therein, the primary cache memory 10 outputs a data read access (105) to the secondary cache memory 11. Secondary cache memory
If the data is not registered in 11 either, the secondary cache memory 11 outputs a data read access (106) to the main memory 103. Secondary cache memory 11 at the same time
The cache read miss signal 38 generated in step 1 is input to the cache hit / miss signal generator 36 of the primary cache memory 10.

At this time, the line full bit 42 of the primary cache memory 10 is input as a line full signal 43 to the cache hit / miss signal generator 36 of the primary cache memory 10. If the line hit signal 43 and the cache miss signal 38 output from the secondary cache memory 11 are enabled, the cache hit / miss signal generator 36 of the primary cache memory 10 transfers them from the main memory 103. Data is not registered. That is, in the process of registering data from the main memory 103 to the entire cache memory,
If the primary cache memory 10 does not have a memory capacity capable of registering data, data is not registered in the primary cache memory 10 but only in the secondary cache memory 11.

Therefore, at this point, the primary cache memory
Data not registered in 10 is the secondary cache memory 11
Therefore, it is possible to register more data than the capacity of the secondary cache memory 11 in the cache memory as a whole.

The operation of the data processing system of the present invention shown in FIGS. 5, 6 and 7 other than the above-described operation of the second invention is the same as that of the conventional data processing system.

A block diagram of FIG. 8 shows a configuration example of a data processing system having a two-level cache memory as an embodiment of the third invention of the data processing system of the present invention. In FIG. 8, reference numeral 100 indicates a data processing device,
Reference numeral 10 is a primary cache memory connected to the data processing device 100, 11 is a secondary cache memory connected to the primary cache memory 10, and 103 is a main memory connected to the secondary cache memory 11. .

The operation of the third embodiment of the data processing system of the present invention shown in the block diagram of FIG. 8 will be described below. When a data read access request occurs in the data processing device 100, first, a data read access (104) is made to the primary cache memory. When a cache miss occurs in the primary cache memory, a data read access from the primary cache memory 10 to the secondary cache memory (105)
Is done. Further, if a cache miss also occurs in the secondary cache memory, the secondary cache memory 11
The data read access (106) is performed from the main memory 103.

The third aspect of the data processing system of the present invention shown in FIG. 8 operates differently from the conventional data processing system when data is registered from the main memory 103 to the entire cache memory. is there. That is, when the primary cache memory 10 has a memory space for registering the data transferred from the main memory 103, the data is not transferred or registered in the secondary cache memory 11 and is not registered in the primary cache memory 11. Only transferred to memory 10 and registered (9). On the other hand, when there is no memory space for registering data in the primary cache memory 10, the data is 1
The data is not transferred / registered in the next cache memory 10 but transferred / registered (112) only in the secondary cache memory 11.

If a cache hit occurs during the data read access (105) to the secondary cache memory 11, the hit data is the primary cache memory.
The data is transferred and registered (111) in 10 and then transferred (110) to the data processing device 100. At this time, no data read access to the main memory 103 is performed. Also, the primary cache memory
If a cache hit occurs during the data read access (104) to 10, the hit data is transferred (110) to the data processing device 100 as it is. At this time, no data read access is made to either the secondary cache memory 11 or the main memory 103.

When a data write access request is issued in the data processing device 100, if both the primary and secondary cache memories 10 and 11 are write-through type cache memories, the primary cache memory 10 must be accessed. Data write access (104, 105, 106) is performed for both the secondary cache memory 11 and the main memory 103.

The data written at this time is transferred from the data processing device 100 through the route of reference numeral 107 → 108 → 109. Then, the primary and secondary cache memories 10, 11,
Further, when a cache write hit occurs in the main memory 103, a data update, that is, a process of overwriting the hit data in the cache memory with the data transferred from the data processing device 100 is executed. By such processing, data consistency is maintained in the write-through cache memory.

FIGS. 9 and 10 show an example of the circuit configuration when the primary cache memory 10 and the secondary cache memory 11 of the third invention of the data processing system of the present invention shown in FIG. 8 are connected. A block diagram is shown. The primary cache memory 10 connected between the data processing device 100 and the secondary cache memory 11 in FIG. 9 is connected between the main memory 103 and the primary cache memory 10 in FIG. The respective secondary cache memories 11 are shown.

The primary cache memory 10 and the secondary cache memory 11 shown in FIGS. 9 and 10 are different from the conventional configuration in that the data section 33 of the primary cache memory 10 is provided with the line full bit 42. That is the point. This line full bit 42 is used for the data section 33 of the primary cache memory 10.
It indicates whether or not each line is already filled with the registered data. The difference from the above-described second invention is that if all the line full bits 42 are enabled, in other words, if one way of the data section 33 is completely filled with registered valid data, the enable is enabled. Is output to the cache hit / miss signal generation unit 36 of both the primary cache memory 10 and the secondary cache memory 11.

Next, the operation of the third embodiment of the data processing system of the present invention shown in FIGS. 8 and 9 and 10, particularly the operation of the cache memory, will be described.

For the data read access (104) input from the data processing device 100, the primary cache memory 10
If the data is not registered therein, the primary cache memory 10 outputs a data read access (105) to the secondary cache memory 11. Secondary cache memory
If the data is not registered in 11 either, the secondary cache memory 11 outputs a data read access (106) to the main memory 103. At this time, the primary cache memory
If the line full bit 42 of 10 is not set and the line full signal 43 is disabled, in the primary cache memory 10, the cache hit / miss signal generation unit 36 detects the line full signal 43 and registers the data. Run. On the other hand, in the secondary cache memory 11, the cache hit / miss signal generator 36 detects that the line-full signal 43 is disabled and does not execute data registration.

On the other hand, when the line full bit 42 of the primary cache memory 10 is set and the line full signal 43 is enabled, data registration is not executed in the primary cache memory 10, but in the secondary cache memory 11. Data registration is executed. That is, data registration from the main memory 103 is executed only for the primary cache memory 10 when the primary cache memory 10 has a memory capacity for data registration, and the memory capacity for data registration in the primary cache memory 10 is executed. Second-level cache memory if no
Only executed for 11.

Therefore, at this point, the primary cache memory
Data not registered in 10 is the secondary cache memory 11
Therefore, it is possible to register more data than the capacity of the secondary cache memory 11 in the cache memory as a whole.

The operation of the data processing system of the present invention shown in FIGS. 8, 9 and 10 is the same as that of the conventional data processing system except the above-mentioned operation of the third invention.

A block diagram of FIG. 11 shows an example of the configuration of a data processing system having a two-level cache memory as an embodiment of the fourth invention of the data processing system of the present invention. In FIG. 11, reference numeral 100 indicates a data processing device,
Reference numeral 10 is a primary cache memory connected to the data processing device 100, 11 is a secondary cache memory connected to the primary cache memory 10, and 103 is a main memory connected to the secondary cache memory 11. .

The operation of the fourth embodiment of the data processing system of the present invention shown in the block diagram of FIG. 11 will be described below.

When a data read access request is issued in the data processing device 100, first, a data read access (104) is made to the primary cache memory 10.
When a cache miss occurs in the primary cache memory 10, a data read access from the primary cache memory 10 to the secondary cache memory 11 (105)
Is done. Further, if a cache miss also occurs in the secondary cache memory 11, the secondary cache memory
Data read access from main memory 103 from 11 (106)
Is done.

Then, the data read access (106)
However, the data read from the main memory 103 is not registered in the secondary cache memory 11 and the primary cache memory
Data processing device 100 after being transferred and registered (9) only to 10
Transferred to (110).

In this series of processing, if a cache hit occurs during the data read access (105) to the secondary cache memory 11, the hit data is transferred from the secondary cache memory 11 to the primary cache memory 10.
Registered (111) and transferred to the data processor 100 (110)
To be done. At this time, the data read access to the main memory 103 is not performed.

On the other hand, if a cache hit occurs in the data read access (104) to the primary cache memory 10, the hit data is transferred (110) from the primary cache memory 10 to the data processing device 100 as it is. At this time, the data read access to the secondary cache memory 11 and the main memory 103 is not performed.

From the main memory 103 to the primary cache memory
When data that cannot be registered in the primary cache memory 10 occurs when data is transferred directly to 10 and registered (9),
The data is transferred / registered (8) from the primary cache memory 10 to the secondary cache memory 11.

When a data write access request is issued in the data processor 100, if both the primary and secondary cache memories 10 and 11 are write-through type cache memories, the primary cache memory 10 must be Data write access (104, 105, 106) is performed for both the secondary cache memory 11 and the main memory 103.

The data written at this time is 1 from the data processing device 100 through the route of reference numeral 107 → 108 → 109.
The data is transferred to the secondary and secondary cache memories 10 and 11, and further to the main memory 103. By such processing, data consistency is maintained in the write-through cache memory.

In the fourth invention of the data processing system of the present invention shown in FIG. 11, as described above,
Of the data in the main memory 103, a part 113 of the data copy corresponding to the capacity of the primary cache memory 10 is first registered in the primary cache memory 10. Then, after the data is registered in all the capacity of the primary cache memory 10, the data copy 112 of the capacity of the secondary cache memory 11 of the data in the main memory 103
Is registered in the secondary cache memory 11.

By adopting such a data access procedure, the primary and secondary caches 10 and 11 as a whole are
It is possible to reduce the number of redundantly registered data as much as possible.

12 and 13 are blocks of a circuit configuration example when the primary cache memory 10 and the secondary cache memory 11 of the fourth invention of the data processing system of the present invention shown in FIG. 11 are connected. The figure is shown. The primary cache memory 10 connected between the data processing device 100 and the secondary cache memory 11 in FIG. 12 is connected between the main memory 103 and the primary cache memory 10 in FIG. The respective secondary cache memories 11 are shown.

The primary cache memory 10 and the secondary cache memory 11 shown in FIGS. 12 and 13 differ from the conventional configuration in that both the primary cache memory 10 and the secondary cache memory 11 have an output buffer control circuit. 45 is provided. The output buffer control circuit 45 controls whether or not the data taken in the output buffer 37 is output to the data buses 65 and 67.

Further, in the primary cache memory 10 and the secondary cache memory 11 shown in FIGS. 12 and 13, the cache hit / miss signal generation unit, which was conventionally indicated by reference numeral 36, is indicated by reference numeral 44. Has been done. The cache hit / miss signal generation unit 44 has a function of outputting certain data on the line to the output buffer if the line of the data unit 33 is full when a cache miss occurs. Further, in the secondary cache memory 11 shown in FIGS. 12 and 13, the cache hit / miss signal generator
The cache miss signal 47 output from 44 is also input to the output buffer control circuit 45 of the primary cache memory 10.

Next, the operation of the fourth embodiment of the data processing system of the present invention shown in FIGS. 11 and 12 and 13, particularly the operation of the cache memory, will be described.

In the data processing system of the present invention, 1 is set for data read access from the data processing device 100.
When the data is not registered in the secondary and secondary cache memories 10 and 11, only the primary cache memory 10 registers the data from the main memory 103. That is, when a cache miss occurs in the primary cache memory 10, the data of the line buffer 35 or the like is registered in the cache memory by the cache miss signal 47 output from the cache hit / miss signal generator 44. At this time, in the secondary cache memory 11, no signal for cache registration is output from the cache hit / miss signal generation unit 44, and data is not registered in the cache memory.

Also, the primary cache memory 10 of this embodiment is
Then, if data that cannot be registered occurs when registering the data transferred directly from the main memory 103 through the line buffer 35, that is, if data is registered on the same line in all four ways, register the data. The data that cannot be transferred is transferred to the output buffer 37 and temporarily held. The data held in the output buffer 37 is output to the data bus 67, and further the bypass path 66, the data bus 65, and the bypass path.
The data is transferred to the line buffer 35 of the secondary cache memory 11 via the data bus 64 and the data bus 63.

Output buffer 37 of primary cache memory 10
The output buffer control circuit 45 controls the output of the data from the output to the data bus 67. Output buffer control circuit
The reference numeral 45 outputs the data write access signals 48, 49 at the timing, that is, at the timing at which there is no conflict with the process in which the data transferred from the main memory 103 is registered in the primary cache memory 10. As a result, the data held in the output buffer 45 is output to the data bus 67, and at the same time, the secondary cache memory 11 is routed through the above-mentioned path.
Is transferred to the line buffer 35 of the secondary cache memory
Registered in 11.

When data read access from the data processing device 100 is performed, if the data to be accessed is not registered in the primary cache memory 10 but registered in the secondary cache memory 11, the secondary cache memory The cache hit signal 46 is output from the cache hit / miss signal generation unit 44 of 11 and the secondary cache memory
Data is output from the data unit 33 of 11 to the output buffer 37 and is temporarily held. And this secondary cache memory
The data held in the output buffer 37 of 11 is output to the data bus 65 by the signal 49 output from the output buffer control circuit 45 of the secondary cache memory 11 and held in the line buffer 35 of the primary cache memory 10. After being registered in the primary cache memory 10, the bypass route
The data is transferred from 66 to the data processing device 100 through the data bus 67.

When the data read access request is issued in the data processing device 100 and the data to be accessed is registered in the primary cache memory 10,
The cache hit / miss signal generation unit 44 of the primary cache memory 10 outputs the cache hit signal 46, and the data unit 33 of the primary cache memory 10 outputs the data to the output buffer 37, which temporarily holds the data. Then, the data held in the output buffer 37 of the primary cache memory 10 is output to the data bus 67 by the signal 49 output from the output buffer control circuit 45 of the primary cache memory 10, and the data processing device 100 as it is. Transferred to.

A case where a data write access request is issued in the data processing device 100 will be described.
When both primary and secondary cache memories 10 and 11 are write-through type, data write access (104, 105) is executed to primary and secondary cache memories 10 and 11 regardless of cache write hit / miss. To be done. for that reason,
Address for data write is address bus 60 → 61
→ 62 routes, primary and secondary caches 10, 11 and main memory 1
Entered in 03.

The data registered in the cache memory is transferred through the data bus and the bypass path. That is, the data is input through the route of data bus 67 → 66 → 65 → 64 → 63 and temporarily stored in the line buffers 35 of the primary and secondary cache memories 10 and 11, respectively. When a cache write hit occurs in the primary and secondary cache memories 10 and 11, the data held in the line buffer 35 is registered in the cache memories 10 and 11 together with the tag by the cache write hit signal 40. Further, the data write access is also executed (106) to the main memory 103 by the address and the data output from the secondary cache memory 11.

In the fourth invention of the data processing system of the present invention shown in FIGS. 11 and 12 and 13, as described above, it is the primary cache that first fetches data from the main memory 103. There is only memory 10. Data that cannot be registered in the primary cache memory 10 in terms of capacity is then registered in the secondary cache memory 11. Therefore, unless a cache hit occurs in the secondary cache memory 11, the data captured in the primary and secondary cache memories 10 and 11 do not overlap. However, when a cache hit occurs in the secondary cache memory 11, the hit data is also registered in the primary cache memory 10, so double registration of the same data occurs.

A block diagram of FIG. 14 shows a configuration example of a data processing system having a two-level cache memory as an embodiment of the fifth invention of the data processing system of the present invention. In FIG. 14, reference numeral 100 indicates a data processing device,
Reference numeral 10 is a primary cache memory connected to the data processing device 100, 11 is a secondary cache memory connected to the primary cache memory 10, and 103 is a main memory connected to the secondary cache memory 11. .

The operation of the fifth embodiment of the data processing system of the present invention shown in the block diagram of FIG. 14 will be described below.

When a data read access request is issued in the data processing device 100, first, a data read access (104) is made to the primary cache memory 10.
When a cache miss occurs in the primary cache memory 10, a data read access from the primary cache memory 10 to the secondary cache memory 11 (105)
Is done. Further, if a cache miss also occurs in the secondary cache memory 11, a data read access (106) is performed from the secondary cache memory 11 to the main memory 103.

Then, the data read access (106)
For the data read from the main memory 103,
It is transferred / registered (112) to the next cache memory 11, and then 1
The data is transferred / registered (111) to the next cache memory 10 and then transferred (110) to the data processing device 100.

The data processing system shown in FIG. 14 operates differently from the conventional data processing system when a cache read hit occurs in secondary cache memory 11.

That is, when a cache hit occurs during the data read access (105) to the secondary cache memory 11, the hit data (A) is the primary cache memory.
After transfer / registration (12a) to 10, secondary cache memory
Disabled in 11 But in this case, hit data
When it is necessary to erase the data (B) already registered in the primary cache memory 10 in order to register (A) in the primary cache memory 10 (that is, hit data ( All lines for registering A) are filled, and data (B) must be overwritten in order to register hit data (A)),
The primary cache memory 10 makes a write access (12b) to the data (B) to the secondary cache memory 11. Write access from the primary cache memory 10 for this data (B)
According to 12b, data is stored in the secondary cache memory 11
If (B) is already registered, the data (B) is not registered, and if it is not registered, it is transferred / registered.

Further, in response to a data write access request generated in the data processing device 100, the primary cache memory 10
When there is a cache read hit in, the data is directly transferred (110) to the data processing device 100. On this occasion,
Data read access to the secondary cache memory 11 and the main memory 103 is not performed.

When a data write access request is issued in the data processing device 100, if both the primary and secondary cache memories 10 and 11 are write-through type cache memories, the primary cache memory 10 must be accessed. Data write access (104, 105, 106) is performed for both the secondary cache memory 11 and the main memory 103.

The data written at this time is 1 from the data processing device 100 through the route of reference numeral 107 → 108 → 109.
The data is transferred to the secondary and secondary cache memories 10 and 11 and the main memory 103. By such processing, data consistency is maintained in the write-through cache memory.

In the fifth aspect of the data processing system of the present invention, as described above, the secondary cache memory 11
If there is a cache read hit in and there is no room to register new hit data in the capacity of the primary cache memory 10, instead of overwriting the hit data in the primary cache memory 10 and invalidating the old data, ,
Transfer and register old data in the secondary cache memory 11. Such processing improves the hit rate of the cache memory as a whole.

FIGS. 15 and 16 show an example of the circuit configuration when the primary cache memory 10 and the secondary cache memory 11 of the fifth invention of the data processing system of the present invention shown in FIG. 14 are connected. A block diagram is shown. Note that the primary cache memory 10 connected between the data processing device 100 and the secondary cache memory 11 in FIG. 15 is connected between the main memory 103 and the primary cache memory 10 in FIG. The respective secondary cache memories 11 are shown.

The primary cache memory 10 and the secondary cache memory 11 shown in FIGS. 15 and 16 differ from the conventional configuration in that the output buffer control circuit 45 and the address latch 51 are provided in the primary cache memory 10. Is provided. The output buffer control circuit 45 controls whether to output the data taken in the output buffer 37 to the data bus. The latch 51 is a latch that holds an address corresponding to the data taken into the output buffer 37 under the control of the output buffer control circuit 45 described above.

Further, in the primary cache memory 10 and the secondary cache memory 11 shown in FIGS. 15 and 16, the cache hit / miss signal generation unit, which is conventionally indicated by reference numeral 36, is indicated by reference numeral 44. It is shown. The cache hit / miss signal generation unit 44 has a function of outputting certain data (A) on the line to the output buffer 37 if the line of the data unit 33 is full when a cache miss occurs. Further, in the secondary cache memory 11 shown in FIGS. 15 and 16, the cache hit signal 46 output from the cache hit / miss signal generation unit 44 is the cache hit / miss signal generation unit of the primary cache memory 10. It is also entered in 44.

Next, the operation of the fifth embodiment of the data processing system of the present invention shown in FIGS. 14, 15, and 16 will be described, particularly the operation of the cache memory.

When a data read access request is issued in the data processor 100, the primary cache memory 10
A data read access (104) is performed to the. If no data is registered in the primary cache memory 10 for the access request, the cache hit / miss signal generator 44 of the primary cache memory 10 outputs a cache miss signal 47 to the secondary cache memory 11. A data read access (105) is performed. When no data is registered in the secondary cache memory 11, the cache hit / miss signal generation unit 44 of the secondary cache memory 11 is also included.
The cache miss signal 47 is output from the memory, and the data read access (106) is performed to the main memory 103.

The data read from the main memory 103 by this data read access (106) is input to the secondary cache memory 11 from the data bus 63 and the line buffer 35.
Are registered in the secondary cache memory 11 through. Also,
Data is also input to the primary cache memory 10 from the data bus 65 via the bypass path 64 and the data bus 65, and is registered in the primary cache memory 10 through the line buffer 35. Further, data is also transferred from the data bus 65 to the data processing device 100 via the bypass path 66 and the data bus 67.

When the capacity for registering new data in the primary cache memory 10 is exhausted in the series of processing for registering data in the cache memory from the main memory 103, the data is overwritten in the primary cache memory 10. It

As a result of the data read access (105) to the secondary cache memory 11, if the data to be accessed is registered in the secondary cache memory 11,
When the cache hit signal 46 is output from the cache hit / miss signal generation unit 44 of the secondary cache memory 11, the hit data (A) is temporarily held in the output buffer 37. The hit data (A) held in the output buffer 37 of the secondary cache memory 11 is transferred to the primary cache memory 10 via the data bus 65 and registered. At the same time, the hit signal 46 output from the cache hit / miss signal generation unit 44 of the secondary cache memory 11 is 1
It is also input to the cache hit / miss signal generation unit 44 of the next cache memory 10.

When the capacity for registering the hit data transferred from the secondary cache memory 11 is exhausted in the primary cache memory 10, the hit data (A) should be registered 1
Data from the data section 33 of the next cache memory 10 (B)
And the corresponding tag value are fetched into the output buffer 37 of the primary cache memory 10 and the tag latch 51.
The output buffer control circuit 45 of the primary cache memory 10 is
In consideration of the timing when the address bus 60 and the data bus 67 do not conflict with each other, the output buffer 37 and the tag latch 51 output the data (B) and the tag value signals 49 and 52, respectively. Output to bus 67.

The tag value output to the address bus 60 is input to the decoder 31 of the secondary cache memory 11 via the address bus 61 and output to the data bus 67.
(B) is bypass route 66, data bus 65, bypass route 6
4, transferred to the line buffer 35 of the secondary cache memory 11 via the data bus 63 and temporarily held.

At the same time, the output buffer control circuit 45 of the primary cache memory 10 outputs a data write signal 48 to the cache hit / miss signal generator 44 of the secondary cache memory 11. Upon receiving the signal 48, the cache hit / miss signal generation unit 44 of the secondary cache memory 11 determines the cache write hit / miss for the write access from the primary cache memory 10. Then, the secondary cache memory 11 does not register the data (B) held in the line buffer 35 in the data section 33 if there is a cache write hit, and registers the data if there is a cache write miss.

As described above, in the fifth invention of the data processing system of the present invention shown in FIGS. 14 and 15 and 16,
When the secondary cache memory 11 is hit, 1 is required to register the hit data in the primary cache memory 10.
The data invalidated in the secondary cache memory 10 is registered in the secondary cache memory 11. Therefore, since more data can be registered in the entire cache memory,
This will improve the hit rate of the cache memory as a whole.

A block diagram of FIG. 17 shows a configuration example of a data processing system having a two-level cache memory as an embodiment of the sixth invention of the data processing system of the present invention. In FIG. 17, reference numeral 100 indicates a data processing device,
10 is a primary cache memory connected to the data processing device 100, 11 is a secondary cache memory connected to the primary cache memory 10, and 103 is a main memory connected to the secondary cache memory 11. There is.

The operation of the sixth embodiment of the data processing system of the present invention shown in the block diagram of FIG. 17 will be described below.

When a data read access request is issued in the data processing device 100, first, a data read access (104) is made to the primary cache memory 10.
When a cache miss occurs in the primary cache memory 10, a data read access from the primary cache memory 10 to the secondary cache memory 11 (105)
Is done. Further, if a cache miss also occurs in the secondary cache memory 11, the secondary cache memory
Data read access from main memory 103 from 11 (106)
Is done.

Then, the data read access (106)
For the data read from the main memory 103,
It is transferred / registered (112) to the next cache memory 11, and then 1
The data is transferred / registered (111) to the next cache memory 10 and then transferred (110) to the data processing device 100.

The sixth aspect of the data processing system of the present invention shown in FIG. 17 operates differently from the conventional data processing system when a cache read hit occurs in the secondary cache memory 11.

That is, if a cache hit occurs during the data read access (105) to the secondary cache memory 11, the hit data (A) is the primary cache memory.
Transferred to 10 and registered (13). However, when there is no capacity to register new hit data (A) in the primary cache memory 10 when registering the hit data (A) in the primary cache memory 10, the data (B) that is invalidated in the conventional case Write access (13) is performed to the secondary cache memory 11.

In response to this write access (13), in the secondary cache memory 11, if the data (B) already exists, it is not registered. If it does not exist, hit data until then is registered.
Register data (B) at the position where (A) was registered. That is, the primary cache memory 10 and the secondary cache memory 11
Data (A) and data (B) will be exchanged between and.

In addition, in response to a data write access request generated from the data processing device 100, the primary cache memory
When a cache read hit occurs in 10, the data is transferred (110) to the data processing device 100 as it is.
At this time, the data read access to the secondary cache memory 11 and the main memory 103 is not performed.

When a data write access request is issued in the data processor 100, if both the primary and secondary cache memories 10 and 11 are write-through type cache memories, the primary cache memory 10 must be Data write access (104, 105, 106) is performed for both the secondary cache memory 11 and the main memory 103.

The data to be written at this time is 1 from the data processor 100 through the route of reference numeral 107 → 108 → 109.
The data is transferred to the secondary and secondary cache memories 10 and 11, and further to the main memory 103. By such processing, data consistency is maintained in the write-through cache memory.

In the sixth invention of the data processing system of the present invention shown in FIG. 17, as described above, a cache read hit occurs in the secondary cache memory 11, and the hit data is in terms of capacity. The position where the old data hit data in the secondary cache memory 11 is registered instead of overwriting the primary cache memory 10 and invalidating the old data when it cannot be registered in the primary cache memory 10. Be registered with. Therefore, the hit rate of the cache memory as a whole is further improved.

In the first to sixth inventions of the data processing system of the present invention described with reference to FIGS. 1 to 17 above,
When some processing occurs, the registered data may not match in the primary cache memory and the secondary cache memory. In other words, a data copy of the data stored in the main memory 103 may not exist in the secondary cache memory 11 but may exist in the primary cache memory 10. Therefore, it becomes possible to register a copy of data having a capacity larger than that of the secondary cache in the cache memory as a whole. However, if something like the above does not occur,
All the data copies registered in the primary cache memory are in the state registered in the secondary cache memory.

The seventh to ninth inventions of the data processing system of the present invention shown in FIGS. 18 to 15 below are for solving the above-mentioned problems. That is, in each of the following inventions, the same data is not registered in the primary cache memory and the secondary cache memory at all, and the capacity of the primary cache memory and the capacity of the secondary cache memory are added to the entire cache memory. A data copy having the same capacity as that of the main memory 103 can be fetched.

A block diagram of FIG. 18 shows a configuration example of a data processing system having a two-level cache memory as an embodiment of the seventh invention of the data processing system of the present invention.

In FIG. 18, reference numeral 100 is a data processor, 10 is a primary cache memory connected to the data processor 100, 11 is a secondary cache memory connected to the primary cache memory 10, 103 Indicate main memories connected to the secondary cache memory 11.

The operation of the seventh embodiment of the data processing system of the present invention shown in the block diagram of FIG. 18 will be described below. The data processing system of the present invention shown in FIG. 18 includes both the data processing system of the first invention shown in FIG. 1 and the data processing system of the fourth invention shown in FIG. It is configured to combine the functions of.

When a data read access request is issued in the data processing device 100, first, a data read access (104) is made to the primary cache memory 10.
When a cache miss occurs in the primary cache memory 10, a data read access from the primary cache memory 10 to the secondary cache memory 11 (105)
Is done. Further, if a cache miss also occurs in the secondary cache memory 11, the secondary cache memory
Data read access from main memory 103 from 11 (106)
Is done.

Then, the data read access (106)
However, the data read from the main memory 103 is not registered in the secondary cache memory 11 and the primary cache memory
Directly transferred to 10 and registered (9) on the data processor
Transferred to 110 (110). A series of processing for directly registering data from the main memory 103 to the primary cache memory 10 (9)
If unregisterable data occurs in the primary cache memory 10 in the process of, the data is transferred / registered from the primary cache memory 10 to the secondary cache memory 11.
(8) It is done.

If a cache hit occurs in the secondary cache memory 11 in response to a data read access request from the data processing device 100, the secondary cache memory
The hit data (A) in 11 is invalidated after being transferred / registered (14) to the primary cache memory 10.

When a cache hit occurs in the primary cache memory 10 in response to a data read access request from the data processing device 100, the hit data is transferred (110) to the data processing device 100 as it is. At this time, the data read access to the secondary cache memory 11 and the main memory 103 is not performed.

When a data write access request is issued in the data processing device 100, if both the primary and secondary cache memories 10 and 11 are write-through type cache memories, the primary cache memory 10 must be written. Data write access (104, 105, 106) is performed for both the secondary cache memory 11 and the main memory 103.

The data to be written at this time is 1 from the data processor 100 through the route of reference numeral 107 → 108 → 109.
The data is transferred to the secondary and secondary cache memories 10 and 11, and further to the main memory 103. By such processing, data consistency is maintained in the write-through cache memory.

In the seventh invention of the data processing system of the present invention shown in FIG. 18, as described above, 1
When the same data is about to be registered in both the secondary cache memory 10 and the secondary cache memory 11, it is controlled so that the data is registered only in the primary cache memory 10.
The duplicate registration of the same data in both the secondary and secondary cache memories 10 and 11 is avoided. Therefore, as a whole cache memory, it is possible to register a data copy having a capacity equal to the sum of the capacities of both the primary and secondary cache memories 10 and 11 from the main memory 103.

This is because the primary and secondary cache memories
When the capacities of 10 and 11 themselves are the same as the conventional one, the memory area of the primary cache memory 10 can be used more effectively than before, so that the average access time of data access is reduced.

A block diagram of FIG. 19 shows a configuration example of a data processing system having a two-level cache memory as an embodiment of the eighth invention of the data processing system of the present invention. In FIG. 19, reference numeral 100 indicates a data processing device,
10 is a primary cache memory connected to the data processing device 100, 11 is a secondary cache memory connected to the primary cache memory 10, and 103 is a main memory connected to the secondary cache memory 11. There is.

The operation of the eighth embodiment of the data processing system of the present invention shown in the block diagram of FIG. 19 will be described below. The data processing system of the present invention shown in FIG. 19 is obtained by providing the data processing system of the seventh invention shown in FIG. 18 with an additional function. Specifically, the data processing system of the eighth invention shown in FIG. 19 is the same as the data processing system of the first invention shown in FIG. 1 and the fifth invention shown in FIG. It is configured to have both functions as a data processing system.

When a data read access request is generated in the data processing device 100, first, a data read access (104) is made to the primary cache memory 10.
When a cache miss occurs in the primary cache memory 10, a data read access from the primary cache memory 10 to the secondary cache memory 11 (105)
Is done. Further, if a cache miss also occurs in the secondary cache memory 11, the secondary cache memory
Data read access from main memory 103 from 11 (106)
Is done.

Then, the data read access (106)
However, the data read from the main memory 103 is not registered in the secondary cache memory 11 and the primary cache memory
Directly transferred to 10 and registered (9) on the data processor
Transferred to 110 (110). A series of processing for directly registering data from the main memory 103 to the primary cache memory 10 (9)
If unregisterable data occurs in the primary cache memory 10 in the process of, the data is transferred / registered from the primary cache memory 10 to the secondary cache memory 11.
(8) It is done.

When a cache hit occurs in the secondary cache memory 11 in response to a data read access request from the data processing device 100, the secondary cache memory
The hit data (A) in 11 is invalidated after being transferred / registered (12a) to the primary cache memory 10. However, in this case, in order to register the hit data (A) in the primary cache memory 10, it is necessary to erase the data (B) already registered in the primary cache memory 10 (that is, the primary cache memory 10). Hit data in cache memory 10 (A)
When all the lines for registering the data are filled and the data (B) must be overwritten in order to register the hit data (A)), the primary cache memory 10 has a write access to that data (B). (12b) is performed on the secondary cache memory 11. Primary cache memory of this data (B) 10
In response to the write access (12b) from the secondary cache memory 11, if the data (B) is already registered, the data (B) is not registered, and the transfer / registration is performed only when the data (B) is not registered. To do.

When a cache hit occurs in the primary cache memory 10 in response to a data read access request from the data processing device 100, the hit data is transferred (110) to the data processing device 100 as it is. At this time, the data read access to the secondary cache memory 11 and the main memory 103 is not performed.

When a data write access request is issued in the data processing device 100, if both the primary and secondary cache memories 10 and 11 are write-through type cache memories, the primary cache memory 10 must be written. Data write access (104, 105, 106) is performed for both the secondary cache memory 11 and the main memory 103.

The data written at this time is 1 from the data processing device 100 through the route of reference numeral 107 → 108 → 109.
The data is transferred to the secondary and secondary cache memories 10 and 11, and further to the main memory 103. By such processing, data consistency is maintained in the write-through cache memory.

In the eighth invention of the data processing system of the present invention shown in FIG. 19, the seventh invention shown in FIG.
Of the data processing system of the present invention, namely, the primary,
It has a feature that the same data is not registered in both the secondary cache memories 10 and 11. Further, by providing a function of registering the data that cannot be registered in the primary cache memory 10 in the secondary cache memory 11, the hit rate of the cache memory as a whole is improved.

A block diagram of FIG. 20 shows a configuration example of a data processing system having a two-level cache memory as an embodiment of the ninth invention of the data processing system of the present invention. In FIG. 20, reference numeral 100 indicates a data processing device,
10 is a primary cache memory connected to the data processing device 100, 11 is a secondary cache memory connected to the primary cache memory 10, and 103 is a main memory connected to the secondary cache memory 11. There is.

The operation of the ninth embodiment of the data processing system of the present invention shown in the block diagram of FIG. 20 will be described below. The data processing system of the present invention shown in FIG. 20 is obtained by adding an additional function to the data processing system of the seventh invention shown in FIG. Specifically, the data processing system of the ninth invention shown in FIG. 20 is the data processing system of the first invention shown in FIG. 1 and the data processing system of the fifth invention shown in FIG. It is configured to have both functions as a data processing system.

When a data read access request is issued in the data processing device 100, first, a data read access (104) is made to the primary cache memory 10.
When a cache miss occurs in the primary cache memory 10, a data read access from the primary cache memory 10 to the secondary cache memory 11 (105)
Is done. Further, if a cache miss also occurs in the secondary cache memory 11, the secondary cache memory
Data read access from main memory 103 from 11 (106)
Is done.

Then, the data read access (106)
However, the data read from the main memory 103 is not registered in the secondary cache memory 11 and the primary cache memory
Directly transferred to 10 and registered (9) on the data processor
Transferred to 110 (110). A series of processing for directly registering data from the main memory 103 to the primary cache memory 10 (9)
If unregisterable data occurs in the primary cache memory 10 in the process of, the data is transferred / registered from the primary cache memory 10 to the secondary cache memory 11.
(8) It is done.

When a cache read hit occurs in the secondary cache memory 11 in response to a data read access request from the data processor 100, the hit data (A) is transferred / registered (13) in the primary cache memory 10. . But 1
When registering the hit data (A) in the secondary cache memory 10, new hit data is stored in the primary cache memory 10.
If there is no capacity to register (A), write access (13) of data (B) that is invalidated in the conventional case is performed to the secondary cache memory 11.

In response to this write access (13), the secondary cache memory 11 does not register the data (B) if it already exists, or hit data until that time if it does not exist.
Register data (B) at the position where (A) was registered. That is, the primary cache memory 10 and the secondary cache memory 11
Data (A) and data (B) will be exchanged between and.

If a cache hit occurs in the primary cache memory 10 in response to a data read access request from the data processing device 100, the hit data is transferred (110) to the data processing device 100 as it is. At this time, the data read access to the secondary cache memory 11 and the main memory 103 is not performed.

When a data write access request is issued in the data processing device 100, if both the primary and secondary cache memories 10 and 11 are write-through type cache memories, the primary cache memory 10 must be accessed. Data write access (104, 105, 106) is performed for both the secondary cache memory 11 and the main memory 103.

The data written at this time is 1 from the data processing device 100 through the route of reference numeral 107 → 108 → 109.
The data is transferred to the secondary and secondary cache memories 10 and 11, and further to the main memory 103. By such processing, data consistency is maintained in the write-through cache memory.

In the ninth invention of the data processing system of the present invention shown in FIG. 20, the seventh invention shown in FIG.
Of the data processing system of the present invention, namely, the primary,
It has a feature that the same data is not registered in both the secondary cache memories 10 and 11. Further, by providing a function of registering the data that cannot be registered in the primary cache memory 10 in the secondary cache memory 11, the hit rate of the cache memory as a whole is improved. Further, since this is realized by the process of the data exchange between the primary cache memory 10 and the secondary cache memory 11, which is less wasteful, the power consumption can be further reduced.

The above-described data processing systems of the first to ninth inventions shown in FIGS. 1 to 20 include a plurality of pyramid-shaped data processing devices 100 and main memories 103. In the embodiment, two cache memories are provided. That is, the primary cache memory 10 (101) is directly connected only to the data processing device 100 and the secondary cache memory 11 (102). Therefore, the main memory 103 cannot be accessed from the primary cache memory 10 (101) without going through the secondary cache memory 11 (102). The secondary cache memory 11 (102) is directly connected only to the primary cache memory 10 (101) and the main memory 103. For this reason, the secondary cache memory 11 (102) must be connected to the data processing device without the primary cache memory 10 (101).
You cannot access 100.

On the other hand, in the tenth to twelfth inventions shown in FIG. 21 to FIG. 25 below, a configuration example of the data processing system of the present invention which can be accessed differently from the above and an outline of its operation Will be described.

A block diagram of FIG. 21 shows a configuration example of a data processing system having a two-level cache memory as an embodiment of the tenth invention of the data processing system of the present invention. In FIG. 21, reference numeral 100 indicates a data processing device,
10 is a primary cache memory connected to the data processing device 100, and 11 is a secondary cache memory connected to the data processing device 100.
The secondary cache memory, 103 is the secondary cache memory 11
The main memory connected to each is shown.

The operation of the tenth embodiment of the data processing system of the present invention shown in the block diagram of FIG. 21 will be described below.

When a data read access request is issued in the data processing device 100, the data read access request is simultaneously issued to both the primary and secondary cache memories 10 and 11. When there is no hit data for the data read access (104) in both the primary and secondary cache memories 10 and 11, the secondary cache memory 11 stores the main memory 103
A data read access (106) is performed to the.

The data read from the main memory 103 for this data read access (106) was not registered in the secondary cache memory 11 but was directly transferred / registered (9) only in the primary cache memory 10. The data is transferred (110) to the data processing device 100. In this way, when data that cannot be registered in the primary cache memory 10 occurs when data is registered in the primary cache memory 10 from the main memory 103, that data is transferred and registered in the secondary cache memory 11.
(8) It is done.

When a cache read hit occurs in the secondary cache memory 11 in response to a data read access request from the data processing device 100, the hit data is transferred / registered (110) to the data processing device 100 and at the same time 1
It is also transferred / registered (111) to the next cache memory 10. At this time, the data read access to the main memory 103 is not performed. When a cache read hit occurs in the primary cache memory 10 in response to a data read access request from the data processing device 100, the hit data is directly transferred (110) to the data processing device 100 and at the same time the secondary cache memory 11 is accessed. Data output from is prohibited. At this time, the data read access to the main memory 103 is not performed.

When a data write access request is issued in the data processor 100, if both the primary and secondary cache memories 10 and 11 are write-through type cache memories, the primary and secondary cache memories 10 and 11 must be 11
Data write access (104, 106) is also performed to the main memory 103.

The data written at this time is transferred from the secondary cache memory 11 to the main memory 103 and simultaneously to the primary cache memory 10 from the data processing device 100 through the route of reference numeral 107 → 109. By such processing, data consistency is maintained in the write-through cache memory.

22 and 23 show examples of circuit configurations when the primary cache memory 10 and the secondary cache memory 11 of the tenth invention of the data processing system of the present invention shown in FIG. 21 are connected. A block diagram is shown.

The primary and secondary cache memories 10 and 11 used in the tenth invention of the data processing system of the present invention shown in FIGS. 22 and 23 are shown in FIGS. The cache memory has the same structure as the cache memory used in the data processing system of the fourth invention.
0, 11 The connection between them is different. That is, FIG. 22 and FIG.
In the tenth aspect of the data processing system of the present invention shown in FIG. 1, the primary and secondary cache memories 10 and 11 are connected to the data processing device 100 via the input address bus 60 and the data bus 67. Therefore, the data processing device 100 can simultaneously access the primary and secondary cache memories 10 and 11.

Also, the secondary cache memory 11 is the main memory 10
It is connected to 3 via an address bus 62 and a data bus 63. An address bus 60 and an address bus 62 are connected between the primary and secondary cache memories 10 and 11, and a data bus 67 is connected to a data bus 65 of the primary cache memory 10 via a bypass path 66. In addition, the data bus of the secondary cache memory 11 via the bypass path 64
It is connected to 63 respectively. Therefore, data can be simultaneously transferred from the main memory 103 to the primary and secondary cache memories 10 and 11.

Next, the operation of the tenth embodiment of the data processing system of the present invention shown in FIGS. 21, 22, and 23, particularly the operation of the cache memory, will be described.

When a data read access request is issued in the data processor 100, a data read access is simultaneously executed to both the primary and secondary cache memories 10 and 11 via the address bus 60. The data for this data read access (104) is the primary cache memory.
If not present in the cache memory 10, the cache hit / miss signal generation unit 44 of the primary cache memory 10 outputs the disabled cache read hit signal 46 and the cache hit / miss signal generation unit 44 of the secondary cache memory 11 is input. It If the data does not exist also in the secondary cache memory 11, the cache hit / miss signal generation unit 44 of the secondary cache memory 11 outputs the cache miss signal 50, and the data read access (10
6) is performed.

The data read from the main memory 103 by this data read access (106) is input to the line buffer 35 of the secondary cache memory 11 from the data bus 63 and further output to the data bus 67 through the bypass path 64. Are transferred to the data processing device 100. At the same time,
Data on data bus 67 is bypassed 66 and data bus 65
Through the line buffer 35 of the primary cache memory 10
Is transferred to and held once. The data held in the line buffer 35 of the primary cache memory 10 is 1
The primary cache memory together with the tag registered in the latch 34 by the cache miss signal 47 output from the cache hit / miss signal generator 44 of the secondary cache memory 10.
Registered in 10.

As described above, when the data for the data read access request from the data processor 100 does not exist in any of the cache memories 10 and 11, the main memory
The data read from 103 is the primary cache memory 10
Will be transferred and registered (9) only.

If unregisterable data is generated in the primary cache memory 10 during the registration, in other words, the data is registered in all 4-way lines of the primary cache memory 10. If any of the 4-way data needs to be overwritten in order to register new data, the data is stored in the primary cache memory 10
Is temporarily stored in the output buffer 36 of the. Then, looking at the timing when the data bus 67 is not used,
The output buffer control circuit 45 of the primary cache memory 10 outputs the signal 49, whereby the data of the output buffer 36 is output to the data bus 67.

The data thus output to the data bus 67 is held in the line buffer 35 of the secondary cache memory 11 in the line buffer 35 through the bypass path 64 and the data bus 63.
The signal 48 output from the output buffer control circuit of the primary cache memory 10 causes the secondary cache memory together with the tag.
Registered in 11.

A block diagram of FIG. 24 shows a configuration example of a data processing system having a two-level cache memory as an embodiment of the eleventh invention of the data processing system of the present invention. In FIG. 24, reference numeral 100 indicates a data processing device,
Reference numeral 10 is a primary cache memory connected to the data processing device 100, 11 is a secondary cache memory connected to the primary cache memory 10, and 103 is a main memory connected to the primary cache memory 10. There is.

The operation of the 11th embodiment of the data processing system of the present invention shown in the block diagram of FIG. 24 will be described below.

When a data read access request is issued in the data processing device 100, first, a data read access (104) is made to the primary cache memory 10.
When a cache miss occurs in the primary cache memory 10, data read access (105) is simultaneously performed from the primary cache memory 10 to the secondary cache memory 11 and the main memory 103.

When a cache read miss occurs in the secondary cache memory 11, the data read from the main memory 103 is transferred / registered (9) directly to the primary cache memory 10 without going through the secondary cache memory 11. The data is transferred (110) to the data processing device 100. A series of processes for directly registering data from the main memory 103 to the primary cache memory 10.
If unregisterable data occurs in the primary cache memory 10 in the process of (9), the data is transferred / registered (8) in the secondary cache memory 11.

When a cache read hit occurs in the secondary cache memory 11 in response to a data read access request from the data processor 100, the hit data is 1
The data is transferred and registered (111) in the next cache memory 10, and then transferred (110) to the data processing device 100. On this occasion,
The data read from the main memory 103 is canceled.

When a cache read hit occurs in the primary cache memory 10 in response to a data read access request from the data processing device 100, the hit data is directly transferred (110) to the data processing device 100. At this time, 2
Data read access to the next cache memory 11 and the main memory 103 is not performed.

When a data write access request is issued in the data processor 100, if both the primary and secondary cache memories 10 and 11 are write-through type cache memories, the primary cache memory 10 must be Data write access (104, 105) is also performed to the secondary cache memory 11 and the main memory 103.

The data written at this time is transferred from the data processor 100 to the primary and secondary cache memories 10 and 11 and further to the main memory 103 by the route of reference numeral 107 → 108. By such processing, data consistency is maintained in the write-through cache memory.

A block diagram of FIG. 25 shows a configuration example of a data processing system having a two-level cache memory as an embodiment of the twelfth invention of the data processing system of the present invention. In FIG. 25, reference numeral 100 indicates a data processing device,
Reference numeral 10 is a primary cache memory connected to the data processing device 100, and 11 is similarly connected to the data processing device 100.
The next cache memory, 103 is the primary cache memory 10
The main memory connected to each is shown.

The operation of the twelfth embodiment of the data processing system of the present invention shown in the block diagram of FIG. 25 will be described below.

When a data read access request is issued in the data processing device 100, the request is simultaneously issued to both the primary and secondary cache memories 10 and 11. Primary, 2
When there is no data corresponding to the data read access request in both the secondary cache memories 10 and 11, the primary cache memory 10 performs a data read access (106) to the main memory 103.

The data read from the main memory 103 is directly transferred / registered (9) to the primary cache memory 10 and then transferred (110) to the data processing device 100. Main memory
When data that cannot be registered in the primary cache memory 10 occurs when data is registered in the primary cache memory 10 from 103, the data is stored in the secondary cache memory 11
Will be transferred and registered (8).

When a cache read hit occurs in the secondary cache memory 11 in response to a data read access from the data processing device 100, the hit data is transferred (110) to the data processing device 100 and at the same time the primary data is read. It is also transferred and registered (111) in the cache memory 10. On this occasion,
No data read access is made to the main memory 103.

When a cache read hit occurs in the primary cache memory 10 in response to a data read access request from the data processing device 100, the hit data is directly transferred (110) to the data processing device 100 and at the same time the secondary data is read. Data output from the cache memory 11 is prohibited. At this time, the data read access to the main memory 103 is not performed.

When a data write access request is issued in the data processor 100, if both the primary and secondary cache memories 10 and 11 are write-through type cache memories, the primary and secondary cache memories 10 and 11 must be 11
Data write access (104, 106) is also performed to the main memory 103.

The data written at this time is transferred from the data processing device 100 to the primary and secondary cache memories 10 and 11 and further to the main memory 103 by the route of reference numeral 107 → 108. By such processing, data consistency is maintained in the write-through cache memory.

In the block diagram of FIG. 26, a demand type primary cache memory 20 and a prefetch type secondary cache memory 21 are shown as a data processing device 100 as one embodiment of a thirteenth invention of the data processing system of the present invention. A configuration example of a data processing system provided hierarchically with the main memory 103 will be shown.

In FIG. 26, reference numeral 100 is a data processing device, 20 is a demand type primary cache memory connected to the data processing device 100, and 21 is a prefetch type 2 connected to the primary cache memory 20. A secondary cache memory and 103 are main memories connected to the secondary cache memory.

Here, the demand type cache memory is a cache memory in which only data requested to be accessed from the outside is registered. On the other hand, the prefetch type cache memory is a cache memory in which not only data requested to be accessed from the outside but also some data consecutive to the data are registered in advance.

The operation of the thirteenth embodiment of the data processing system of the present invention shown in the block diagram of FIG. 26 will be described below.

When a read access request for data (A) is issued in the data processing device 100, first, a data read access (104) is made to the primary cache memory 20.
Is done. When data (A) does not exist in the primary cache memory 20 and a cache miss occurs, a data read access (105) is performed from the primary cache memory 20 to the secondary cache memory 21. In the data read access (105) at this time, since the primary cache memory 20 is a demand type cache memory, the read access to only the data (A) is output. If a cache miss also occurs in the secondary cache memory 21, 2
A data read access (106) is performed from the next cache memory 21 to the main memory 103.

At this time, the data read access (106) is
Since the secondary cache memory 21 is a prefetch type cache memory, the data (A) and the data continuous with it
It is also done for (B). This data read access
Data (A) read from main memory 103 for (106)
Is not registered in the secondary cache memory 21, is transferred and registered (9) only in the primary cache memory 20, and is then transferred (110) to the data processing device 100. Further, the data (B) following the data (A) is also read from the main memory 103 and transferred / registered (15) only to the secondary cache memory 21.

When a cache hit occurs in the secondary cache memory 21 in response to a data read access request from the data processing device 100, the hit data is transferred / registered (111) in the primary cache memory 20 and then the data is transferred. It is transferred (110) to the processing device 100. At this time, the data read access to the main memory 103 is not performed.

When a cache hit occurs in the primary cache memory 20 in response to a data read access request from the data processing device 100, the hit data is transferred (110) to the data processing device 100 as it is. At this time, the data read access to the secondary cache memory 21 and the main memory 103 is not performed.

When data that cannot be registered in the primary cache memory 20 occurs when data is transferred / registered (9) from the main memory 103 to the primary cache memory 20, that data is stored in the secondary cache memory 21. Data is registered (8).

When a data write access request is issued in the data processing device 100, if both the primary and secondary cache memories 20 and 21 are write-through type cache memories, the primary cache memory 20 is guaranteed. Data write access (104, 105, 106) is performed for both the secondary cache memory 21 and the main memory 103.

The data written at this time is 1 from the data processing device 100 through the route of reference numeral 107 → 108 → 109.
The data is transferred to the secondary and secondary cache memories 20 and 21, and further to the main memory 103. By such processing, data consistency is maintained in the write-through cache memory.

In the circuit diagram of FIG. 27, the prefetch for judging whether or not the prefetch type secondary cache memory 21 provided in the embodiment of the fourteenth invention of the data processing system of the present invention should perform the prefetch. The configuration of the suppression circuit will be described.

The data processing system of the fourteenth invention is
In the data processing system of the thirteenth invention shown in FIG. 26, the data (B) continuous with the data (A) is stored in the main memory 103.
This is because there is a case where the cache is not on the upper side and a cache or the like is in an inappropriate area, and in such a case, the prefetch type secondary cache memory 21 determines whether or not to perform prefetch.

In FIG. 27, reference numeral 70 indicates a prefetch suppressing circuit, which is provided in the secondary cache memory 21. This prefetch suppression circuit 70 is mainly composed of an I / O register 71 that stores an address inappropriate for caching, for example, an I / O address, and a register enable bit 72 that is set when the I / O register is valid. ing. Further, reference numeral 73 is a prefetch suppression circuit enable signal, and 74 is a prefetch inhibit signal 74.
Are shown respectively.

The I / O register 71 constitutes a register for storing one address in one column in the left-right direction in FIG. 27, and a register enable bit 72 is attached to each of them.
When an address to be accessed (fetch address) is input to the prefetch suppression circuit 70, when the register enable bit 72 is active and the addresses match, each register is grounded via the associated register enable bit 72. It Therefore, if the prefetch suppression circuit enable signal 73 is high level, if the fetch address matches the I / O address, a low level signal is output as the prefetch inhibit signal 74.
If they do not match, a high level signal is output.

The operation of the fourteenth embodiment of the data processing system of the present invention shown in FIGS. 26 and 27, particularly the operation of the prefetch suppressing circuit 70, will be described below.

When a read access request for data (A) is issued in the data processing device 100, first, a data read access (104) to the primary cache memory 20.
Is done. If no data (A) exists in the primary cache memory 20 and a cache miss occurs, a data read access (105) is made from the primary cache memory 20 to the secondary cache memory 21. The data read access (105) at this time is performed by the primary cache memory 20.
Since it is a demand type cache memory,
Only for (A). Further, if a cache miss also occurs in the secondary cache memory 21, a data read access (106) is made from the secondary cache memory 21 to the main memory 103.

At this time, the data read access (106) is
Since the secondary cache memory 21 is a prefetch type cache memory, the data to be originally accessed
This is done not only for (A) but also for data (B) that follows it. Therefore, the address of the prefetched data (B) is compared with the I / O register 71 in the prefetch suppression circuit 70. At this time, since the prefetch suppression circuit enable signal 73 is set to the high level, if the data (B) address is in the I / O area, the prefetch inhibit signal 74 is set to the high level and the data (B) address is set to the I / O area. If it is not in the O region, the prefetch prohibition signal 74 becomes low level.

In the secondary cache memory 21, when the prefetch inhibit signal 74 is at low level, the fetch address is judged to be prefetchable, and the main memory 103 is accessed. And data read access
Data (A) read from main memory 103 for (106)
Is not registered in the secondary cache memory 21, is transferred / registered (9) only in the primary cache memory 20, and is transferred (110) to the data processing device 100. Further, the data (B) following the data (A) is transferred / registered (15) only in the secondary cache memory 21.

If the data (B) is in the I / O area, the prefetch inhibit signal 74 goes high and the data
The data (B) following the data (A) is not accessed and is not registered in the secondary cache memory 21. By the operation of the prefetch suppressing circuit 70 as described above, fetching of the I / O area is avoided.

The block diagram of FIG. 28 shows an embodiment of the data processing system of the present invention when applied to a multiprocessor system as an embodiment of the 15th and 16th inventions. Figure
In FIG. 28, reference numeral 100a indicates a first data processing device,
Reference numeral 100b indicates a second data processing device, and reference numeral 100c indicates a third data processing device having a built-in cache memory.

Reference numeral 20a is the first data processing device 100a.
The primary cache memory of the first series connected to
Is one of the second series connected to the second data processing device 100b.
The secondary cache memory, 21a is the first series secondary cache memory connected to the first series primary cache memory 20a, and 21b is the second series secondary cache memory connected to the second series primary cache memory 20b. The secondary cache memory 21c is a secondary cache memory of the third series connected to the third data processor 100c.

Reference numeral 22 is a first series secondary cache memory 21a and a second series secondary cache memory 21b.
And a tertiary cache memory connected to the secondary cache memory 21c of the third series, 23 is a tertiary cache memory 22
Is a quaternary cache memory connected to, and 103 is a main memory connected to the quaternary cache memory 23.

The operation of the 15th and 16th embodiments of the data processing system of the present invention shown in the block diagram of FIG. 28 will be described below. The fifteenth invention is an invention in which the fourth invention shown in FIGS. 11 and 12 and 13 is applied to a multiprocessor system, and the 16th invention is described in FIGS. 3 is an example in which the first invention shown in FIG. 3 is applied to a multiprocessor system.

In the data processing system of the fifteenth invention, when the first data processing device 100a issues a data read access request for data (A) existing only in the main memory 103, first the primary cache memory of the first series. 20a accesses the first-level secondary cache memory 21a by causing a cache miss. However, the first series secondary cache memory 21a also causes a cache miss and accesses the tertiary cache memory 22. In addition, this third-level cache memory 22 also causes a cache miss to cause a fourth-level cache memory.
Access 23. However, this 4th level cache memory
23 also makes a cache miss and accesses the main memory 103. As a result, the data (A) from the main memory 103 is stored in the tertiary cache memory 22 and the primary cache memory 20a of the first series.
To be registered with.

Next, in the above-mentioned state, the second data processor
When 100b issues a data read access request for data (A), first, the second series primary cache memory 20b causes a cache miss, and the second series secondary cache memory.
Access 21b. However, the secondary cache memory 21b of the second series also causes a cache miss and accesses the tertiary cache memory 22.

In the data processing system of each invention up to the fifteenth invention, the main memory 103 is accessed next, but in the data processing system of the fifteenth invention, the third-level cache memory 22 is used.
Since there is a cache hit in the second data processing device 10
0b can read data (A) more quickly.

Further, although the tertiary cache memory 22 has a cache hit due to the data access by the second data processing device 100b described above, in the data processing system of the fifteenth invention, the data (A) in the tertiary cache memory 22 is Not disabled. Therefore, the data from the third data processing device 100c
Even when the data read access of (A) occurs, a high-speed data access is possible because a cache hit occurs in the tertiary cache memory 22 without accessing the main memory 103.

FIG. 29 is a block diagram showing a configuration example of a data processing system having a multi-level cache memory and having an address snoop function as one embodiment of the seventeenth and eighteenth inventions of the data processing system of the present invention. Show.

In FIG. 29, reference numeral 100 is a data processing device, 20 is a primary cache memory connected to the data processing device 100, 21 is a secondary cache memory connected to the primary cache memory 20, 22 Is a tertiary cache memory connected to the secondary cache memory 21, 103 is a main memory connected to the tertiary cache memory 22 and the data processing device 100, and 115 is a main memory connected to the main memory 103.
Other processing devices capable of rewriting the contents of 103 are respectively shown.

The operation of the seventeenth and eighteenth embodiments of the data processing system of the present invention shown in the block diagram of FIG. 29 will be described below.

First, for simplification of description, the basic function of the address snoop will be described. When the data (A) in the main memory 103 is stored in the secondary cache memory 21, for example, when another processor 115 rewrites the data (A) in the main memory 103 to (AA), the secondary cache memory
A state occurs in which the contents registered in 21 and the contents of the main memory 103 are different. In order to avoid such a data inconsistency between the main memory 103 and each cache memory, each cache memory uses the data in the main memory 103 as a data processing device.
When rewritten by a device other than 100, the corresponding data needs to be rewritten.

In the conventional data processing system having a plurality of cache memories, since a plurality of cache memories hold the same data, it is necessary to rewrite data in all the cache memories at the time of address snooping as described above. To start. In this way, if all the cache memories are activated at the same time, the power consumption of the entire data processing system will increase.

However, in the data processing system of the present invention,
In the seventeenth and eighteenth inventions, since a plurality of cache memories do not have overlapping data, it is not necessary to activate all the cache memories. This will be specifically described below.

In the data processing system of the seventeenth invention, when another processing device 115 rewrites the data (A) in the main memory 103 to (AA), the primary cache memory 20 firstly writes the data (A). It is judged whether or not it holds. As a result, 1
Since the secondary cache memory 20 does not hold the data (A), the secondary cache memory 21 in the lower stage is instructed to rewrite the data (A).

Next, the secondary cache memory 21 determines whether or not the secondary cache memory 21 itself holds the data (A). As a result, 2
Since the next cache memory 21 holds the data (A), the data (A) is invalidated. Secondary cache memory 21
Since the data (A) is not held in each cache memory in the lower stage, the tertiary cache memory 22 is not activated. Therefore, the power consumption can be reduced.

Further, in the data processing system of the eighteenth invention, another processing device 115 converts the data (A) in the main memory 103 into (AA).
When it is rewritten to, the third-level cache memory 22 first judges whether or not it holds the data (A). As a result, since the tertiary cache memory 22 does not hold the data (A), the secondary cache memory 21 in the upper stage has the data (A).
To rewrite.

Next, the secondary cache memory 21 determines whether or not the secondary cache memory 21 itself holds the data (A). As a result, 2
Since the next cache memory 21 holds the data (A), the data (A) is rewritten to (AA). Since the data (A) is not held in each cache memory above the secondary cache memory 21, the primary cache memory 20 is not activated. Therefore, the power consumption can be reduced.

[0308]

As described above in detail, according to the data processing system of the present invention, when the data requested by the cache memory in the upper stage and the data requested by the cache memory in the lower stage overlap with each other, The data area requested by the cache memory is registered only in the upper side cache memory, and the data excluding the data area requested by the upper side cache memory is registered in the lower side cache memory. By adopting such a data access procedure, it becomes possible for the cache memory as a whole to hold redundant data as much as possible.

Therefore, more data copies can be fetched from the main memory to the entire cache memory, the cache hit rate for data access from the data processing device is improved, and the data processing device can store more data in the cache memory. Data can be accessed at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a data processing system including a two-level cache memory as a first embodiment of the first invention.

FIG. 2 is a block diagram showing a circuit configuration example when the primary cache memory of the first embodiment of the data processing system of the first invention is connected to the secondary cache memory.

FIG. 3 is a block diagram showing a circuit configuration example when the secondary cache memory of the first embodiment of the data processing system of the first invention is connected to the primary cache memory.

FIG. 4 is a block diagram showing a configuration example of a data processing system including a two-level cache memory as a second embodiment of the first invention.

FIG. 5 is a block diagram showing a configuration example of a data processing system including a two-level cache memory as an embodiment of the second invention.

FIG. 6 is a block diagram showing a circuit configuration example when the primary cache memory of the data processing system of the second invention is connected to the secondary cache memory.

FIG. 7 is a block diagram showing a circuit configuration example when the secondary cache memory of the data processing system of the second invention is connected to the primary cache memory.

FIG. 8 is a block diagram showing a configuration example of a data processing system including a two-level cache memory as an embodiment of the third invention.

FIG. 9 is a block diagram showing a circuit configuration example when the primary cache memory of the data processing system of the third invention is connected to the secondary cache memory.

FIG. 10 is a block diagram showing a circuit configuration example when the secondary cache memory of the data processing system of the third invention is connected to the primary cache memory.

FIG. 11 is a block diagram showing a configuration example of a data processing system including a two-level cache memory as an embodiment of the fourth invention.

FIG. 12 is a block diagram showing a circuit configuration example when the primary cache memory of the data processing system of the fourth invention is connected to the secondary cache memory.

FIG. 13 is a block diagram showing a circuit configuration example when the secondary cache memory of the data processing system of the fourth invention is connected to the primary cache memory.

FIG. 14 is a block diagram showing a configuration example of a data processing system including a two-level cache memory as an embodiment of the fifth invention.

FIG. 15 is a block diagram showing a circuit configuration example when the primary cache memory of the data processing system of the fifth invention is connected to the secondary cache memory.

FIG. 16 is a block diagram showing a circuit configuration example when the secondary cache memory of the data processing system of the fifth invention is connected to the primary cache memory.

FIG. 17 is a block diagram showing a configuration example of a data processing system including a two-level cache memory as an embodiment of the sixth invention.

FIG. 18 is a block diagram showing a configuration example of a data processing system including a two-level cache memory as an embodiment of the seventh invention.

FIG. 19 is a block diagram showing a configuration example of a data processing system provided with a two-level cache memory as an embodiment of the eighth invention.

FIG. 20 is a block diagram showing a configuration example of a data processing system including a two-level cache memory as an embodiment of the ninth invention.

FIG. 21 is a block diagram showing a configuration example of a data processing system including a two-level cache memory as an embodiment of the tenth invention.

FIG. 22 is a block diagram showing a circuit configuration example when the primary cache memory of the data processing system of the tenth invention is connected to the secondary cache memory.

FIG. 23 is a block diagram showing a circuit configuration example when the secondary cache memory of the data processing system of the tenth invention is connected to the primary cache memory.

FIG. 24 is a block diagram showing a configuration example of a data processing system including a two-level cache memory as an embodiment of the eleventh invention.

FIG. 25 is a block diagram showing a configuration example of a data processing system including a two-level cache memory as an embodiment of the twelfth invention.

FIG. 26 is a block diagram showing a configuration example of a data processing system including a two-tier cache memory as an embodiment of the thirteenth invention.

FIG. 27 is a block diagram showing a configuration example of a data processing system including a two-level cache memory as an embodiment of the fourteenth invention.

FIG. 28 is a second example of the fifteenth and sixteenth inventions.
It is a block diagram which shows the structural example of the data processing system provided with the cache memory of a hierarchy.

FIG. 29 is a second example of the seventeenth and eighteenth inventions.
It is a block diagram which shows the structural example of the data processing system provided with the cache memory of a hierarchy.

FIG. 30 is a block diagram showing a configuration example of a conventional data processing system including a two-level cache memory.

FIG. 31 is a block diagram showing an example of a general circuit configuration of a cache memory of a conventional data processing system.

FIG. 32 is a block diagram showing a circuit configuration example when the primary cache memory of the conventional data processing system is connected to the secondary cache memory.

FIG. 33 is a block diagram showing a circuit configuration example when the secondary cache memory of the conventional data processing system is connected to the primary cache memory.

FIG. 34 is a schematic diagram for explaining details of a data access process in the cache memory of the conventional data processing system.

[Explanation of symbols]

 10 primary cache memory 11 secondary cache memory 20 primary cache memory 20a primary cache memory 20b primary cache memory 21 secondary cache memory 21a secondary cache memory 21b secondary cache memory 21c secondary cache memory 22 tertiary cache memory 23 Quaternary cache memory 60 Address bus 61 Address bus 62 Address bus 63 Data bus 65 Data bus 67 Data bus 70 Prefetch suppression circuit 100 Data processing device 100a Data processing device 100b Data processing device 100c Data processing device 101 Primary cache memory 102 2 Next cache memory 103 Main memory 115 Other processing devices

[Procedure amendment]

[Submission date] June 14, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction content]

In this series of processing, if a cache hit (a state in which the requested data is registered in the cache memory) is made in the data read access (105) to the secondary cache memory 102, the requested data ( (Hereinafter referred to as hit data) is the primary cache memory 1
Data processing device 1 after being transferred (111) to 01 and registered
It is transferred (110) to 00. When a cache hit occurs in the data read access (105) to the secondary cache memory 102 as described above, the data read access (106) to the main memory 103 is not performed.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] 0164

[Correction method] Change

[Correction content]

Also, the primary cache memory 10 of this embodiment is
Then, if data that cannot be registered occurs when registering the data transferred directly from the main memory 103 through the line buffer 35, that is, if data is registered on the same line in all four ways, register the data. The data that cannot be transferred is transferred to the output buffer 37 and temporarily held. The data held in the output buffer 37 is output to the data bus 67, and further the bypass path 66, the data bus 65, and the bypass path.
It is transferred to the line buffer 35 of the secondary cache memory 11 via 64 and the data bus 63.

Claims (18)

[Claims] 1. A cache memory of n layers (where n ≧ 2) or more is arranged between a data processing device and a main memory, and the cache memory of the first layer closest to the data processing device is An address bus for data access and a data bus for data transfer are respectively connected to the data processing device and the second-level cache memory, and the n-th level cache memory closest to the main memory is
Another address bus and a data bus are respectively connected to the cache memory of the (n-1) th layer and the main memory, and the cache memory of the mth layer (where 2 ≦ m <n) is,
In a data processing system in which a cache memory of the (m-1) th layer and a cache memory of the (m + 1) th layer are respectively connected to another address bus and a data bus, the mth layer after the second layer (however, (2 ≦ m ≦ n), the cache memory of the (m−1) th hierarchical level stores the access target data if the access target data exists in itself when the data read access request is made from the cache memory of the (m−1) th layer. The data processing system is characterized in that the data to be accessed is transferred to the cache memory of the (m-1) layer and then the access target data existing in itself is invalidated. 2. A cache memory of n layers (where n ≧ 2) or more is arranged between the data processing device and the main memory, and the cache memory of the first layer closest to the data processing device is An address bus for data access and a data bus for data transfer are respectively connected to the data processing device and the second-level cache memory, and the n-th level cache memory closest to the main memory is
Another address bus and a data bus are respectively connected to the cache memory of the (n-1) th layer and the main memory, and the cache memory of the mth layer (where 2 ≦ m <n) is,
In a data processing system in which a cache memory of the (m-1) th layer and a cache memory of the (m + 1) th layer are respectively connected to another address bus and a data bus, a kth layer (where 1≤k≤n ) Cache memory is
At the time of a data read access request from the cache memory of the (k-1) th layer, the presence or absence of a memory space in which data can be registered is detected when the data to be accessed does not exist in all the cache memories of the layers subsequent to itself. When there is a memory space in which data can be registered, the access target data transferred from the main memory is registered, and when there is no memory space in which data can be registered, the registration is prohibited. Data processing system. 3. A cache memory of n layers (where n ≧ 2) or more is arranged between the data processing device and the main memory, and the cache memory of the first layer closest to the data processing device is An address bus for data access and a data bus for data transfer are respectively connected to the data processing device and the second-level cache memory, and the n-th level cache memory closest to the main memory is
Another address bus and a data bus are respectively connected to the cache memory of the (n-1) th layer and the main memory, and the cache memory of the mth layer (where 2 ≦ m <n) is,
In a data processing system in which the cache memory of the (m-1) th layer and the cache memory of the (m + 1) th layer are respectively connected to another address bus and a data bus, the cache memory of the mth layer is -1) When a data read access request is made from the cache memory of the hierarchical level, if the data to be accessed does not exist in all the cache memories of the subsequent layers, the presence / absence of a memory space in which data can be registered is determined as (m-1). When it is detected in a cache memory of a hierarchy or higher and there is no memory space in which data can be registered in the cache memory of the (m-1) th hierarchy or higher, the access target data is registered in itself. And data processing system. 4. A cache memory of n layers (where n ≧ 2) or more is arranged between the data processing device and the main memory, and the cache memory of the first layer closest to the data processing device is An address bus for data access and a data bus for data transfer are respectively connected to the data processing device and the second-level cache memory, and the n-th level cache memory closest to the main memory is
Another address bus and a data bus are respectively connected to the cache memory of the (n-1) th layer and the main memory, and the cache memory of the mth layer (where 2 ≦ m <n) is,
In a data processing system in which a cache memory of the (m-1) th layer and a cache memory of the (m + 1) th layer are respectively connected by another address bus and a data bus, the cache memory of the first layer is the data When the data read access request from the processing device is not present in the access target data, the data read access request is output to the cache memory of the second layer,
If the access target data does not exist in all cache memories of the second and subsequent layers, the access target data transferred from the main memory is registered, and the m-th layer (2 ≦ m ≦) of the second and subsequent layers is registered. In the n) cache memory, in the data read access request from the (m-1) th level cache memory, if the access target data does not exist in itself, the (m + 1) th cache memory
Registration of the access target data transferred from the cache memory of the hierarchy is prohibited, and the cache memory of the kth hierarchy (where 1 ≦ k <n) is
In the series of processes for registering the access target data from the main memory into the cache memory of the first layer, if unregisterable data occurs in the cache memory of the (k-1) th layer, the registration is impossible. A data processing system characterized by registering various data with itself. 5. A cache memory of n layers (where n ≧ 2) or more is arranged between the data processing device and the main memory, and the cache memory of the first layer closest to the data processing device is An address bus for data access and a data bus for data transfer are respectively connected to the data processing device and the second-level cache memory, and the n-th level cache memory closest to the main memory is
Another address bus and a data bus are respectively connected to the cache memory of the (n-1) th layer and the main memory, and the cache memory of the mth layer (where 2 ≦ m <n) is,
In a data processing system in which a cache memory of the (m-1) th layer and a cache memory of the (m + 1) th layer are respectively connected to another address bus and a data bus, the mth layer after the second layer (however, 2 ≦ m ≦ n), the cache memory of the (m−1) th layer, when requesting data read access from the cache memory of the (m−1) th layer, stores the access target data of the first layer when the access target data exists in itself. The series of processes of transferring to the cache memory and registering the access target data from the main memory in the cache memory of the first layer in the cache memory of the (k−1) th layer (where 1 ≦ k <n) At this time, if unregisterable data occurs in itself, the unregisterable data is transferred to the cache memory of the kth layer, Data processing system, wherein the cache memory layers, where a said registration impossible data are no order to register only if that does not exist in itself. 6. A cache memory of n layers (where n ≧ 2) or more is arranged between the data processing device and the main memory, and the cache memory of the first layer closest to the data processing device is An address bus for data access and a data bus for data transfer are respectively connected to the data processing device and the second-level cache memory, and the n-th level cache memory closest to the main memory is
Another address bus and a data bus are respectively connected to the cache memory of the (n-1) th layer and the main memory, and the cache memory of the mth layer (where 2 ≦ m <n) is,
In a data processing system in which a cache memory of the (m-1) th layer and a cache memory of the (m + 1) th layer are respectively connected to another address bus and a data bus, the mth layer after the second layer (however, 2 ≦ m ≦ n), the cache memory of the (m−1) th layer, when the data read access request is issued from the cache memory of the (m−1) th layer, stores the access target data of the first layer in the first layer. The cache memory of the (k−1) th layer (where 1 ≦ k <n) is transferred to the cache memory and is not registered during the series of processes of registering the access target data in the cache memory of the first layer. When possible data is generated in itself, the unregisterable data is transferred to the cache memory of the kth layer, and the key of the kth layer is transferred. Sshumemori a data processing system, wherein the registration impossible data are no order to register on the partial access target data is present only if that does not exist in itself. 7. A cache memory of n layers (where n ≧ 2) or more is arranged between the data processing device and the main memory, and the cache memory of the first layer closest to the data processing device is An address bus for data access and a data bus for data transfer are respectively connected to the data processing device and the second-level cache memory, and the n-th level cache memory closest to the main memory is
Another address bus and a data bus are respectively connected to the cache memory of the (n-1) th layer and the main memory, and the cache memory of the mth layer (where 2 ≦ m <n) is,
In a data processing system in which a cache memory of a (m-1) th layer and a cache memory of a (m + 1) th layer are respectively connected to another address bus and a data bus, the cache memory of the first layer is the data processing unit. When a data read access request is issued from the device, if the access target data does not exist in itself, the data read access request is output to the cache memory of the second layer, and the access target data is also stored in all the cache memories of the second and subsequent layers. If it does not exist, the access target data transferred from the main memory is registered, and the cache memory of the m-th layer (2 ≦ m ≦ n) after the second layer is (m−1) th layer. When requesting a data read access from the cache memory, the access target data is stored in itself. If no standing the (m + 1) -th
Registration of the access target data transferred from the memory of the hierarchy is prohibited, and the cache memory of the kth hierarchy (where 1 ≦ k <n) is
In the series of processes of registering the access target data from the main memory into the first layer cache memory, if unregisterable data occurs in the (k-1) th layer cache memory, the registration is impossible. Data is registered in itself, and the cache memory in the m-th layer (2 ≦ m ≦ n) after the second layer is accessed when a data read access request is made from the cache memory in the (m−1) -th layer. When the target data exists in itself, the access target data is transferred to the (m-1) th level cache memory, and then the access target data existing in itself is invalidated. A data processing system characterized by the above. 8. A cache memory of n layers (where n ≧ 2) or more is arranged between the data processing device and the main memory, and the cache memory of the first layer closest to the data processing device is An address bus for data access and a data bus for data transfer are respectively connected to the data processing device and the second-level cache memory, and the n-th level cache memory closest to the main memory is
Another address bus and a data bus are respectively connected to the cache memory of the (n-1) th layer and the main memory, and the cache memory of the mth layer (where 2 ≦ m <n) is,
In a data processing system in which a cache memory of a (m-1) th layer and a cache memory of a (m + 1) th layer are respectively connected to another address bus and a data bus, the cache memory of the first layer is the data processing unit. When a data read access request is issued from the device, if the first data to be accessed does not exist in itself, the data read access request is output to the cache memory of the second layer, and the cache memory of the second layer and subsequent layers also receives the data read access request. When the first target data does not exist, the first data transferred from the main memory is registered, and the cache memory of the m-th layer (2 ≦ m ≦ n) after the second layer is At the time of a data read access request for the first data from the (m-1) layer cache memory, the first data is accessed. The If the data does not exist in itself (m + 1) the transferred from the hierarchy of the memory first
The registration of the data of the above is prohibited, and the cache memory of the kth layer (where 1 ≦ k <n) is
In the series of processes for registering the first data from the main memory into the cache memory of the first layer, the second register that cannot be registered in the cache memory of the (k-1) th layer.
Register the second data to itself, and the cache memory of the m-th layer (2 ≦ m ≦ n) after the second layer is the cache of the (m−1) -th layer. At the time of a data read access request from the memory, if the third data to be accessed exists in itself, the third data is transferred to the cache memory of the (m-1) th layer, and then to the self. The existing third data is invalidated, and the cache memory of the kth layer (where 1 ≦ k <n) is
In the series of processing for registering the third data in the cache memory of the first layer, if unregisterable fourth data occurs in the cache memory of the (k-1) th layer, the fourth data A data processing system characterized in that it is designed to register data with itself. 9. A cache memory of n layers (where n ≧ 2) or more is arranged between the data processing device and the main memory, and the cache memory of the first layer closest to the data processing device is An address bus for data access and a data bus for data transfer are respectively connected to the data processing device and the second-level cache memory, and the n-th level cache memory closest to the main memory is
Another address bus and a data bus are respectively connected to the cache memory of the (n-1) th layer and the main memory, and the cache memory of the mth layer (where 2 ≦ m <n) is,
In a data processing system in which a cache memory of a (m-1) th layer and a cache memory of a (m + 1) th layer are respectively connected to another address bus and a data bus, the cache memory of the first layer is the data processing unit. When a data read access request is issued from the device, if the first data to be accessed does not exist in itself, the data read access request is output to the cache memory of the second layer, and the cache memory of the second layer and subsequent layers also receives the data read access request. When the first target data does not exist, the first data transferred from the main memory is registered, and the cache memory of the m-th layer (2 ≦ m ≦ n) after the second layer is At the time of a data read access request for the first data from the (m-1) layer cache memory, the first data is accessed. The If the data does not exist in itself (m + 1) the transferred from the hierarchy of the memory first
The registration of the data of the above is prohibited, and the cache memory of the kth layer (where 1 ≦ k <n) is
In the series of processes for registering the first data from the main memory into the cache memory of the first layer, the second register that cannot be registered in the cache memory of the (k-1) th layer.
Register the second data to itself, and the cache memory of the m-th layer (2 ≦ m ≦ n) after the second layer is the cache of the (m−1) -th layer. At the time of a data read access request from the memory, if the third data to be accessed exists in itself, the third data is transferred to the cache memory of the (m-1) th layer, and then to the self. The existing third data is invalidated, and the k-th layer cache memory registers the (k−1) th data in the series of processes for registering the third data in the first-layer cache memory. Hierarchy (however, 1 ≦ k <
n) When the unregisterable fourth data is generated in the cache memory, the fourth data is to be registered in the portion where the third data existed. Data processing system. 10. A cache memory of n layers (where n ≧ 2) or more is arranged between the data processing device and the main memory, and all the cache memories are for accessing the data processing device for data access. An address bus and a data bus for data transfer are connected, and the cache memory of the nth layer closest to the main memory is
In a data processing system in which another address bus and a data bus are connected to the main memory, the cache memory of the first layer has no access target data in itself when a data read access request is made from the data processing device. In this case, the data read access request is output to the second level cache memory,
If the access target data does not exist in all the cache memories of the second and subsequent layers, the access target data directly transferred from the main memory is registered, and the m-th layer (2 ≦ m) of the second and subsequent layers is registered. The cache memory of ≦ n) does not fetch the data for the request when the data read access request from the cache memory of the (m−1) th layer does not exist in itself when the access target data does not exist in the cache memory of the kth layer. (However, 1≤k <n)
In the series of processes for registering the access target data from the main memory into the cache memory of the first layer, if unregisterable data occurs in the cache memory of the (k-1) th layer, the registration is impossible. A data processing system characterized by registering various data with itself. 11. A cache memory of n layers (where n ≧ 2) or more is arranged between the data processing device and the main memory, and the cache memory of the first layer closest to the data processing device is An address bus for data access and a data bus for data transfer are respectively connected to the data processing device and the main memory, and the nth hierarchical cache memory closest to the main memory is
The cache memory of the (n-1) th layer is connected to another address bus and a data bus, and the cache memory of the mth layer (where 2 ≦ m <n) is
In a data processing system in which a cache memory of the (m-1) th layer and a cache memory of the (m + 1) th layer are respectively connected by another address bus and a data bus, the cache memory of the first layer is the data When the data read access request from the processing device is not present in the access target data, the data read access request is output to the cache memory of the second layer,
If the access target data does not exist in all the cache memories of the second and subsequent layers, the access target data directly transferred from the main memory is registered, and the m-th layer (2 ≦ m) of the second and subsequent layers is registered. The cache memory of ≦ n) does not fetch the data for the request when the data read access request from the cache memory of the (m−1) th layer does not exist in itself when the access target data does not exist in the cache memory of the kth layer. (However, 1≤k <n)
In the series of processes for registering the access target data from the main memory into the cache memory of the first layer, if unregisterable data occurs in the cache memory of the (k-1) th layer, the registration is impossible. A data processing system characterized by registering various data with itself. 12. A cache memory of n levels (where n ≧ 2) or more is arranged between a data processing device and a main memory, and all the cache memories are for accessing the data processing device for data access. An address bus and a data bus for data transfer are connected, and the cache memory of the first layer closest to the data processing device is a data processing device which is connected to the main memory by another address bus and a data bus. In the system, the first level cache memory outputs the data read access request to the second level cache memory when the data read access request from the data processing device does not exist in itself,
If the access target data does not exist in all the cache memories of the second and subsequent layers, the access target data directly transferred from the main memory is registered, and the m-th layer (2 ≦ m) of the second and subsequent layers is registered. The cache memory of ≦ n) does not fetch the data for the request when the data read access request from the cache memory of the (m−1) th layer does not exist in itself when the access target data does not exist in the cache memory of the kth layer. (However, 1≤k <n)
In the series of processes for registering the access target data from the main memory into the cache memory of the first layer, if unregisterable data occurs in the cache memory of the (k-1) th layer, the registration is impossible. A data processing system characterized by registering various data with itself. 13. A cache memory of n layers (where n ≧ 2) or more is arranged between the data processing device and the main memory, and the cache memory of the first layer closest to the data processing device is An address bus for data access and a data bus for data transfer are respectively connected to the data processing device and the second-level cache memory, and the n-th level cache memory closest to the main memory is
Another address bus and a data bus are respectively connected to the cache memory of the (n-1) th layer and the main memory, and the cache memory of the mth layer (where 2 ≦ m <n) is,
In a data processing system in which a cache memory of the (m-1) th layer and a cache memory of the (m + 1) th layer are respectively connected by another address bus and a data bus, the cache memory of the first layer is the data When the data read access request is issued from the processing device, if the first data to be accessed does not exist in itself, the first data transferred from the main memory is registered, and the second cache of the second and subsequent layers is registered. In the data read access from the first cache memory of the upper layer, the memory performs a data read access to the second data to the third cache memory of the lower layer when the second data to be accessed does not exist in itself. A request and a data read access request for third data that follows the second data Data processing system wherein the output is, without writing the second data to be transferred from the main memory, that is no order to register the third data transferred from the main memory. 14. A cache memory of n layers or more (where n ≧ 1) is provided between a data processing device and a main memory, and at least one of the cache memories is a first access target when a data read access request is made. If the data of No. 1 does not exist in itself, a read access request for the first data is issued to the cache memory in the lower layer or the main memory, and a data read access request from the cache memory in the upper layer or the data processing device is issued. In the data processing system, which does not exist, the second data existing in the vicinity of the first data is read-accessed to the cache memory of the lower hierarchy or the main memory. Prefetch suppression for determining whether to perform a read access to data 2 Data processing system comprising the circuit. 15. A data processing system comprising an n (where n ≧ 2) data processing devices and a main memory with m or more hierarchical levels (where m ≧ 2) cache memory, wherein the i-th ( However, the 1st-tier cache memory of the i-th series closest to the data processing device of 1 ≦ i ≦ n) is the i-th
No. 2 data processor and the i-th series second layer cache memory are connected by an address bus for data access and a data bus for data transfer. The cache memory is
The (m-1) th level cache memory and the main memory are connected to other address buses and data buses, and the i-th series kth level (where 2 ≦ k <m) cache memory is , The i-th series (k-1) -th cache memory and the j-th series (where 1≤j≤n) 1-th hierarchy (where 2≤l <m-1) cache memory and the (k +) th cache memory.
1) The cache memory of the hierarchy is connected to another address bus and a data bus, and the cache memory of the p-th hierarchy (where 2 ≦ p <m, p ≠ k) is the (p−1) -th hierarchy. Cache memory and the (p
In a data processing system in which a cache memory of +1) layer is connected to another address bus and a data bus, the cache memory of the first layer is such that the access target data itself is the data read access request from the data processing device. If it does not exist, the access target data transferred from the lower layer cache memory or the main memory is registered, and the kth layer cache memory registers the data read access request from the upper layer cache memory,
When the access target data does not exist in itself, the access target data transferred from the lower layer cache memory or the main memory is registered, and the p-th layer cache memory stores the data read access from the upper layer cache memory. At this time, if the access target data does not exist in itself, the access target data transferred from the cache memory in the lower hierarchy or the main memory is not registered. 16. A data processing system comprising an n (where n ≧ 2) data processing devices and a main memory with m or more (where m ≧ 2) cache memories between the data processors and the i-th ( However, the 1st-tier cache memory of the i-th series closest to the data processing device of 1 ≦ i ≦ n) is the i-th
No. 2 data processor and the i-th series second layer cache memory are connected by an address bus for data access and a data bus for data transfer. The cache memory is
The (m-1) th level cache memory and the main memory are connected to other address buses and data buses, and the i-th series kth level (where 2 ≦ k <m) cache memory is , The i-th series (k-1) -th cache memory and the j-th series (where 1≤j≤n) 1-th hierarchy (where 2≤l <m-1) cache memory and the (k +) th cache memory.
1) The cache memory of the hierarchy is connected to another address bus and a data bus, and the cache memory of the p-th hierarchy (where 2 ≦ p <m, p ≠ k) is the (p−1) -th hierarchy. Cache memory and the (p
In a data processing system in which a cache memory of +1) layer is connected to another address bus and a data bus, in the cache memory of the first layer, when the data read access request is made from the data processing device, the access target data is When it exists in itself, it outputs the access target data to the data processing device, and the cache memory of the k-th layer is a data read access request from the cache memory of an upper layer,
When the access target data exists in itself, the access target data is output to the data processing device or the cache memory of the upper layer, and the cache memory of the p-th layer, in the data read access from the cache memory of the upper layer, If the access target data exists in itself, the access target data is output to the data processing device or the cache memory of the upper layer, and then the access target data existing in itself is invalidated. Characteristic data processing system. 17. A cache memory of n layers (where n ≧ 2) or more is provided between the data processing device and the main memory, and the cache memory of the first layer closest to the data processing device is the data processing device. And a second level cache memory are connected to each other by an address bus for data access and a data bus for data transfer. The nth level cache memory closest to the main memory is
The (n-1) th level cache memory and the main memory are connected to other address buses and data buses, and the mth level (where 2 ≦ m <n) cache memory is
In a data processing system in which a cache memory of the (m-1) th layer and a cache memory of the (m + 1) th layer are connected to another address bus and a data bus, the cache memory of the first layer is the data processing unit. When a data read access request is issued from the device, if the access target data does not exist in itself, the access target data transferred from the lower level cache memory or the main memory is registered, and the mth level cache memory In the data read access from the cache memory of the hierarchy, if the access target data does not exist in itself, the access target data transferred from the cache memory of the lower hierarchy or the main memory is not registered, and the cache memory of the upper hierarchy is not registered. The data that was created to register the write data In the data processing system, when the data processing device or a device other than the cache memory rewrites data in the main storage device, the cache memory of the n-th layer (where 2 ≦ m <n) is -1) If the data is not registered in the cache memory of the hierarchy, it is searched whether the first data is registered in the cache memory of the nth hierarchy,
If not registered, the cache memory of the (m + 1) th layer of the next stage is searched for the first data, and
A data processing system, wherein when the first data is registered in the cache memory of the hierarchy, the cache memory of the (m + 1) th hierarchy of the next stage is not searched for the first data. . 18. A cache memory of n layers (where n ≧ 2) or more is provided between the data processing device and the main memory, and the cache memory of the first layer closest to the data processing device is the data processing device. And a second level cache memory are connected to each other by an address bus for data access and a data bus for data transfer. The nth level cache memory closest to the main memory is
The (n-1) th level cache memory and the main memory are connected to other address buses and data buses, and the mth level (where 2 ≦ m <n) cache memory is
The cache memory of the (m-1) th layer and the cache memory of the (m + 1) th layer are connected to each other by another address bus and a data bus, and the cache memory of the first layer is the data from the data processing device. At the time of a read access request, if the data to be accessed does not exist in itself, the data transferred from the cache memory of the lower layer or the main memory is registered. In the data read access, if the data to be accessed does not exist in itself, the data transferred from the cache memory of the lower layer or the main memory is not registered, but the write data from the cache memory of the upper layer is registered. In a data processing system, the data processing device or When a device other than the cache memory rewrites the data in the main storage device, the cache memory of the nth layer (where 2 ≦ m <n) is stored in the cache memory of the (m−1) th layer. Is registered, the cache memory of the nth layer is searched for the data. If not registered, the cache memory of the (m + 1) th layer of the next stage is searched for the data, and A data processing system, wherein when the data is registered in the cache memory of the mth layer, the cache memory of the (m + 1) th layer of the next stage is not searched for the data.