JPH06245203A - Coder for digital video signal - Google Patents

Abstract

PURPOSE:To utilize effectively a data transmission period by coding a digital video signal at a high compression rate and controlling adaptively bit allocation to two frame data when the data quantity of a coded output is made constant for each prescribed period. CONSTITUTION:The difference between an input frame P and a frame I generated by a local decoder is detected by a subtractor circuit 23, its absolute value is integrated for each block and an integrated output Ef is compared with two threshold levels Th1, Th2 at a comparator circuit 26. Data transmission of a block having a relation of Ef<=Th1 is omitted, and difference data of blocks having a relation of Th1<Ef<Th2 are subjected to DC transformation and processing of variable length coding. Blocks having the relation of Ef>=Th2 are subjected to in-frame coding processing. Since three modes are in existence as coding results of the frame P, the quantity of data generated from the frame P is fluctuated. Since the quantity of data generated from the frame P is less, data of excess blocks are added to data from the frame I and then bit allocation data T-B and B to the two frames are generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video signal coding apparatus applied to compression-coding a digital video signal.

[0002]

2. Description of the Related Art A digital VTR for recording a digital video signal on a magnetic tape by a rotary head is known. Since the amount of information in a digital video signal is large,
High-efficiency coding for compressing the amount of transmitted data is often adopted. Among various high efficiency coding, DC
Practical application of T (Discrete Cosine Transform) is progressing.

In the DCT, one frame image is converted into, for example, (8
X8) is converted into a block structure, and this block is subjected to cosine transform processing which is a kind of orthogonal transform. As a result, (8 × 8) coefficient data is generated. Such coefficient data is transmitted after being subjected to variable-length coding processing such as run-length coding and Huffman coding. At the time of transmission, in order to facilitate data processing on the reproducing side, a code signal, which is an encoded output, is inserted into the data area of a sync block of a certain length, and a sync signal, I
The sync block to which the D signal is added is framed.

A digital VTR using a magnetic tape,
In a disc recording device or the like using a disc-shaped recording medium, it is usual that one field or one frame of video data is recorded on a plurality of tracks. However, when a variable length output is formed as in the DCT described above, there is a problem that the amount of data in these predetermined periods fluctuates, which makes editing in field or frame units troublesome. For this reason, fixed lengthening processing (referred to as buffering processing) is performed to reduce the amount of data in the predetermined period to the target value or less. The predetermined period may be one field and one frame, but in order to reduce the required memory capacity, the data amount in a shorter period (referred to as a buffering unit) is controlled, resulting in one field and one frame.
The amount of frame data is fixed.

[0005]

For standard resolution video signals (referred to as SD-H signals) such as the 525/60 system, the transmission rate of the recording / reproducing data is set to 25 MBPS, for example. If this transmission rate could be halved to 12.5 MBPS, the amount of tape consumed could be halved. For example, at a predetermined track pitch, two rotary heads alternately form tracks, whereas the tape speed can be halved and only one rotary head can form tracks. Further, the high resolution video signal (referred to as HD signal) is S
Since the number of pixels in the horizontal direction is about twice and the number of horizontal scanning lines is about twice that of the D-H signal, the amount of information is four times that of the SD signal. In order to record / reproduce such an HD signal, it is desirable to perform encoding with a compression rate as high as possible.

As one of the methods for increasing the compression rate,
A method is known in which intra-frame coding is performed every 10 to 15 frames and the frame difference is coded for the remaining frames. However, in the case of a digital VTR, since it is necessary to edit in a shorter frame,
Encoding in units of such many frames is inappropriate. If the intra 2 frames are encoded, editing can be performed in units of 2 frames. In the above-described fixed length of the encoded output data amount, the buffering process is performed for the period of two frames.

Therefore, an object of the present invention is to provide a digital video signal coding apparatus which can achieve a high compression rate and can perform a good buffering process.

[0008]

The invention according to claim 1 is
An encoding device for compressing the amount of data of an input digital video signal, which is an orthogonal transform circuit for transform encoding for each encoding block of a predetermined size, and a fixed length by combining with an orthogonal transform circuit. In order to fit the encoded output data amount within a unit within the data area of multiple sync blocks,
An adaptive quantizing circuit for controlling, a variable length coding circuit coupled to the adaptive quantizing circuit, a framing circuit for making the output of the variable length coding circuit into transmission data of a sync block configuration, A circuit for locally decoding the output of the quantization circuit, a frame memory for storing the locally decoded data, decoded data of the first frame from the frame memory, and a second frame following the first frame. A frame difference between the coding blocks is detected for each coding block, and the coding block is classified into a first class in which the frame difference is smaller than a threshold value and a second class in which the frame difference is larger than the threshold value. For the first class coding block, the frame difference is given to the orthogonal transformation circuit, and for the second class coding block, the second frame data is transformed to the orthogonal transformation circuit. And an encoding control circuit for controlling bit allocation for the encoded output of the first frame and the encoded output of the second frame within the fixed length unit in response to the classification information. An encoding device for a digital video signal, which comprises:

According to a fifth aspect of the present invention, there is provided an encoding device for compressing the data amount of an input digital video signal, which comprises an orthogonal transformation circuit for performing transformation coding for each coding block of a predetermined size. , Coupled with an orthogonal transformation circuit, and coupled with an adaptive quantization circuit for controlling the data amount of the encoded output in the fixed length unit so that the data amount of the coded output is within the data area of a plurality of sync blocks, and the adaptive quantization circuit Variable length coding circuit, a framing circuit for converting the output of the variable length coding circuit into transmission data having a sync block configuration, a circuit for locally decoding the output of the adaptive quantization circuit, and a local decoding A frame memory for storing the stored data, the decoded data of the first frame from the frame memory and the first
Frame difference between the second frame and the second frame subsequent to the frame is detected for each coding block, and a first class in which the frame difference is smaller than a threshold and a second class in which the frame difference is larger than the threshold are detected. The coding blocks are divided into classes, the frame difference is given to the orthogonal transformation circuit for the first class coding blocks, and the data of the second frame is transformed to the orthogonal transformation circuit for the second class coding blocks. And a bit allocation for the coded output of the first frame and the coded output of the second frame within the fixed length unit is adaptively controlled in response to the classification information. And a coding control circuit for selectively controlling a second mode in which bit allocation is a fixed ratio in consideration of scene changes and the like. An encoding device Deo signal.

[0010]

When the data amount generated by the encoding of the intra 2 frames is fixed length, the generated data amount of the second frame is predicted within the fixed length unit and the allocation to the second frame is performed according to the prediction result. Determine the amount of data. The remaining amount of data in the fixed length unit is assigned to the first frame. When the data amount of the encoded output of the second frame is small, the number of bits of a predetermined value or more is assigned to the first frame. In this way, the data transmission period can be effectively used.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a digital VTR will be described below with reference to the drawings. FIG. 1 shows the configuration of a video data processing circuit provided on the recording side of a digital VTR. In FIG. 1, a digital video signal is supplied to the input terminal indicated by 1. This digital video signal is supplied to the preprocessing circuit 2, and the output signal of the preprocessing circuit 2 is supplied to the blocking and shuffling circuit 3. The preprocessing circuit 2 is a thinning filter, a line-sequentializing circuit, or the like provided to reduce the data rate. In the blocking and shuffling circuit 3,
If the video data in the interlaced scanning order is (8 ×
8) Blocking processing that is converted into data of the block (DCT block) structure and processing that makes the spatial position of video data different from the original within one frame, that is, shuffling is performed. .

The output of the blocking and shuffling circuit 3 is supplied to the subtraction circuit 4, and the output signal of the subtraction circuit 4 is D
It is supplied to the CT (cosine transform) circuit 5. From the DCT circuit 5, (8 × 8) coefficient data (that is, the DC component D
C, AC component AC coefficient data) is generated. DC component DC of (8 × 8) coefficient data generated in the DCT circuit 5
Is transmitted to the circuit at the subsequent stage without being compressed, and 63 of the alternating current components are supplied to the adaptive quantization circuit 6.

The alternating current coefficient data is transmitted in order of zigzag scanning from the low order alternating current to the high order alternating current. Further, the coefficient data for the alternating current is supplied to the data amount estimating device 7. The quantization number QNo corresponding to the quantization step from the estimator 7 is supplied to the quantization circuit 6 and inserted into the recording data.

In the quantizing circuit 6, the AC component in the coefficient data is quantized. That is, the coefficient data for the alternating current is divided by an appropriate quantization step, and the quotient is converted into an integer.
This quantization step is the quantization number QN from the estimator 7.
determined by o. The amount of data generated by DCT and variable-length coding varies depending on the pattern to be coded. Therefore, a buffering process for reducing the amount of generated data in a buffering unit shorter than one field or one frame period to a target value or less. Is done. The reason for shortening the buffering unit is to simplify the buffering circuit, such as reducing the memory capacity for buffering. In this example, the predetermined period (buffering unit)
The quantization step is controlled so that the data generated in step 5 can be contained within 5 sync blocks.

The output of the quantization circuit 6 is the variable length coding circuit 8
And run-length coding, Huffman coding, etc. are performed. For example, the run length, which is the number of consecutive "0" s of coefficient data, and the value of coefficient data are given to a Huffman table stored in the ROM, and a variable length code (encoded output) is given.
Two-dimensional Huffman coding is used to generate The code signal from the variable length coding circuit 8 is supplied to the subsequent stage. The estimator 7 has the same Huffman table as that referred to by the variable length coding circuit 8. This Huffman table generates bit number data of an output code when variable length coding is performed. The estimator 7 determines the optimum quantization step, and the quantization circuit 6 quantizes the coefficient data at this quantization step.

The DCT circuit 5, the adaptive quantization circuit 6, the estimator 7 and the variable length coding circuit 8 in FIG. 1 have a basic configuration, and a process for distinguishing a DCT transform between a still block and a motion block. , A process of varying the quantization step of coefficient data according to the definition (activity) of the block, a process of varying the quantization step according to the order of the coefficient data, a process of parallelizing the encoding of the HD signal, etc. . The result of motion detection (motion flag) and the activity code for identifying the activity are also recorded.

The data (DC component data, variable length coded output, quantization number QNo, motion flag, activity code) generated by the above-described coding process is supplied to the framing circuit 9 in the subsequent stage. In the framing circuit 9, error correction coding processing, conversion processing of recording data into a frame structure, and track shuffling are performed. Recording data appears at the output terminal of the framing circuit 9. The recording data is supplied to the rotary head via the channel encoding circuit and the recording amplifier and recorded on the magnetic tape.

According to the present invention, intra 2 frame coding is performed in order to increase the compression rate. That is, the pair POP of the first frame I and the second frame P that are temporally consecutive is the target of encoding. A pair of a block included in the first frame I and a block included in the second frame P and located at the same position as the block of the frame I is an encoding unit. The block of the first frame I is D as described above.
It is compressed by CT and variable length coding processing. A difference is calculated for each pixel between the locally decoded output regarding the first frame and the video data regarding the second frame, and the absolute value of this difference is integrated for each block. The coding of the block of the second frame P is adaptively controlled according to the magnitude of this integrated value. Usually, there is an image correlation between the first frame and the second frame, and the value of the inter-frame difference is small. When this frame difference is DCT and variable length coded, the data amount of the coded output is smaller than that when the original data is coded and output.

In FIG. 1, an inverse quantization circuit 10 connected to the adaptive quantization circuit 6 and an inverse DCT circuit 11 connected to the inverse quantization circuit 10 form a local decoding circuit. The locally decoded data of the first frame I is stored in the frame memory 12. The video data of the second frame P and the decoded data read from the frame memory 12 and passed through the gate circuit 13 are subtracted by the subtraction circuit 4.

The gate circuit 13 is turned on / off by a control signal generated by the encoding control circuit 14. Both the input video data and the data from the frame memory 12 are supplied to the encoding control circuit 14. The coding control circuit 14 also has a function of controlling the number of bits assigned to the frame I and the number of bits assigned to the frame P in the fixed length unit. The bit allocation information is stored in the memory 15. The bit allocation information generated by the current POP is
It is temporarily stored in the memory 15 and applied to the next POP.

In addition, in intra 2 frame encoding, when a scene change occurs, the correlation between the first and second frames disappears, and the data amount of encoded output can be reduced.
In some cases, the amount of data will rather increase. The scene change is detected by the detection circuit 16, and the detection result is supplied to the estimator 7. A frame difference between two temporally consecutive frames of the input video signal is detected, and when the frame difference is large to some extent, it is determined that a scene change has occurred. It is not necessary to detect the frame difference of the entire screen, but the frame difference of several lines may be detected.

An example of the encoding control circuit 14 will be described with reference to FIG. The data of the frame I is supplied to the input terminal 21, and the locally decoded data of the frame P is supplied to the input terminal 22. The subtraction circuit 23 subtracts the data of both frames for each pixel to generate a frame difference. An absolute value conversion circuit 24 is connected to the subtraction circuit 23. The frame difference converted into the absolute value is the integrating circuit 25.
And the absolute value of the frame difference for one block is integrated.

The output Ef of the integrating circuit 25 is supplied to the comparing circuit 26. The threshold values Th1 and Th2 (Th1 <Th2) are also supplied to the comparison circuit 26. Comparison circuit 26
Generates a 2-bit flag (classification information) according to the magnitude relationship between Ef and Th1 and Th2. That is,
Blocks with Ef ≦ Th1 are divided into class NONE,
The block of Th1 <Ef <Th2 is divided into the class PRED, and the block of Ef ≧ Th2 is divided into the class INTRA.

This flag is taken out to the output terminal 27. ON / OFF of the gate circuit 13 of FIG. 1 is controlled by the flag. In the case of class NONE, the gate circuit 13 may be on or off. Class NO
The NE block is a block having a small integrated output Ef, that is, a block having a small frame difference. Typically, in the case of a still image, Ef = 0 except noise. Recording is omitted in the blocks of the frame P belonging to the class NONE. On the reproducing side, the decoded data of the block of the other frame I of the pair POP is used again as the block of the frame P.

In the block of class PRED, the integrated output Ef of the absolute value of the frame difference exists to some extent. In this block, the gate circuit 13 is turned on.
Therefore, the frame difference generated by the subtraction circuit 4 in FIG.
CT, variable length coding. A block of class PRED is a block that receives intra 2 frame processing.
For blocks of class INTRA, gate circuit 1
3 is turned off, and the data itself of the frame P is generated from the subtraction circuit 4. Therefore, frame P of class INTRA
Data is subjected to intra-frame encoding processing. The class INTRA is a class in which the correlation between frames is small and improvement of the compression rate cannot be expected even if the difference data is encoded.

The flag indicating the above classification information is also used to determine the bit allocation in the fixed length unit. This embodiment is for recording / reproducing a standard-definition component video signal.
The data amount is controlled so that the sum of the coded data amount of the macroblock and the coded data amount of the 5 macroblocks of the frame P at the same position as this is equal to or less than a predetermined target bit number. ing. The target number of bits is 5
This is the amount of data that can be inserted into each sync block. Here, the macroblock is a processing unit having a size of 6 blocks, that is, 4 blocks of the Y signal and 2 blocks of the color difference signal when each component of the component video signal is divided into blocks. Therefore, 5 macroblocks are 30 blocks.

FIG. 3 illustrates this process, 5+
The target number of bits of the data amount of 5 = 10 macroblocks (buffering unit) is represented by T. It is controlled how to assign the target number of bits T to the coded data of the 5 macroblocks of the frame I and the coded data of the 5 macroblocks of the frame P. The bit allocation modes are PRE, FIX, and SCH.
There are 3 modes. As shown in FIG. 4, in PRE, TB (bit) is assigned to the frame I and B (bit) is assigned to the frame P. However, TB is (3/4) T or more. FIX
In, the bit allocation for each of the frame I and the frame P is fixed to T × (3/4) and T / 4. In the SCH, the bit allocation for each of the frame I and the frame P is fixed to T / 2 and T / 2.

A mode PRE in which bit allocation is adaptively controlled will be described. In this mode, at least (3/4) T is assigned to the frame I as described above. Therefore, the remaining T / 4 is the number of bits allocated to the frame P. Since the amount of generated data in the frame P is smaller than that in the frame I, the standard of the number of allocated bits is set in this way. Further, the encoding of the frame P, as described above,
There are three classes (NONE, PRED, INTRA), and as a result, the amount of encoded data of 5 macroblocks is not constant. As an extreme example, if all 5 macroblocks are in the NONE class, the amount of generated data is 0.
Is. Therefore, frame P may not require T / 4 even though the bit allocation for frame P is less than that for frame I. In that case, the number of bits of margin generated is added to (3/4) T for frame I. The increase in the number of bits allocated for the frame I is advantageous for improving the image quality of the decoded image of the frame I.

The adaptive allocation control is performed by the coding control circuit 14. As shown in FIG. 2, the flag is supplied to the slice number generation circuit 28, and the number of slices corresponding to the flag indicating the classification information is generated from the circuit 28. A slice is a unit of data amount introduced for adaptive control of bit allocation, and for example, T / 4 is 30
The number of bits equally divided is selected for one slice. The slice number generation circuit 28 has 0 slices for the NONE class, 2 slices for the PRED class, and INTRA.
3 slices are generated for each class. The number of slices is an example determined based on statistical and empirical grounds.

The output signal of the slice number generating circuit 28 is supplied to an integrating circuit 29 and integrated for 5 macroblocks (= 30 blocks). The clipping circuit 30 is connected to the integrating circuit 29. The clipping circuit 30 clips the integrated number of slices by 30 (= T / 4). A data conversion circuit 31 is connected to the clip circuit 30. The data conversion circuit 31 converts the number of slices into the number of bits. Data of the number of bits B allocated to the frame P is generated from the data conversion circuit 31 to the output terminal 32. In the arithmetic circuit 33, the calculation of T-B is performed, and the data of the number of bits T-B allocated to the frame I is generated at the output terminal 34.

The bit allocation data generated in this way is stored in the memory 15 in FIG. The two-frame pair POP includes, for example, 270 buffering units. As described above, 270 pieces of bit allocation information determined for each buffering unit are stored in the memory 1
Stored in 5. The bit allocation data of the memory 15 is read at the time of the next POP encoding process, and the estimation unit 7
Is supplied to. The estimator 7 refers to the bit allocation data of each buffering unit to perform the buffering process. Bit allocation information represented by the number of slices instead of the number of bits may be stored in the memory 15.

The bit allocation information determined by the previous POP data cannot be used in the two frames and the scene change at the time of starting the encoding. Therefore,
The three bit allocation modes shown in FIG. 4 are prepared, and the mode is selected according to the case. Prediction mode (PRE) is
This is the above-mentioned adaptive control mode, which is the normal mode. When encoding is started, the fixed (FIX) mode is selected. In this mode, for frame I (3 /
4) T (bits) are allocated, and (T / 4) is allocated to the frame P.

FIG. 5 is for explaining the bit allocation mode. F1, F2, F3, ... Represent frames, and Fi and Fi + 1 (i = 1, 3, 5, ...). ) And, a two-frame pair POP is formed. The FIX mode is adopted in the frames F1 and F2 in which encoding is started. Scene changes occur in two cases shown in FIGS. 5A and 5B, respectively. In the example of FIG. 5A, PO
A scene change occurs between P frames, and in the example of FIG. 5B, a scene change occurs between the POP and the next POP. In the case of FIG. 5A, the bit allocation mode for the POP in which the scene change has occurred is SCH. This is a mode in which the bit allocation is T / 2 each. In the case of FIG. 5B, this is equivalent to the case of the start of encoding, and therefore the POP mode after the scene change is set to FIX.

The scene change detection circuit 16 detects each of these two scene changes and gives the detection result to the estimator 7. The estimator 7 has a function of generating bit allocation data of the mode FIX or SCH in response to the detection result and using this bit allocation data instead of the data of adaptive allocation from the memory 15.

By the above encoding, D within one frame
The data rate can be halved to 12.5 Mbps as compared with the case of CT and variable length coding. In the above example, the difference is calculated between blocks at the same location in frames I and P, but it is also possible to calculate the difference after motion compensation. This allows a higher compression rate.

[0036]

Since the present invention employs intra 2 frame encoding, the compression rate can be made higher than that of intra 1 frame, and editing in units of 2 frames is possible. Is. Since the present invention adaptively controls the bit allocation for two frames in the buffering unit in order to control the amount of generated data between two frames, the efficiency can be improved within the limited interval represented by the target number of bits. It is possible to stuff the encoded data in a physical manner.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of an encoding circuit of a digital VTR.

FIG. 2 is a block diagram of an example of an encoding control circuit.

FIG. 3 is a schematic diagram for explaining adaptive control of bit allocation for encoded outputs of two frames.

FIG. 4 is a schematic diagram used to describe a bit allocation mode.

FIG. 5 is a schematic diagram used to explain selection of a bit allocation mode.

[Explanation of symbols]

 4 Subtraction circuit 5 DCT circuit 6 Adaptive quantization circuit 7 Estimator 13 Gate circuit 14 Coding control circuit 16 Scene change detection circuit

Claims (9)

[Claims] 1. An encoding device for compressing a data amount of an input digital video signal, comprising orthogonal transform means for transform-encoding for each encoded block of a predetermined size, and the orthogonal transform means. An adaptive quantization unit for controlling the combined data amount of the encoded output in the fixed length unit so that the data amount of the encoded output is contained in the data areas of a plurality of sync blocks; and a variable length unit combined with the adaptive quantization unit. Encoding means, framing means for making the output of the variable length encoding means into transmission data having the structure of the sync block, means for locally decoding the output of the adaptive quantizing means, and the local decoding A frame memory for storing the stored data, a frame between the decoded data of the first frame from the frame memory and a second frame following the first frame. Is detected for each of the coded blocks, and the coded blocks are classified into a first class in which the frame difference is smaller than the threshold value and a second class in which the frame difference is larger than the threshold value. , The frame difference is given to the orthogonal transform means for the first class coded block, and the second frame data is given to the orthogonal transform means for the second class coded block. For controlling the bit allocation for the coded output of the first frame and the coded output of the second frame within the fixed length unit in response to the classification information. An encoding device for a digital video signal, comprising: a control means. 2. The encoding device according to claim 1, wherein the encoding control means sets the detected frame difference to a first threshold value and a second threshold value larger than the first threshold value. A first class in which the frame difference is between the first and second thresholds as compared to a threshold, and a second class in which the frame difference is greater than the second threshold , Classifying the coded block into a third class in which the frame difference is smaller than the first threshold,
For the coded block of the class, the frame difference is given to the orthogonal transforming means, and for the coded block of the second class, the data of the second frame is given to the orthogonal transforming means and the third transforming means. An encoding apparatus for digital video signals, characterized in that the encoding block of the above class is controlled so as not to be transmitted. 3. The encoding device according to claim 1, wherein the bit allocation for the encoded output of the first frame is at least ½ within at least the fixed length unit. Digital video signal encoding device. 4. The encoding device according to claim 1, wherein one bit allocation is provided for the encoded output of the first frame and the encoded output of the second frame within the fixed length unit. An encoding device for a digital video signal, characterized in that it is controlled in response to previous classification information. 5. An encoding device for compressing the data amount of an input digital video signal, comprising orthogonal transforming means for transform coding for each coding block of a predetermined size, and said orthogonal transforming means. An adaptive quantization unit for controlling the combined data amount of the encoded output in the fixed length unit so that the data amount of the encoded output is contained in the data areas of a plurality of sync blocks; and a variable length unit combined with the adaptive quantization unit. Encoding means, framing means for making the output of the variable length encoding means into transmission data having the structure of the sync block, means for locally decoding the output of the adaptive quantizing means, and the local decoding A frame memory for storing the stored data, a frame between the decoded data of the first frame from the frame memory and a second frame following the first frame. Is detected for each of the coded blocks, and the coded blocks are classified into a first class in which the frame difference is smaller than the threshold value and a second class in which the frame difference is larger than the threshold value. , The frame difference is given to the orthogonal transform means for the first class coded block, and the second frame data is given to the orthogonal transform means for the second class coded block. And the bit allocation for the coded output of the first frame and the coded output of the second frame within the fixed length unit is adaptively controlled in response to the classification information. And a coding control means for selectively controlling the second mode in which the bit allocation is a fixed ratio in consideration of a scene change and the like. Encoding apparatus of a digital video signal to. 6. The encoding device for a digital video signal according to claim 5, wherein the second mode is a scene change mode. 7. The encoding device according to claim 6, wherein the second mode is a mode for scene change occurring between the first and second frames. Encoding device. 8. The encoding device according to claim 5, wherein the second mode assigns 1 / to the first frame.
An encoding device for a digital video signal, which is equal to or more than 2 and the allocation for the second frame is the remaining predetermined value. 9. The encoding device according to claim 8, wherein the second mode is an initial state or a mode for scene change that occurs between pairs of first, first and second frames. An encoding device for a digital video signal, characterized by being: