JPH06244686A - Multiplex signal receiver - Google Patents

Abstract

PURPOSE:To provide a multiplex signal receiver which can provide a proper slice level by suppressing the large fluctuation of the slice level caused by deformation at one part of a CR1 signal. CONSTITUTION:This device is provided with a comparator 2 for generating slice data by comparing the voltage of a video signal 1 to be inputted with a reference voltage. A count value corresponding to one cycle term of the CRI signal is measured from the slice data corresponding to the CRI signal by a counter 12, the reference value of an 'H' level term during one cycle term of the CRI signal is calculated from this count value by a reference value calculation part 13, and a count value corresponding to the 'H' level term during one cycle period of the CRI signal is calculated by a counter 14. The reference value of the 'H level term is compared with the count value of the counter 14 by an H level comparator part 15 and corresponding to the compared result, the reference voltage is changed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used, for example, in a decoding device for decoding a multiplexed signal on which binarized information is superimposed, and is a repetitive signal indicating the phase and amplitude of the binarized signal. Also, the present invention relates to a multiplexed signal receiving apparatus that performs a slice process for extracting a binarized signal from a multiplexed signal on which the binarized signal following the repeated signal is superimposed.

[0002]

2. Description of the Related Art Currently, a system for transmitting each information by superimposing a binarized signal during a vertical line period of a television signal has been realized. As one of these systems, information such as characters and figures is transmitted. Teletext is provided.

In a teletext receiver for receiving this teletext, a sliced signal is sliced on the multiplexed signal on which the binarized signal is superposed during the vertical blanking period to obtain a 2x signal from the multiplexed signal. A decoding device is used which extracts a binarized signal and decodes the binarized signal. This decoding device is provided with a multiplexed signal receiving device, and in this multiplexed signal receiving device, for a multiplexed signal in which the binarized signal is superimposed during the vertical blanking period, Slice processing is performed to extract the binarized signal, and the distorted binarized signal is waveform-shaped into a regular binarized signal.

Next, this multiplexed signal receiving apparatus will be described with reference to the drawings. FIG. 5 is a block diagram showing an example of a conventional multiplexed signal receiving apparatus.

As shown in FIG. 5, the multiplexed signal receiving apparatus includes a comparator 2 that takes in a video signal 1. The comparator 2 compares the voltage of the video signal 1 with the reference voltage. When the voltage of video signal 1 is higher than the reference voltage,
"H" level slice data is output, and when the voltage of the input signal is lower than the reference voltage, "L" level slice data is output.

The video signal 1 includes a multiplexed signal in which a binarized signal is superposed during a vertical blanking period, and this multiplexed signal is a clock run-in signal (hereinafter referred to as CRI) added to the head thereof. Signal), start bit, and 2
It is composed of a packet with data of digitized information. The CRI signal is a repetitive signal indicating the phase and amplitude of the data and the start bit, and the start bit is bit data indicating the start of the data.

The slice data from the comparator 1 is C
It is given to the RI gate circuit 3. CRI gate circuit 3
Extracts the slice data corresponding to the CRI signal from the slice data, and the output of this slice data is controlled by the gate pulse.

Slice data corresponding to the CRI signal from the CRI gate 3 is given to the rising edge detecting section 4. The rising edge detection unit 4 detects the rising edge of the CRI signal based on the slice data corresponding to the CRI signal, and outputs the detection result as C
It is output together with the slice data corresponding to the RI signal.

Slice data corresponding to the detection result of the rising edge detector 4 and the CRI signal is given to an up / down counter (hereinafter referred to as U / D counter) 6. U /
The D counter 6 operates with a clock sufficiently faster than the cycle of the CRI signal from the clock generator 5. When the detection result of the rising edge detector 4 indicates a rising edge, the U / D counter 6
Starts the counting operation, and this counting operation is continued until the rising edge detection unit 4 detects the next rising edge.

When the slice data corresponding to the CRI signal is in the "H" level period, the count value of the U / D counter 6 increases, and when the slice data corresponding to the CRI signal is in the "L" level period, The count value of the U / D counter 6 decreases.

The count value of the U / D counter 6 is given to a digital / analog converter (hereinafter, D / A converter) 7. The D / A converter 7 converts the count value of the U / D counter 6 into a corresponding voltage, and this voltage is given to the comparator 2 as a reference voltage.

Next, the operation of the above-mentioned multiplexed signal receiving apparatus will be described with reference to the drawings. FIG. 6 is a CRI signal waveform used for explaining the operation of the multiplexed signal receiving apparatus of FIG.
FIG. 7 is a time chart showing the slice level, slice data, and the count value of the U / D counter. FIG. 7 is a CRI signal waveform used for explaining the malfunction of the multiplexed signal receiving apparatus of FIG. 5, the slice level, and the count of the U / D counter. It is a time chart which shows a value.

First, the voltage of the video signal 1 is the comparator 1
Is compared with a reference voltage, and the slice data generated as a result of this comparison is output. Slice data is C
It is given to the RI gate circuit 3. During the input period of the CRI signal, as shown in FIGS. 6A and 6B, slice data corresponding to the CRI signal is extracted. The slice data corresponding to the CRI signal is supplied to the rising edge detection unit 4 and CR
Whether or not the slice data corresponding to the I signal rises is detected. As shown in FIG. 6C, the U / D counter 6 performs a counting operation from the rising edge of slice data to the next rising edge, and the count value in this period depends on the logical level of the slice data corresponding to the CRI signal. Go up and down. The count value from the U / D counter 6 is converted into a corresponding voltage by the D / A converter 7, and this voltage is given to the comparator 2 as a reference voltage. In the first cycle of the CRI signal, as shown in FIG. 6C, the U / D counter 6
Since the last count value of R is larger than the count value of the first rising, the reference voltage applied to the comparator 2 becomes higher. Therefore, the slice level is as shown in FIG.
As shown in FIG. 5, it becomes high for the next cycle of the CRI signal. That is, as shown in FIG. 6C, the duty ratio between the first rising edge and the next rising edge of the slice data (length m and “L” of the “H” level period of the slice data).
The ratio to the length n of the level period) is detected, and the slice level is set based on this duty ratio.

The above operation is repeated for each cycle of the CRI signal, and the slice level is set for each cycle of the CRI signal.

However, if a part of the CRI signal is deformed and distorted due to the influence of the ghost signal, the rising edge of the slice data corresponding to the CRI signal cannot be detected as shown in FIG. Since the count value of 6 becomes a very small value, the slice level greatly decreases with this count value, and the optimum slice level may not be obtained.

In order to prevent the slice level from varying due to the deformation and distortion of the CRI signal, U /
A method of correcting the count value of the D counter 6 or a method of setting an initial value of the slice level is conceivable. However, in these methods, the timing of changing the slice level is delayed, and optimum slice processing cannot be performed. .

[0017]

As described above, in the conventional multiplexed signal receiving apparatus, when a part of the CRI signal is deformed, the slice level fluctuates greatly and an appropriate slice level is obtained. I can't.

An object of the present invention is to provide a multiplexed signal receiving apparatus capable of suppressing a large change in slice level due to a partial deformation of a CRI signal and obtaining an appropriate slice level.

[0019]

SUMMARY OF THE INVENTION According to the present invention, a repetitive signal indicating a phase and an amplitude of a binarized signal and a multiplexed signal in which the binarized signal following the repetitive signal is superimposed are multiplexed. A multiplexed signal receiving device for performing slice processing for extracting a binarized signal from a multiplexed signal, the slice signal being applied to the multiplexed signal by comparing the voltage of the input multiplexed signal with a reference voltage. Comparing means for generating slice data, cycle detecting means for detecting one cycle period of each cycle of the repeating signal from the slice data generated by the comparing means, and the repetition detected by the cycle detecting means. Reference value calculating means for calculating a reference value of one logic level period in one cycle period of the repetitive signal from one cycle period of the signal, and one cycle period of the repetitive signal Logic level period detecting means for detecting one logic level period; reference value of one logic level period of the repeating signal calculated by the reference value calculating means for each cycle of the repeating signal; Reference voltage changing means for comparing with one logic level period of the repetitive signal detected by the period detecting means and changing the reference voltage of the comparing means to the other logic level period of the repetitive signal according to the result of the comparison. With.

[0020]

[Operation] In the multiplexed signal receiving apparatus of the present invention, the reference value of one logic level period of the repetitive signal calculated by the reference value calculating means and the logic level period are calculated for each cycle of the repetitive signal. The repetitive signal detected by the detecting means is compared with one logic level period of the repetitive signal, and the reference voltage of the comparing means is changed to the other logic level period of the repetitive signal according to the result of the comparison.

For each cycle of the repetitive signal, one of the reference value of one logic level period of the repetitive signal calculated by the reference value calculating means and one of the repetitive signals detected by the logic level period detecting means Since the reference voltage of the comparison means is changed to the other logic level period of the repetitive signal according to the result of the comparison with the logic level period, the reference voltage caused by the deformation such as a part loss of the repetitive signal. That is, it is possible to suppress a large variation in slice level and obtain an appropriate slice level.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the multiplexed signal receiving apparatus of the present invention.

As shown in FIG. 1, the multiplexed signal receiving apparatus includes a comparator 2 that takes in a video signal 1. The comparator 2 compares the voltage of the video signal 1 with the reference voltage. When the voltage of video signal 1 is higher than the reference voltage,
"H" level slice data is output, and when the voltage of the input signal is lower than the reference voltage, "L" level slice data is output.

The video signal 1 includes a multiplexed signal in which a binarized signal is superimposed during the vertical blanking period, and the multiplexed signal has a CRI signal added to the head thereof, a start bit, and It is composed of a packet of binary information data. The CRI signal is a repetitive signal indicating the phase and amplitude of the data and the start bit, and the start bit is bit data indicating the start of the data.

The slice data from the comparator 1 is C
It is given to the RI gate circuit 3. CRI gate circuit 3
Extracts the slice data corresponding to the CRI signal from the slice data, and the output of this slice data is controlled by the gate pulse.

Slice data corresponding to the CRI signal from the CRI gate 3 is given to the rising edge detecting section 4 and the rising edge / falling edge detecting section 11.

The rising edge detecting section 4 detects the rising edge of the CRI signal based on the slice data corresponding to the CRI signal and outputs the result of the detection.

The detection result of the rising edge detector 4 is the counter 12
Given to. The counter 12 operates with a clock sufficiently faster than the cycle of the CRI signal from the clock generator 5, and the rising edge detection unit 4 continues counting operation during the period from the detection of the rising edge to the detection of the next rising edge. By this counting operation, the count value for one cycle of the slice data corresponding to the CRI signal is calculated. That is, this count value becomes a value indicating one cycle in the CRI signal. Counter 1
Reference numeral 2 cooperates with the rising detection section 4 to form a cycle detection means.

The count value of the counter 12 is given to the reference value calculator 13. The reference value calculation unit 13 calculates a value that is 1/2 times the count value of the counter 12, and outputs a value that is 1/2 times the count value as the “H” level period reference value. A predetermined initial value is preset in the reference value calculation unit 13.

The rise / fall detector 11 detects the rise and fall of the CRI signal based on the slice data corresponding to the CRI signal, and outputs the result of the detection.

The detection result of the rising / falling detecting section 11 is given to the counter 14. The counter 14 operates by the clock from the clock generator 5, and continues the counting operation during the period from the rise detection to the fall detection by the rise / fall detection unit 14. By this counting operation, the count value for the "H" level period in one cycle of the slice data corresponding to the CRI signal is calculated. That is, this count value becomes a value indicating the "H" level period. The counter 14 cooperates with the rising / falling detecting section 11 to form a logic level period detecting means.

The count value of the counter 14 is given to the H level comparing section 15 together with the "H" level period reference value of the reference value calculating section 13. The H level comparison unit 15 uses the counter 1
The count value of 4 is compared with the “H” level period reference value of the reference value calculation unit 13, and the U / D counter 16 is instructed to increase or decrease the count value according to the result of the comparison. Counter 14
When the count value of is smaller than the “H” level period reference value of the reference value calculation unit 13, the U / D counter 16 is instructed to increase the count value. On the other hand, when the count value of the counter 14 is larger than the “H” level period reference value of the reference value calculation unit 13, the U / D counter 16 is instructed to decrease the count value.

The U / D counter 16 includes a clock generator 5
It operates by the clock from and the count value is increased or decreased based on the instruction from the H level comparison unit 15.

The count value from the U / D counter 16 is D
It is given to the / A converter 7, and the D / A converter 7 converts it into a voltage corresponding to the count value from the U / D counter 16, and this voltage is given to the comparator 2 as a reference voltage.
The reference voltage is applied to the comparator 2 during the “L” period of slice data.

The D / A converter 7 cooperates with the H level comparing section 15 and the U / D counter 16 to form a reference voltage changing means.

Next, the operation of the multiplexed signal receiving apparatus will be described with reference to the drawings. 2 is a time chart showing a CRI signal waveform, slice level, slice data, an output waveform of the counter 12 and an output waveform of the counter 14, which are used for explaining the operation of the multiplexed signal receiving apparatus of FIG. 1, and FIG. 7 is a time chart showing a CRI signal waveform, a slice level, slice data, an output waveform of a counter 12, and an output waveform of a counter 14, which are used for explaining an operation failure of the encoded signal receiving device.

First, the voltage of the video signal 1 is the comparator 1
Is compared with a reference voltage, and the slice data generated as a result of this comparison is output. Slice data is C
It is given to the RI gate circuit 3. During the input period of the CRI signal, as shown in FIGS. 2A and 2B, slice data corresponding to the CRI signal is extracted. The slice data corresponding to the CRI signal is given to the rising edge detecting section 4 and the rising edge / falling edge detecting section 11.

The rising detector 4 detects the rising of the first cycle of the CRI signal based on the slice data corresponding to the CRI signal, and outputs the detection result. The detection result of the rising detection unit 4 is given to the counter 12, and the counter 12
Continues the period counting operation from the detection of the rising edge of the first cycle by the rising edge detection unit 4 to the detection of the rising edge of the next second cycle. By this counting operation, the count value for one cycle of the slice data corresponding to the CRI signal is calculated. That is, this count value becomes a value f indicating one cycle of the CRI signal, as shown in FIG.

The count value of the counter 12 is given to the reference value calculator 13. The reference value calculation unit 13 calculates a value that is 1/2 times the count value of the counter 12, and outputs a value that is 1/2 times the count value as the “H” level period reference value.

The rising / falling detecting section 11 detects the rising and falling of the first cycle of the CRI signal based on the slice data corresponding to the CRI signal, and outputs the detection result. The detection result of the rising / falling detection unit 11 is given to the counter 14, and the counter 14 rises / falls.
The counting operation is continued during the period from the rise detection by the fall detection unit 14 to the fall detection. By this counting operation, 1 of slice data corresponding to the CRI signal is obtained.
The count value for the "H" level period in the cycle is calculated. That is, this count value becomes a value indicating the “H” level period Hp, as shown in FIG.

The count value of the counter 14 is compared with the "H" level period reference value set as an initial value in the reference value calculation unit 13 by the H level comparison unit 15, and the U / D counter is determined according to the result of the comparison. An instruction to increase or decrease the count value is issued to 16.

When the count value of the counter 14 is smaller than the "H" level period reference value of the reference value calculation unit 13, U / D
The counter 16 is given an instruction to increase the count value,
The count value of the U / D counter 16 increases. As the count value increases, the reference voltage for the comparator 2 is changed to a high value during the “L” level period of the first cycle, that is, the slice level is changed to a high value during the “L” level period of the first cycle. It

When the count value of the counter 14 is larger than the "H" level period reference value of the reference value calculation unit 13, U / D
An instruction to decrease the count value is given to the counter 16, and U
The count value of the / D counter 16 decreases. As the count value decreases, the reference voltage for the comparator 2 is changed to a low value during the “L” level period of the first cycle, that is, the slice level is changed to a low value during the “L” level period of the first cycle. It

Next, in the second cycle of the CRI signal, the count value corresponding to the second cycle of the counter 14 and the “H” level period reference value of the first cycle of the reference value calculation unit 13 are the H level comparison unit 15 And the U / D counter 16 is instructed to increase / decrease the count value according to the comparison result. The reference voltage of the comparator 2 is changed to the “L” level period of the second cycle according to the count value of the U / D counter 16.

The above-described operation is repeated for each cycle of the CRI signal, and for each cycle of the CRI signal, the "H" level period reference value corresponding to the CRI signal is compared with one cycle of the slice data. The slice level is set.

When the CRI signal is affected by a ghost signal or the like, a part of the CRI signal may be lost as shown in FIG. For example, when the fourth cycle of the CRI signal is missing, the fourth cycle of the CRI signal is recognized as an “L” level period, and the recognized “L” level period is calculated by the reference value calculation unit 13 as “H”. It is a variable period of the reference voltage, that is, the slice data after the comparison between the “level period reference value” and the “H” level period corresponding to the count value of the counter 14. Therefore, it is possible to prevent malfunction of the multiplexed signal receiving apparatus during this period.

Also, due to the lack of the fourth cycle, "H"
The level period reference value may be very large, but C
Large fluctuations in the slice level can be suppressed by correcting the "H" level period reference value during the "H" level detection period of the fifth cycle of the RI signal or using an initial value.

As described above, it is possible to suppress large fluctuations in the slice level due to the partial deformation of the CRI signal and obtain an appropriate slice level.

In this embodiment, the "H" level period of the slice data corresponding to the CRI signal is detected. Instead of this, as shown in FIG. 4, the slice data corresponding to the CRI signal is detected. "L" level period of
It is also possible to compare the “L” level period and the reference value of the “L” level period and change the slice data during the “H” level period.

[0051]

As described above, according to the multiplexed signal receiving apparatus of the present invention, it is possible to suppress a large fluctuation of the slice level due to the partial deformation of the CRI signal and obtain an appropriate slice level. You can

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a multiplexed signal receiving apparatus of the present invention.

2 is a time chart showing a CRI signal waveform, a slice level, slice data, an output waveform of a counter 12 and an output waveform of a counter 14 which are used for explaining the operation of the multiplexed signal receiving apparatus of FIG.

3 is a time chart showing a CRI signal waveform, a slice level, slice data, an output waveform of a counter 12 and an output waveform of a counter 14, which are used for explaining the malfunction of the multiplexed signal receiving apparatus of FIG.

FIG. 4 shows a CRI signal waveform, a slice level, slice data, an output waveform of a counter 12 and a counter 14, which are used for explaining a slice level varying method applied to another embodiment of the multiplexed signal receiving apparatus of the present invention. It is a time chart which shows an output waveform.

FIG. 5 is a block diagram showing a conventional multiplexed signal receiving apparatus.

FIG. 6 is a time chart showing CRI signal waveforms, slice levels, slice data, output waveforms of counter 12 and output waveforms of counter 14, which are used for explaining the operation of the conventional multiplexed signal receiving apparatus.

7 is a time chart showing a CRI signal waveform, a slice level, slice data, an output waveform of a counter 12 and an output waveform of a counter 14 which are used for explaining a malfunction of the multiplexed signal receiving apparatus of FIG.

[Explanation of symbols]

2 ... Comparator (comparing means), 3 ... CRI gate circuit, 4 ... Rise detector, 7 ... D / A converter, 11 ... Rise / fall detector, 12, 14 ... Counter, 13 ... Reference value calculator ( Reference value calculating means), 15 ... H level comparing section, 16 ... U / D counter.

Claims (3)

[Claims] 1. A binarized signal from this multiplexed signal for a repetitive signal indicating the phase and amplitude of the binarized signal and a multiplexed signal on which the binarized signal following the repetitive signal is superimposed. A multiplexed signal receiving device that performs slice processing for extracting, and performs slice processing on this multiplexed signal by comparing the voltage of the input multiplexed signal with a reference voltage,
Comparing means for generating slice data; cycle detecting means for detecting one cycle period of each cycle of the repeating signal from the slice data generated by the comparing means; and the repeating signal detected by the cycle detecting means. Reference value calculating means for calculating the reference value of one logic level period of one cycle period of the repetitive signal from the one cycle period of, and a logic level for detecting one logic level period of one cycle period of the repetitive signal. A period detection means, a reference value for one logic level period of the repetition signal calculated by the reference value calculation means, and a repetition signal detected by the logic level period detection means for each cycle of the repetition signal. A reference voltage for comparing with one logic level period and changing the reference voltage of the comparing means to the other logic level period of the repeating signal according to the result of the comparison. A multiplexed signal receiving apparatus comprising: a changing unit. 2. A reference value of one logic level period calculated by the reference value calculation means is a reference value of an "H" level period, and one logic level period detected by the logic level period detection means is The multiplexed signal receiving apparatus according to claim 1, wherein the multiplexed signal receiving period is an "H" level period. 3. The reference value of one logic level period calculated by the reference value calculation means is a reference value of the "L" level period, and one logic level period detected by the logic level period detection means is The multiplexed signal receiving device according to claim 1, wherein the multiplexed signal receiving period is an "L" level period.