JPH06244402A - Solid-state image pickup device and manufacture thereof - Google Patents

Abstract

PURPOSE:To make it easier to eliminate steps on a device by arranging transfer electrodes without overlapping each other and covering the almost whole surface of the metal wiring connected to the transfer electrodes on the transfer electrodes except for photo-electric conversion section. CONSTITUTION:After an N-type transfer section is formed on a semiconductor substrate 1 by phosphorus implantation, a gate insulation film 2 is formed on substrate 1. Then, after gate electrodes 3a, 3b, and 3c are formed by use of a gate electrode pattern, an insulation film 4 is formed on it. After a first contact hole 5 is formed in the gate electrode 3b, a first layer metal wiring film of WSix is formed on the insulation film 4 and a first layer metal wiring 6 is formed by use of a first layer metal wiring pattern to form an insulation film 7. Then, a second contact hole 8 is formed in the gate electrode 3a by use of a second contact hole pattern. Then, a second layer metal film of Al-Si is formed on the insulation film 7 to form a second layer metal wiring 9 by use of a second layer metal wiring pattern, thereby making it possible to almost flatten the surface of the transfer section.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device, and more particularly to an all-pixel readout type solid-state image pickup device.

[0002]

2. Description of the Related Art Conventionally, as an all-pixel-reading type solid-state image pickup device capable of high-speed transfer such as FIT (frame interline transfer) operation, there has been disclosed in Japanese Patent Laid-Open No. 4-1155
As disclosed in No. 73, there is known a solid-state imaging device characterized in that three layers of gate electrodes are shunted with metal electrodes.

The above-mentioned conventional all-pixel readout type solid-state image pickup device will be described below with reference to FIGS.

FIG. 5A shows a plan view of the solid-state image pickup device. That is, the solid-state image pickup device includes the photoelectric conversion unit 5
00 and a transfer unit 501 that reads in a charge signal generated in the photoelectric conversion unit and transfers it in the vertical direction. The transfer unit 501 includes a first-layer gate electrode 53, a second-layer gate electrode 55, The third-layer gate electrode 56 is electrically connected to these gate electrodes through contact holes 58,
It is composed of a metal wiring 59 formed along the vertical direction. Wherein the first phase transfer clock pulses phi ₁ to the metal wiring 59 connected to the 1-layer gate electrode 53 is applied, 2 a second phase layer conductive wiring 59 connected to the gate electrode 55 transfer clock pulses phi ₂ Is applied, and the third-phase transfer clock pulse φ ₃ is applied to the metal wiring 59 connected to the third-layer gate electrode 56, and the metal wiring to which these three-phase transfer clock pulses are applied is repeatedly formed in the horizontal direction. Has been done.

Next, as shown in FIG. 5B, C- in FIG.
A C'cross section is shown. In this sectional view, 51 is a semiconductor substrate, 52 is a gate insulating film, 53 is a first-layer gate electrode,
54 is an insulating film, 55 is a second layer gate electrode, 56 is a third layer gate electrode, 57 is an insulating film, 58 is a contact hole, 59
Indicates metal wiring.

Next, a method of manufacturing the above conventional solid-state image pickup device will be described with reference to FIGS. FIG. 6 shows each pattern plane shape, and FIG. 7 shows sectional views in each manufacturing process. First, after an N-type transfer portion is formed on the semiconductor substrate 51 (not shown), the gate insulating film 52 is formed on the semiconductor substrate 51.
Is formed, a polysilicon film containing an N-type impurity such as phosphorus is deposited, and a first-layer gate electrode pattern (FIG. 6A) is used to form a first-layer gate electrode 53 (FIG. 7).
(A)).

Next, an insulating film 54 is formed by thermal oxidation or the like (FIG. 7B), a polysilicon film containing N-type impurities such as phosphorus is deposited, and a second-layer gate electrode pattern (FIG. 6) is formed.
The second-layer gate electrode 55 is formed by using (b)) (FIG. 7C).

Next, an insulating film 54 is formed by thermal oxidation or the like (FIG. 7D), a polysilicon film containing N-type impurities such as phosphorus is deposited, and a third-layer gate electrode pattern (FIG. 6) is formed.
The third-layer gate electrode 56 is formed by using (c)) (FIG. 7E).

Next, after forming an insulating film 54 by thermal oxidation or the like, an insulating film 57 is formed (FIG. 7F), and a contact hole 58 is formed by using a contact hole pattern (FIG. 6D).
Is formed on the first-layer gate electrode 53 (FIG. 7).
(G)). At this time, contact holes 58 are also formed on the second-layer gate electrode 55 and the third-layer gate electrode 56 at the same time (not shown).

Further, after the metal wiring material is deposited, the metal wiring 59 is formed by using the metal wiring pattern (FIG. 6 (e)) (FIG. 7 (h)).

As described above, an all-pixel readout type solid-state image pickup device in which three layers of gate electrodes are shunted with metal wiring has been realized so far.

[0012]

However, in the structure of the above-mentioned all-pixel readout type solid-state image pickup device, the gate electrode is composed of three layers of polysilicon film, and the gate electrodes have an overlapping structure. Due to the structure of the image pickup device, the step becomes large, and even if a flattening process is performed after the gate electrode is formed, the step is not sufficiently reduced, and the on-chip color filter forming process and the on-chip microlens forming process in the subsequent process are usually performed. Since there is a step of applying a resin, these forming steps become difficult, and as a result, color unevenness due to color filter formation unevenness, sensitivity deterioration due to microlens formation failure, and sensitivity unevenness within the pixel surface There was a problem that caused such as.

Further, in the step of forming these gate electrodes, since the film thickness of the gate insulating film of the gate electrode formed in a later step occurs, the characteristics of the three-phase gate electrodes are all different, so that the transfer There was a problem of causing defects.

Therefore, an object of the present invention is to solve the above problems.

[0015]

In order to achieve the above object, the present invention provides a photoelectric conversion section, at least two sets of independent transfer electrodes for transferring charge signals generated in the photoelectric conversion section, and the transfer electrode. In the solid-state imaging device having a metal wire connected to the transfer electrode, the transfer electrodes are arranged so as not to overlap each other, and the metal wire connected to at least one set of the transfer electrodes among the transfer electrodes, It is characterized in that it covers substantially the entire surface of the transfer electrode except for the photoelectric conversion portion, and has the functions of applying a transfer clock to the transfer electrode and shielding light.

Further, according to the present invention, in the above-mentioned method for manufacturing a solid-state image pickup device, a step of forming a gate insulating film and a gate electrode film on a semiconductor substrate and simultaneously forming the transfer electrode, and the transfer electrode. A step of forming an insulating film on the top,
The method is characterized by including a step of removing a desired region of the insulating film on the transfer electrode and a step of forming the metal wiring on the insulating film.

[0017]

According to the present invention, since it is possible to easily flatten the solid-state image pickup device, it is possible to easily form an on-chip color filter or an on-chip microlens in a subsequent step. As a result, it is possible to suppress color unevenness, sensitivity deterioration, and sensitivity unevenness.

Further, according to the present invention, since the gate electrode is formed of one layer, the characteristics of the three-phase gate electrode can be made the same.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an all-pixel readout type solid-state image pickup device according to the present invention will be described below with reference to FIGS.

FIG. 1A is a plan view of the all-pixel readout type solid-state image pickup device according to this embodiment. That is, this solid-state imaging device is mainly configured by a photoelectric conversion unit 100 and a transfer unit 101 that reads a charge signal generated in the photoelectric conversion unit and transfers the charge signal in the vertical direction. The electrodes of the transfer unit 101 are
A one-layer gate electrode composed of two-phase gate electrodes 3a and 3b arranged in an island shape and one-phase gate electrode 3c arranged in the horizontal direction; 1
The first-layer metal wiring 6 electrically connected through the contact hole 5 and formed in a mesh shape so as not to cover the photoelectric conversion unit 100, and electrically through the gate electrode 3a and the second contact hole 8. The second layer metal wiring 9 is connected and is formed along the vertical direction. When the solid-state imaging device having the above structure is applied to, for example, a 1/3 inch 410,000 pixel CCD area sensor, the first contact hole 5 and
The size of the second contact hole 8 is preferably about 0.8 μm × 0.8 μm in order to obtain an ohmic contact,
Island-shaped gate electrode 3 in which these contact holes are formed
The size of a and 3b is 3.0 μm (horizontal direction) x 2.0
About μm (vertical direction) is desirable, and in order to avoid a short circuit between the first-layer metal wiring 6 and the second-layer metal wiring 9, the first-layer metal wiring 6 around the second contact hole 8 has a window shape. It must be removed, and its size is 1.8 μm (horizontal direction) × 1.
About 4 μm (vertical direction) is desirable. The first phase transfer clock pulses phi ₁ is applied to the second layer metal wiring 9 that is connected to the gate electrode 3a, second phase for a first layer metal wiring 6 connected to the gate electrode 3b transfer clock pulses phi ₂ Is applied and the third-phase transfer clock pulse φ ₃ is applied to the gate electrode 3c formed along the horizontal direction, whereby the transfer operation becomes possible. The gate electrode 3c is preferably connected to the metal wiring at the end of the pixel region in the horizontal direction.

Next, FIG. 1B is a sectional view taken along the line AA 'of the solid-state image pickup device shown in FIG. In this sectional view, 1 is a semiconductor substrate, 2 is a gate insulating film, 3a, 3
b and 3c are gate electrodes, 4 is an insulating film, 5 is a first contact hole, 6 is a first layer metal wiring, 7 is an insulating film, 8 is a second contact hole, and 9 is a second layer metal wiring. . here,
The first-layer metal wiring 6 is connected to the gate electrode 3b through the first contact hole 5, and the second-layer metal wiring 9 is connected to the gate electrode 3a through the contact hole 8.

Next, a method of manufacturing the above solid-state image pickup device will be described with reference to FIGS. FIG. 2 shows each pattern plane shape, and FIG. 3 shows sectional views in each manufacturing process.

First, an N-type transfer portion is formed on the semiconductor substrate 1 by ion implantation of phosphorus (not shown), and then the gate insulating film 2 which is a composite film of an oxide film and a nitride film is formed on the semiconductor substrate 1. Is formed to have an oxide film thickness of about 50 to 100 nm,
A polysilicon film having a thickness of 300 to 600 n is formed by the CVD method.
m. At this time, suitable conditions for forming the polysilicon film are a flow rate of monosilane of 100 to 200 cc / min, a film forming temperature of 550 to 700 ° C., and a film forming time of 30 to 70 minutes. Then, in order to reduce the resistance of the polysilicon film, phosphine or phosphorus oxychloride is used to 900 to 1000 ° C.
The heat treatment is performed at the temperature of, and the sheet resistance of the polysilicon film becomes about 20Ω / □ by this heat treatment. Then, photo and etching are performed using the gate electrode pattern (FIG. 2A) to form the gate electrodes 3a, 3b, 3c (FIG. 3A).

Since the gate electrodes 3a, 3b, 3c are three-phase gate electrodes, it is preferable that the distance between these gate electrodes is small in order to suppress transfer deterioration. It is usually desirable that the distance be 0.3 μm or less, but it may be increased to some extent depending on the element characteristics. In addition,
In order to form such a minute gap, it is desirable to use an i-line photo technique or a technique combining the i-line photo technique and the phase shift technique.

Further, the gate electrodes 3a, 3b, 3c
Is composed of a polysilicon film. However, when the gate electrode pattern becomes long in the horizontal direction due to an increase in the pixel area or the like, pulse waveform rounding may occur due to the resistance of the polysilicon film. is there. In this case, the resistance of the polysilicon film is reduced by changing the doping conditions, the metal such as W is sputtered on the polysilicon film, or the silicide such as WSi is deposited to reduce the resistance. It is also possible to plan.

Next, on the gate electrodes 3a, 3b, 3c,
The insulating film 4 has a film thickness of 1500 to 3000 Å by thermal oxidation in the atmosphere of nitrogen, oxygen and hydrogen at a temperature of 900 to 1000 ° C.
To be formed (FIG. 3B). As another method of forming the insulating film 4, a CVD method may be used, and the gate electrode 3a,
The gap between 3b and 3c is preferably filled with the insulating film 4 for flattening.

Next, the first contact hole pattern (see FIG.
Using (b), photo etching is performed to form the first contact hole 5 on the gate electrode 3b (FIG. 3).
(C)). The contact hole is etched by RF power of 500 to 500 with a parallel plate type plasma etching apparatus.
It is preferable to use 1000 W and use argon, CF ₄ , CHF ₃ or the like as a gas species.

Next, a first-layer metal film of WSix is formed on the insulating film 4 to a film thickness of 200 to 1000 nm by the CVD method, and the first-layer metal wiring pattern (FIG. 2C) is used.
Photo and etching are performed to form the first layer metal wiring 6 (FIG. 3D). The etching of the first metal film is
It is preferable to use a parallel plate type plasma etching apparatus with an RF power of 100 to 200 W and gas species SF ₆ , O _{2 and the} like. Further, as the first layer metal film, TiW, Ti
N, Al-Si, Al or the like may be used. In addition, the first-layer metal wiring pattern (FIG. 2C) functions not only as a wiring but also as a light-shielding film that suppresses the occurrence of smear, so that the second contact hole is formed in a later step. The pattern covers the entire gate electrode except the neighboring region.

Next, the first layer metal wiring 6 is formed by the CVD method.
An insulating film 7 is formed thereon to a film thickness of 200 to 700 nm (FIG. 3E). The insulating film 7 may be a flattenable insulating film such as BPSG (boron phosphorus silicate glass).

Next, the second contact hole pattern (see FIG.
Photoetching is performed using (d) to form the second contact hole 8 on the gate electrode 3a (FIG. 3).
(F)). The contact hole is etched by RF power of 500 to 500 with a parallel plate type plasma etching apparatus.
It is preferable to carry out at 1000 W by using argon, CF ₄ , CHF ₃ or the like as a gas species.

Next, a second layer metal film of Al--Si is formed on the insulating film 7, and a second layer metal wiring pattern (FIG. 2 (e)).
Is used to perform photo-etching to form the second-layer metal wiring 9 (FIG. 3G). As the second-layer metal film, Al, Al-Si / TiW or the like may be used. Further, the second-layer metal wiring 9 has a second metal wiring 9 for preventing smear.
It is better to cover the area where the first-layer metal wiring 6 is removed in the contact hole formation area.

From the above, the transfer portion formed of the gate electrodes 3a, 3b and 3c can be made substantially flat, and by extension, the photoelectric conversion portion can also be made flat.
Usually, a flattening step (not necessarily required) on the second-layer metal film which is performed in a later step becomes easier, and in the subsequent step,
Usually, the on-chip color filter forming step and the on-chip microlens forming step that accompany the resin applying step can be performed in a state where there is almost no application unevenness.

Next, another embodiment according to the present invention will be described with reference to FIG.

FIG. 4A shows a plan view of the all-pixel readout type solid-state image pickup device in this embodiment. That is, this solid-state imaging device is mainly composed of a photoelectric conversion unit 400 and a transfer unit 401 that reads in a charge signal generated in the photoelectric conversion unit and transfers it in the vertical direction. The electrodes of the transfer unit 401 are:
Two-phase gate electrodes 43a and 43b arranged in an island shape and one-phase gate electrode 43c arranged in the horizontal direction
A first electrode metal wiring 46 which is electrically connected to the gate electrode 43a and the gate electrode 43a through the first contact hole 45 and is formed along the horizontal direction, the gate electrode 43c and the first contact. Via a first-layer metal wiring 46 ′, which is electrically connected through the hole 45 and is formed along the horizontal direction, different from the above-mentioned first-layer metal wiring, the gate electrode 43 b and the second contact hole 48. The second layer metal wiring 49 is electrically connected and is formed along the vertical direction. Here, 1 connected to the gate electrode 43a
The first phase transfer clock pulse φ ₁ is applied to the second layer metal wiring 46, and the second phase transfer clock pulse φ ₂ is applied to the second layer metal wiring 49 connected to the gate electrode 43b and connected to the gate electrode 43c. Third on the first layer metal wiring 46 '
A phase transfer clock pulse φ ₃ is applied, and the transfer operation becomes possible by these three-phase transfer clock pulses. In the above-described embodiment, the gate electrode 43c to which the third-phase transfer clock pulse φ ₃ is applied is also shunted by the metal wiring as compared with the embodiment shown in FIG. It is less likely to occur.

Next, FIG. 4B is a sectional view taken along the line BB 'of the solid-state image pickup device shown in FIG. In this cross-sectional view, 41 is a semiconductor substrate, 42 is a gate insulating film, and 43.
a, 43b, 43c are gate electrodes, 44 is an insulating film, 45
Is the first contact hole, 46 and 46 'are the first layer metal wiring,
Reference numeral 47 is an insulating film, 48 is a second contact hole, and 49 is a second layer metal wiring. Here, the first-layer metal wiring 46,
46 'is connected to the gate electrodes 43a and 43c through the first contact holes 45, respectively, and is connected to the second-layer metal wiring 4
9 is the gate electrode 43b through the second contact hole 48
Connected with.

The solid-state image pickup device is manufactured by the same method as that shown in FIG. 3, except that the first contact hole pattern, the first layer metal wiring pattern, and the second contact hole pattern shown in FIG. Will be manufactured using a different pattern.

The present invention can be variously modified within the scope of the claims and is not limited to the above embodiment.

[0038]

As described above in detail, according to the present invention, the step difference on the device can be reduced by about 500 to 800 nm to facilitate the flattening, and the on-chip color filter and the microlens can be formed. It can be formed easily and stably, and as a result, it is possible to reduce color unevenness, reduce sensitivity unevenness, and improve sensitivity and smear by improving the light collection rate.

Further, since the insulating film thickness of each gate electrode is the same, the characteristics of each gate electrode are uniform, so that transfer failure can be eliminated.

Further, since the number of steps of forming the gate electrode and the metal wiring can be reduced, a lower cost solid-state image pickup device can be obtained.

Further, since the metal wiring for applying the clock pulse covers all the transfer electrodes, light can be shielded and smear can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing a planar structure and a sectional structure according to an embodiment of the present invention.

FIG. 2 is a diagram showing a plane pattern according to an embodiment of the present invention.

FIG. 3 is a diagram showing a sectional structure of a manufacturing process according to an embodiment of the present invention.

FIG. 4 is a diagram showing a planar structure and a sectional structure according to another embodiment of the present invention.

FIG. 5 is a diagram showing a planar structure and a cross-sectional structure of a conventional solid-state imaging device.

FIG. 6 is a diagram showing a plane pattern according to a conventional technique.

FIG. 7 is a diagram showing a cross-sectional structure of a manufacturing process according to a conventional technique.

[Explanation of symbols]

1,41 Semiconductor substrate 2,42 Gate insulating film 3a, 3b, 3c, 43a, 43b, 43c Gate electrode 4,44 Insulating film 5,45 First contact hole 6,46,46 'First layer metal wiring 7,47 Insulating film 8,48 Second contact hole 9,49 Second layer metal wiring

Claims (2)

[Claims] 1. A solid-state imaging device comprising a photoelectric conversion unit, at least two sets of independent transfer electrodes for transferring charge signals generated in the photoelectric conversion unit, and a metal wiring connected to the transfer electrodes, The transfer electrodes are arranged so as not to overlap each other, and the metal wiring connected to at least one set of the transfer electrodes of the transfer electrodes covers substantially the entire surface of the transfer electrodes except the photoelectric conversion section. At the same time, a solid-state image pickup device having the functions of applying a transfer clock to the transfer electrodes and shielding light. 2. The method for manufacturing a solid-state imaging device according to claim 1, wherein a gate insulating film and a gate electrode film are formed on a semiconductor substrate, and the transfer electrode is simultaneously formed, and the transfer electrode. A step of forming an insulating film thereon, a step of removing a desired region of the insulating film on the transfer electrode, and a step of forming the metal wiring on the insulating film. Manufacturing method of solid-state imaging device.