JPH06237481A - Input buffer type switch device - Google Patents

Abstract

PURPOSE:To reduce a delay in ATM cell flow and fluctuation in the ATM cell flow. CONSTITUTION:When a 0 system SW31 is switched to a 1 system SW32, a control section 30 allows selectors 39, 40 to select 1 system from 0 system and allows each of input buffers 36, 37 of the 1 system to stop reading. Cells resident in the O system are multiplexed by output interface sections 41, 42 and the result is outputted. When either of the input buffers 33, 34 of the 0 system is idle, the read stop of the input buffer 36 or 37 of the corresponding 1 system is released. The output interface sections 41, 42 multiplex cells from the 0 system and cells from the 1 system by using a clock CK2 having the double speed (2Xf1) and store the result to the buffers 44, 46 by using the CK2, and reads the cell at a transfer speed (f1) of the inputted cell and outputs the cells.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input buffer type switch device, and can be applied to, for example, switching of ATM switches when ATM switches are redundantly constructed inside the device.

[0002]

2. Description of the Related Art In recent years, various technical developments have been made to realize ATM communication. For example, a normal ATM switch used in an ATM switch requires a buffer for avoiding cell collision in the internal or output section, so that the switching section and the buffer constitute one switch. .

The buffers are arranged at the input side and the output side of the switching section.

As a non-instantaneous switching system for the input buffer type switch provided on the input side of the switching section,
An example is a switching system having a configuration as shown in FIG.

In FIG. 2, the system is composed of 0 system and 1 system. Then, the 0-system is the active system and the 1-system is the standby system. As an explanation of the switching operation, an operation when switching from the 0-system active system to the 1-system standby system will be described as an example.

In the active system (0 system) before switching,
The input selector 3 and the input selector 4 are connected to the 0 system side. Then, since the switching buffers 1 and 2 are capable of reading cells at the same time as writing cells, cells arriving at the input port 50 or 51 are immediately given to the 0-system switch (SW) 5, It is switched by the internal switch (SW) unit 8 and is output from the output port 52 or 53 through the output selector 13 or 14.

When a switching request for the system is requested (generated), the switching buffers 1 and 2 are read until all the cells accumulated in the 0 system input buffers 6 and 7 are output at this time. Is stopped. Then, the cells arriving at the input ports 50 and 51 thereafter are switched to the switching buffers 1 and 2.
And is put in a waiting state for reading.

When cells do not exist inside the input buffers 6 and 7 of the 0-system switch (SW) section 5 due to system switching, the input selectors 3 and 4 are set to 0 for the first time.
Switch from the system (active system) side to the 1 system (standby system) side. Then, by switching the input selectors 3 and 4 to the 1-system side, the input cells can read from the switching buffers 1 and 2, and the switching to the 1-system (standby system) is completed. .

By the switching operation as described above, the switching can be performed without causing cell duplication or loss.

[0010]

However, in the case of the system switching operation according to the configuration of FIG. 2 described above,
When the 0-system is operated as the active system, all the input buffers 6 and 7 have no cells and are switched to the switch (SW) unit 5 or 9 as a unit only when they become empty. Therefore, when switching is performed, there is a problem that there is a delay time from the time when the input buffer 6 or 7 becomes empty first to the time when the input buffer 7 or 6 becomes empty later.

That is, since the internal states of the input buffers 6 and 7 of the active system (0 system) switch (SW) unit 5 at the time of generating the system switching command differ depending on the traffic characteristics of each input port, the switching command. The time required from the occurrence to the emptying of the input buffers 6 and 7 is usually different for each input buffer.

For example, in the explanatory view of FIG. 3, time t1
If the input buffer 6 becomes empty first and then the input buffer 7 becomes empty at time t2 thereafter, the input port 50
As shown in FIG. 3B, a delay of (t2-t1) time occurs in the ATM cell flow flowing from the output port 52 to the output port 52 or 53. This means that the AT flowing from the input port 50 to the output port 52 or 53
In the case of paying attention to the M cell flow, after the switching command is generated, from the time when the input buffer 6 becomes empty to the time when the other input buffer 7 becomes empty (t2-t1), the output port It means that the ATM cell flow output from 52 or 53 is interrupted.

In an ideal case where there is no delay due to such switching, the output is uniform without interruption as shown in FIG. 3 (a).

As means for solving the above problems, the delay due to the switching as described above is temporarily suppressed, that is, in order to converge the delay within a certain time,
It is conceivable to solve the problem by making the reading speed of the cells from the switching buffers 1 and 2 faster than the writing speed. This means that the switching buffers 1 and 2 are made empty within a certain time. However, it is expected that fluctuations will occur in the ATM cell flow rate output from the output port 52 or 53 by performing such a thing.
The fluctuation of the ATM cell flow rate means that the cell interval becomes shorter (clogged) or becomes longer.

Therefore, in the system switching system having the above configuration, the delay of the ATM cell flow and the fluctuation of the ATM cell flow, which are caused by the switching, finally result in the deterioration of the ATM communication quality and the traffic control of the ATM communication network. It is expected that such things will become difficult.

Therefore, there is a demand for an apparatus for switching that does not cause delays in the ATM cell flow and fluctuations in the ATM cell flow rate due to system switching. Such a problem is also demanded in a device for switching packets.

The present invention has been made in view of the above problems, and its object is to reduce delay of ATM cell flow and fluctuation of ATM cell flow to a slight amount. It is an object of the present invention to provide an input buffer type switch device that can be used.

[0018]

In order to achieve the above object, the present invention comprises a plurality (N) of input buffers,
When input packets (for example, fixed-length packet cells or variable-length packets) are given in parallel to these input buffers, they are stored in the respective input buffers and are switched according to the route information of the stored packets. A plurality of input buffer type switch units (for example, input buffer type ATM switches) that output from each output line according to route information are redundantly provided, and any one of the input buffer type switch units is operated. The system operates as a standby system, and any one of the remaining input buffer type switch units is made to stand by as a standby system, and packets are given in parallel to a plurality of (N) input lines to the above operating system. When a system switching request is given to the standby system, the plurality of (N) input lines are switched to the standby system and connected, and the standby system is operated to switch the input packet. In the input buffer type switch device for performing quenching was achieved at a characteristic configuration described below.

That is, the detection means for detecting the presence or absence of a packet inside each input buffer of the above-mentioned operating system, the read control means for controlling the reading of the packet of each input buffer of the above-mentioned backup system, and each of the above-mentioned operating system. The multiplexing of each output packet from the output line and each output packet from each output line of the protection system corresponding to each output line of the operation system is performed at a speed higher than the transmission rate of the input packet. When the multiplexed packet is stored in the buffer at the first clock and the multiplexed packet is read out,
A plurality of (N) output means for reading at the same speed as the transmission speed of the input packet are provided.

Then, when the system switching request is given from the operating system to the standby system, the plurality (N) of input lines are switched to the standby system and connected, and the reading of the packet of each buffer of the standby system is performed. When stopped by the read control means, the packets remaining in the operating system are given to the corresponding output means from any of the output lines, and the no-packet state is detected by the detecting means in each input buffer of the operating system, The read suspension of the packets in the standby input buffer corresponding to the active packet-less input buffer is released, and the output packet from the standby system and the packet remaining in the active system are multiplexed. It is characterized in that each output means performs each packet and outputs each packet.

After the plurality of (N) input lines are switched from the active system to the standby system and connected,
When all the input buffers of the operation system are in a state of no packet, the output means transfers only the packets supplied from the output lines of the backup system to the corresponding buffers. It may be stored using a second clock having the same speed as the speed.

In the input buffer type switch device,
Three or more input buffer type switch units are provided, any of which may be an active system, and any input buffer type switch unit may be used as a standby system.

[0023]

According to the present invention, after a plurality (N) of input lines are switched from the active system to the standby system and connected, the input packet is given to the standby system. Although the input packet is not given to the active system, the packets before switching may remain in each input buffer. Therefore, until the remaining packet disappears from the active system, Stop reading packets stored in each input buffer.

When any of the active input buffers becomes empty, the read suspension of the standby input buffer corresponding to the active input buffer is released. For example,
The input buffer of the operation system corresponding to the input line 1, and the input line 1
Corresponds to the input buffer of the spare system corresponding to. By this release, the output line of the standby system (for example, S
2) outputs an input packet from, for example, output line S2
To the output means corresponding to. At this time, even if packets from other input buffers in the active system are also supplied to the same output means, the packets from the two routes can be multiplexed by the first clock having a high speed.

The multiplexed packet obtained by this multiplexing is stored in the buffer using the first clock and is read at the same speed as the input packet transmission rate at the time of reading, so that the transmission rate is the same as the input packet transmission rate. Packets can be output.

Then, after that, when the input buffer of the active system becomes empty, the suspension of reading of the corresponding input buffer of the standby system is released. In this way, each output unit can multiplex packets from both the active system and the standby system and read them from the buffer until all input buffers in the active system are empty. It is possible to minimize the delay of the packet interval as in the conventional case when switching to the backup system and also minimize the fluctuation of the packet interval.

When all the input buffers of the active system are in the state of no packet after the active system is switched to the standby system and connected, each output means is supplied from each output line of the standby system. The second packet at the same transmission rate as the input packet is sent to each corresponding buffer.
By using the clock of (1), the packet interval delay and the packet interval fluctuation can be minimized in the same manner as described above without performing the multiplexing operation.

After the input buffer type switch unit A of the operation system is switched to the input buffer type switch unit B of the standby system, the input buffer type switch unit B is operated as the operation system in the same manner as described above, Shape switch section A
Can also be operated as a standby system, so B to A
Even when the system is switched to, it is possible to obtain the same effect as described above.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the present invention applied to an input buffer type ATM switch device will be described with reference to the drawings.

FIG. 1 shows an input buffer type AT of this embodiment.
It is a functional block diagram of an M switch device. In FIG. 1, the input buffer type ATM switch device is provided with input ports 61 and 62 to which cells are supplied and output ports 63 and 64 for outputting cells. The transmission rate of the input cell and the output cell is, for example, STM.
In the case of -4, it is about 600 Mbps.

A 0-system switch (SW) 31 (active system, active system), a 1-system switch (SW) 32 (standby system), and a selector provided on the input side are provided between the input and output. 39, 40, output interface units 41, 42 newly provided on the output side, and a control unit 30 for controlling each component are interposed.

Moreover, 0 system switches (SW) 31 and 1
The system switch (SW) 32 has the same configuration as the conventional configuration. That is, the 0-system switch (SW) 31, which is the active system (operating system), is composed of the input buffers 33 and 34 and the switching (SWG) unit 35. Further, the 1-system switch (SW) 32, which is a standby system, is used for the input buffer 3
6, 37 and a switching (SWG) unit 38.

Furthermore, the newly provided output interface section 41 comprises a multiplexer 43 and a buffer 44. Similarly, the newly provided output interface unit 42 also includes a multiplexer 45 and a buffer 46.

Input buffers 33 to 3 provided in the 0-system switch (SW) 31 and the 1-system switch (SW) 32.
Reference numerals 4 and 36 to 37 are buffers having the same capacity, for example, buffers for storing about 50 to 100 cells. If one cell is 53 bytes, then about 2650 bytes (= 53 bytes x 50 cells) to 5
It is a buffer of about 300 bytes (= 100 cells × 53 bytes).

Then, these input buffers 33 to 3
4, 36 to 37 are supplied with the basic clock CK1 at the speed f1 and are used for writing a given cell or reading a stored cell.

The buffer 44 and the buffer 46 of the newly provided output interface units 41 and 42 have the same capacity, and have a capacity of 20 to 30 cells or more. That is, about 1060 bytes (= 20 cells x
It is about 53 bytes to 1590 bytes (= 30 cells × 53 bytes).

Then, the output interface units 41 and 42
The function and operation of will be described with reference to FIGS. 1 and 4. The output interface units 41 and 42 have the same function as a single function.

For the sake of simplicity, the function and operation of one of the output interface units 41 will be described as a representative. Basically, the cell signal S1 from the 0-system switch 31 and the cell signal S2 from the 1-system switch 32 are multiplexed to obtain a multiplexed signal S.
Get 5. The multiplexed cell signal S5 is stored in the buffer 44. The stored multiplexed cell signal is stored in this buffer 4
4 and is output as a cell signal S7 from the output port 63
Is output from.

Further, the operation for realizing the output interface unit 41 will be concretely described. Since the multiplexer 43 actually requires high-speed operation, it is desirable that the multiplexer 43 be realized by a high-speed logic gate circuit or the like rather than by programming. The same applies to the buffer 44.

Then, in the multiplexer 43, the basic clock CK1 (FIG. 4A) and the basic clock CK1 (f
1 frequency, for example, twice the frequency (600 MHz) (2
The clock CK2 (× f1) (FIG. 4D) is the control unit 3
Supplied from 0. Similarly for the buffer 44, the clock C
K1 (FIG. 4A) and clock CK2 (FIG. 4D) are supplied. Then, from the clock CK2, the supplied cell signal is read into the multiplexer 43, or the multiplexer 43
Clocks CK21 and CK22 for writing cells from
Produces and.

The operation when the cell signal S1 (0 system) and the cell signal S2 (1 system) are supplied to the multiplexer 43 at the same timing will be described. When the cell signal S1 is supplied at the timing A (FIG. 4 (b)) and the cell signal S2 is supplied at the timing B (FIG. 4 (c)), the clock CK21 generated from the clock CK2 is supplied to the cell A. The data of the cell A (FIG. 4 (b)) is read at the falling timing e1 (FIG. 4 (e)). And the clock CK
The data of the cell B (FIG. 4C) is read at the falling timing f1 (FIG. 4F) of 22.

The data of the cell A read at the timing e1 is the rising timing e2 of the clock CK21.
Then, the cell A is written, the cell A ^* is output as the signal S5, and the signal is written in the buffer 44 at the clock CK2. When the written cell A ^* is read from the buffer 44,
Readout output cell A at the speed of clock CK1 (see FIG. 4 (h)
S7) is obtained.

As for the data of the cell B read at the timing f1 (FIG. 4 (f)), the cell B is written at the rising timing f2 of the clock CK22 and the cell B ^* is output as the signal S5, and the buffer 44 clocks it. CK2
Write in. When the written cell B ^* is read from the buffer 44, the read output cell B (S7 in FIG. 4H) is obtained at the speed of the clock CK1.

Similarly to the above, when the cells C and D are applied to the multiplexer 43 at the same time, the cell C is read at the falling timing e3 of the clock CK21. Also,
The cell D also has the falling timing f3 of the clock CK22.
Then, the cells C and D are multiplexed and output from the buffer 44 in the same procedure as described above.

Next, the function of the control unit 30 will be described. The control unit 30 supplies a selector switching instruction signal to the selectors 39 and 40 on the input side to set the selectors 39 and 40 to 0.
Switch to system or system 1. Incidentally, selector 3
The switching operation from the 0 system to the 1 system of 9 and 40 is performed in conjunction with the switching operation from the 1 system to the 0 system.

Further, the control unit 30 includes the input buffers 33 to 33.
A read control signal is supplied to each of 34 and 36 to 37.

Next, the operation of the input buffer type ATM switch device of FIG. 1 will be described. In FIG. 1, as an example, it is assumed that the 0-system switch 31 is the active system (active system) and the 1-system switch 32 is the operation, with no buffer in each buffer. Operation Before Switching First, before switching, the selectors 39 and 40 are switched to the 0 system side by the selector switching instruction signal from the control unit 30, and the input buffers 33 and 34 are read by the read control signal from the control unit 30. Controlled as possible.
In such a state, the cell applied to the input port 61 is stored in the input buffer 33 through the selector 39. On the other hand, the cell given to the input port 62 is also stored in the input buffer 34 through the selector 40.

The cells stored in the input buffers 33 and 34 can be read, and the read cells are supplied to the switching (SWG) unit 35, where they are set in the cells and follow the route information in the header. Each cell is output from one of the two outgoing lines of the switching (SWG) unit 35. For example, the cells output from the output line S1 are multiplexed by the double speed clock CK2 by the multiplexer 43 of the output interface unit 41, and the double speed clock C is stored in the buffer 44.
It is stored in K2. The cells stored in the buffer 44 are
When reading, the original speed clock CK1 is read. Then, the data is read from the output port 63.

On the other hand, the cell output from the output line S3 of the 0-system switch 31 is multiplexed by the double speed clock CK2 by the multiplexer 45 of the output interface section 42, and the buffer 4
6 is stored in the double speed clock CK2. Buffer 46
When reading the cell stored in, the clock is read at the clock CK1 at the original speed. Then, the data is read from the output port 64.

When the operation control unit 30 at the time of switching receives a system switching command from the outside or the like, the control unit 30 supplies a selector switching instruction signal for switching the system to the selectors 39 and 40. The selectors 39 and 40 switch from the 0 system to the 1 system by the selector switching instruction signal.

At the same time, the control unit 30 supplies a read control signal for stopping the cell read to the input buffers 36 and 37 of the 1-system switch 32. The supply of the read control signal causes the input buffers 36 and 37 to change from the cell readable state up to that point to the read stopped state. However, even if the reading is stopped, the input buffer 36,
When a cell is supplied to 37, the cell is written and stored.

Even when the selector switching instruction signal is output from the control unit 30, since the input buffers 33 and 34 of the 0-system switch (SW) 31 are set to the readable state, the cells can be read as long as the cells remain. Is output. Then, one of the input buffers 33 and 34 becomes empty first. This depends on the internal states of the buffers 33 and 34 at the time when the selector switching instruction signal is output.
Normally, it does not become empty at the same time.

Operation when the input buffer 33 becomes empty first. Therefore, in this example, the 0-system switch (SW) 3
The description will be made assuming that the input buffer 33 of 1 becomes empty first. Then, when the input buffer 33 becomes empty, a buffer empty detection signal is supplied to the control unit 30. Then, the control unit 30 supplies to the input buffer 36 a read control signal for canceling the read stop of the input buffer 36 of the 1-system (standby system) switch (SW) 32. As a result, the input buffer 36 reads out the cell stored so far and supplies it to the switching (SWG) unit 38.

In this way, the switching (SWG) unit 3
8 performs switching according to the route information of the cell supplied from the input buffer 36 of the 1-system switch (SW) 32, and outputs from the output line S2 or S4. Among the outputs, the cell output from the output line S2 is supplied to the multiplexer 43.
At this time, the cells remaining in the input buffer 34 of the 0-system switch (SW) 31 are the switching (SWG) unit 35.
When output from the output line S1 of the output line S1 and supplied to the multiplexer 43, the cells from the output line S2 and the cells of the output line S1 are simultaneously multiplexed.

This multiplexer 43 has a double speed (frequency 2 × f).
The cells from two routes are multiplexed using the clock CK2 of 1), and the multiplexed cell signal is written in the buffer 44 at the clock CK2. Then, at the time of reading, it is read at CK1 of the original speed (frequency f1), and the multiplexed cell is output from the output port 63.

The outgoing line S of the 1-system switch (SW) 38
The cells output from No. 4 are supplied to the multiplexer 45, and at the same time, the cells output from the output line S3 of the 0-system switching (SWG) unit 38 are also supplied to the multiplexer 45.
This multiplexer 45 multiplexes with a clock CK2 of double speed (frequency 2 × f1), and buffers the multiplexed cell signal.
Write to 6 with clock CK2. Then, when reading, the cell is read at CK1 at the original speed (frequency f1), and the multiplexed cell is output from the output port 64.

Operation when the input buffer 34 is emptied later Next , when all the cells in the input buffer 34 of the 0-system switch (SW) 31 are read out, it is detected by the control unit 30 by the empty buffer detection signal. Then, the control unit 30 supplies a read control signal for canceling the read stop of the input buffer 37 of the 1-system switch (SW) 32 to the input buffer 37.

This read control signal causes the input buffer 3
7 starts reading the cell that has been stored until then. The cells read from the input buffer 37 are supplied to the switching (SWG) unit 38, where they are switched according to the route information and output from the output line S2 or S4. The cell output from the output line S2 is supplied to the multiplexer 43. At this time, the multiplexer 43 is no longer supplied with cells from the 0-system switch (SW) 31. Then, the cells from the outgoing line S2 are multiplexed with the clock CK2, and the multiplexed cell signal is written into the buffer 44 with the clock CK2 and is read with the clock CK1 when reading.

The outgoing line S of the 1-system switch (SW) 32
The cells output from No. 4 are given to the multiplexer 45 of the output interface unit 42. At this time, the multiplexer 45 is no longer supplied with cells from the 0-system switch (SW) 31. Then, the cells from the outgoing line S4 are clocked by the clock C.
Multiplexing is performed with K2, and the multiplexed cell signal is written into the buffer 46 with the clock CK2 and is read with the clock CK1 when reading.

As a result, the switching from the 0 system (active system, active system) switch (SW) 31 to the 1 system (standby system) switch 32 is completed.

The 0-system (active system, active system) switch (S
If the control unit 30 detects that the input buffers 33 and 34 of W) 31 are in the state of no cells at the same time, the control unit 30 simultaneously detects this and the control unit 30 switches the 1-system (standby system) switch (S
W) 32 can be realized by giving a read control signal for reading the cell to the input buffers 36 and 37.

According to the input buffer type ATM switch device of the above embodiment, the control unit 30 causes the 0-system switch (S
A selector switching instruction signal for switching from W) 31 to the 1-system switch (SW) 32 is given to the selectors 39 and 40 so that cells from the input ports 61 and 62 are supplied to the 1-system switch (SW) 32. In this case, the cells remain in the input buffers 33 and 34 of the 0-system switch (SW) 31 for a certain period of time after switching, so that the cells are also output from the 0-system switch (SW) 31.

In such a case, the 1-system switch (SW) 3
When the cells from 2 and the remaining cells output from the 0-system switch (SW) 31 are simultaneously output, the multiplexer 43
And 45 both cells with double speed clock CK2
And the multiplexed cell signal is written to the buffers 44 and 46 with the clock CK2 and read with the clock CK1 at the original speed when reading, thereby delaying the cell flow speed output from the output ports 63 and 64, and The fluctuation of the flow can be made extremely small. That is, it is possible to minimize the effect of switching the system on the input cell flow.

In the above embodiment, the switching (SW) units 31 and 32 are used for double redundancy. However, the present invention is not limited to such a double redundancy configuration, and a triple or more redundancy configuration is also possible. Can be applied.

Further, in the above-mentioned one embodiment, an example in which the number of input ports is two is shown, but the present invention is not limited to this, and is actually realized by several tens of ports. The present invention can be applied even if the number of input ports is larger. The number of output ports also depends on the number of input ports as described above, so any number may be set.

Furthermore, in the above-described embodiment, the 0-system switching (SW) unit 31 is set as the active system (operating system), and
Although the switching operation from the 0 system to the 1 system has been described with the system switching (SW) unit 32 as the standby system, the same effect as described above can be obtained even in the switching operation from the 1 system to the 0 system. You can

Furthermore, the output interface unit 4 of FIG.
The operation timing charts of Nos. 1 and 42 are examples, and cell multiplexing and storage / readout of cells to / from the buffer may be performed at other operation timings. Since the output interface units 41 and 42 are required to operate at high speed, it is desirable that the hardware is realized by a device capable of performing high speed switching even when realizing a circuit.

In the above embodiment, after switching from the 0-system switch (SW) 31 to the 1-system switch (SW) 32, both of the input buffers 33 and 34 of the 0-system switch (SW) 31 are used. Even if there is no cell in
The multiplexer 43 is configured so as to be able to multiplex cells from both paths from the outgoing line S1 (0 system) and the outgoing line S2 (1 system). Further, one multiplexer 45 is also configured so as to be able to multiplex cells from both paths from the outgoing line S3 (0 system) and the outgoing line S4 (1 system). The configuration is not limited, and as another configuration, for example, a 0-system switch (S
If both of the two input buffers 33, 34 of W) 31 become empty, the cells from the output line S2 of the 1-system switch (SW) 32 are not multiplexed by the multiplexer 43, and the buffer 44 is used as it is. Write clock CK1 to clock C
The configuration may be such that the reading is performed by K1. Furthermore, in the above-mentioned one embodiment, one embodiment in the case of being applied to the input buffer type ATM switching device has been described, but it is also possible to apply to another, for example, the input buffer type packet switching device.

[0069]

As described above, the input buffer type switch device of the present invention comprises the detecting means, the reading control means and the plurality of (N) output means, and the system switching request from the active system to the standby system. Is given, the plurality of (N) input lines are switched to the standby system and connected, and the reading of the packets from the buffers of the standby system is stopped by the read control means.
When the packet remaining state in the active system is given to each corresponding output means from one of the output lines and the no-packet state is detected by each input buffer in the active system, the input buffer without the packet in the active system is detected. It is possible to release the suspension of reading of packets from the corresponding backup system input buffer, multiplex the output packets from the backup system with the packets remaining in the active system, and output each packet by the corresponding output means. Therefore, it is possible to minimize the delay such as the packet interval and the cell interval when switching the system, and to minimize the fluctuations such as the packet interval and the cell interval.

[Brief description of drawings]

FIG. 1 is a functional block diagram of an input buffer type ATM switch device according to an embodiment of the present invention.

FIG. 2 is a functional block diagram of a conventional input buffer type ATM switch device.

FIG. 3 is an explanatory diagram for explaining a problem of a conventional input buffer type ATM switch device.

FIG. 4 is an operation timing chart of the output interface unit according to the embodiment.

[Explanation of symbols]

30 ... Control unit, 31 ... 0 system switch (SW), 32 ... 1
System switch, 33, 34, 36, 37 ... Input buffer,
35, 38 ... Switching (SWG) section, 39, 40 ...
Selectors 41, 42 ... Output interface unit 43,
45 ... Multiplexer, 44, 46 ... Buffer, 61, 62 ...
Input ports, 63, 64 ... Output ports.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical display location 9076-5K H04Q 11/04 M

Claims (2)

[Claims] 1. A plurality of (N) input buffers are provided, and when input packets are supplied to these input buffers in parallel, they are stored in the respective input buffers and switched according to the route information of the stored packets. There is redundantly provided a plurality of input buffer type switch units for outputting from each output line according to route information, and one of the input buffer type switch units is operated as an operating system, and the remaining input buffer type switch units are operated. Any one of the switch units is made to stand by as a standby system, packets are given in parallel to a plurality of (N) input lines to the above-mentioned operating system, and a switching request for the system from the above-mentioned operating system to the standby system is given. And an input buffer type switch device that switches the plurality of (N) input lines to a standby system and connects them, and operates the standby system to switch input packets. Detecting means for detecting the presence / absence of a packet in each input buffer of the operating system, read control means for controlling the reading of the packet of each input buffer of the standby system, and each output from each output line of the operating system The packet and each output packet from each output line of the protection system corresponding to each output line of the operation system are multiplexed by using the first clock having a speed higher than the transmission speed of the input packet. When the multiplexed packet is stored in the buffer at the first clock and the multiplexed packet is read out, a plurality of (N) output means for reading out at the same transmission speed as the input packet are provided. When a system switching request is given to the standby system, the plurality of (N) input lines are switched to the standby system and connected, and the reading of packets from each buffer of the standby system is performed by the read control. When a packet-less state is detected by the detecting means in each of the input buffers of the operating system, the packet remaining in the operating system is given to the corresponding output means from any output line, and The read suspension of the packets in the standby input buffer corresponding to the input buffer without a packet in the active system is released, and the above-mentioned each corresponding to the multiplexing of the output packet from the standby system and the packet remaining in the active system An input buffer type switch device characterized in that output means outputs each packet. 2. When all the input buffers of the active system are in a state of no packet after the plurality of (N) input lines are switched from the active system to the standby system and are connected, Each output means stores only each packet supplied from each output line of the backup system in each corresponding buffer using a second clock having the same speed as the transmission speed of the input packet. Item 3. The input buffer type switch device according to Item 1.