JPH06233277A - Picture encoder - Google Patents

Abstract

PURPOSE:To provide the picture encoder at a low price. CONSTITUTION:In the picture encoder in which a motion detecting part, an interframe differential unit, a DCT part, and a variable length encoder are constituted of one LSI, a RAMC 101 to store the blocks of the Y-signal and the C-signal of a present frame, the RAMR 102 to store the block searching area of the Y-signal of the frame, and the RAMB 103 to store the blocks of the Y-signal and the C-signal corresponding to a detected motion vector are provided, and processing to input a video signal to both the RAMC 101 and the RAMR 102, the processing to detect the motion of the Y-signal stored in both the RAMC 101 and the RAMR 102 by using the motion detecting means 104, the processing to encode by using the Y-signal and the C-signal stored in both the RAMC 101 and the RAMB 103 by an interframe predicting means and a converting and encoding means, and the processing to output an encoded result are operated simultaneously in parallel at every continuous macroblock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image coding apparatus for coding a video signal composed of a luminance signal and a color difference signal.

[0002]

2. Description of the Related Art Image coding is based on JPE as an international standard.
G, H. 261, MPEG is known. JPEG,
H. 261 and the MPEG algorithm are described in, for example, "International Standard of Multimedia Encoding Hiroshi Yasuda Maruzen Co., Ltd. 1991, pp. 14-155". In these coding methods, an image composed of a luminance signal and a color difference signal is coded in units of 64 pixels, which is called a block and is 8 bits per pixel and 8 pixels square. Below, the luminance signal is Y
Signals and color difference signals are referred to as C signals. H.264, which is a moving image coding system. In H.261 and MPEG, motion compensation, inter-frame prediction, orthogonal transformation and variable length coding are used. The motion compensation and the inter-frame prediction reduce the amount of information by using the block that best matches the four blocks of 16 pixels square of the Y signal of the current frame of the previous frame, and generally, whether the motion detection and the motion compensation are performed or not. It is realized by such determination, inter-frame difference, and creation of a previous frame image. In the motion detection, matching between the block of the current frame Y signal and the block of the previous frame is obtained by, for example, the sum of absolute difference between pixels in the block, and the vector with the best matching is output from the search area. For details, refer to Japanese Patent Laid-Open No. 3-340944 or "Digital Signal Processing of TV Image, Fukigaki, Nikkan Kogyo Shimbun Ltd., 1988, pp. 201-207".
There is a description in. The determination algorithm for whether or not to perform motion compensation is, for example, “L64760 Int of LSI Logic Company”.
er-Frame Processor Data Book p
p. 6 ”.

Orthogonal transform coding is a discrete cosine transform (DC
T) is used, and the calculation method of DCT is described, for example, in "Image Coding Technology-DCT and Its International Standard KR Rao Translated by Hiroshi Yasuda Ohmsha 1992". Huffman coding is used in variable-length coding.

The input signal is regulated by the encoding method, and for example, H.264. 261 is a CIF signal (360 × 288)
Pixel, 1 pixel 8 bits, 30 frames per second) as input, 4 blocks of Y signal and 2 blocks of C signal called macro block
The above algorithm is executed for each block.

In the conventional image coding apparatus, an LSI for detecting a motion vector for motion compensation (hereinafter, referred to as a motion detection LSI) and an LSI for performing DCT (hereinafter, DCT).
(Referred to as LSI) is a different LSI.

FIG. 3 shows an H.264 codec of a moving picture coding apparatus using a motion detection LSI and a DCT LSI. 261 shows a general configuration example when realizing the H.261. The moving picture coding apparatus of FIG. 3 has a current frame memory 301 and a current frame memory 30.
Difference unit 30 connected to 1 and performing difference in block units
2. DCT LSI 303 connected to the difference unit 302, which can calculate DCT and inverse DCT by changing coefficient values,
A quantizer 304 connected to the DCT LSI 303 for quantizing DCT coefficients, a motion detection LSI 305 connected to the current frame memory 301, and an inverse quantizer connected to the quantizer 304 for converting a quantized value into a DCT coefficient. Inverse DCTL, which is connected to the inverse quantizer 306 and obtains a value for each pixel from the DCT coefficient of the block by inverse DCT calculation
SI 307, previous frame memory 308 for storing blocks output from inverse DCT LSI 307, quantizer 30
4, a variable length encoder 309 for Huffman encoding a quantized value, a determination as to whether or not motion compensation is to be performed, and on / off control of a differentiator and control of a quantization parameter according to the determination result. The controller 310 is provided.

The operation of the encoder will be described with reference to FIG.

First, a Y signal used for motion detection is input from the current frame memory 301 to the motion detection LSI 305 in blocks, and at the same time, the area in which the block searches for a motion vector is searched from the previous frame memory 308 from the motion detection LSI 3.
Enter in 05. Next, the block of the Y signal and the C signal stored in the previous frame memory 308 corresponding to the motion vector output from the LSI, and the current frame memory 301
The block of the Y signal and the block of the C signal stored in is input to the differentiator 302, and the difference result is input to the DCT LSI 303. Next, the quantizer 304 quantizes the DCT coefficient output from the DCT LSI 303. Finally, after the quantized value is inversely quantized by the inverse quantizer 306, the inverse DCT LSI 3
At 07, the DCT coefficient is converted into a pixel value and written in the previous frame memory 308 in block units. At the same time, the quantized value is encoded by the variable length encoder 309, and the encoded result is output.

A specific example of a moving picture coding apparatus in which motion detection and transform coding are separated will be given. LSI Logic Co., Ltd. is an IEEE Transactions on Ci
rcuits and Systems for Vi
Deo Technology (June 1992 pp.111-122) in CCITT H. et al. Two
We have announced a 61-compliant image coding chipset,
This realizes motion detection and transform coding by different LSIs.

Graphic Communications Technology Co., Ltd. is a member of IEEE Transactions.
on Circuits and Systems
for Video Technology (June
1992 pp. 123-133) in CCI
TT H. An image coding chip set conforming to 261 has been announced.

The SGS Thomson Company is the IEEE Euro
ASIC Conference (1991 p
p. 96-99) motion detection LSI STI32
20 and Discrete Cosine Transformation LSI STV3208 are announced.

In the encoding device having the configuration shown in FIG. 3, the following three inputs and outputs are required for the previous frame memory 308.

(1) Y signal output within the motion vector search range (2) Y signal and C which are collated after the motion vector is determined
Output of signal (3) Input of Y signal and C signal after inverse DCT Here, for example, for a block of Y signal 16 × 16 pixels and C signal 8 × 8 pixel when encoding the CIF signal, (1 ) To (3) indicate the required data amount. (1)
The amount of data of H. Assuming -16 pixels to +15 pixels that can be coded by H.261, 48 * 48 = 2,304 bytes. A conceptual diagram of the search range at this time is shown in FIG. Figure 6 shows 16x16
Search ranges 601, 602, 603 of the block 605 of
48 consisting of 604, 606, 607, 608, 609
A pixel area of × 48 and a search range 604 of a block 608,
605, 606, 607, 608, 609, 610, 6
A 48 × 48 area consisting of 11, 612 is shown.
Of the search range, the adjacent blocks 604, 60
5, 606, 607, 608 and 609 are shared search ranges, and 610, 611 and 612 excluding the shared range are pixel data that need to be updated. The data that needs to be updated is 48 × 16 = 768 bytes. The data amount of (2) is 16 × 16 + 8 × 8 × 2 = 384 bytes. The data amount of (3) above is 16 × 16 + 8 × 8 × 2 =
It is 384 bytes.

In the conventional pixel encoder for which motion detection and DCT are not one chip, the number of chips is larger than that of one chip and the amount of input / output data to / from the previous frame memory is large, which is high speed. -Large capacity RAM is required, and the device including these is expensive.

[0015]

SUMMARY OF THE INVENTION In order to reduce the cost of an image coding apparatus, some functions are integrated into an LSI.
A method of reducing the number of points and a method of using a low-speed external frame memory are effective.

As a first solution, when the motion detection and the transform coding are realized by one LSI, the data transfer amount between the previous frame memory and the present LSI is reduced, and the motion detection is performed on the LSI. The challenge is to reduce the amount of memory in as much as possible. IIT is an IEEE Custom
m Integrated Circuits Con
In Fence (1991 No. 12.3.1), an LSI in which motion detection and conversion coding are integrated into one chip has been announced. The method (2) for reducing the transfer memory amount of the Y signal and the method (2) ), The method of performing the data transfer of the C signal is not described.

When the motion detection and the transform coding are realized by one LSI, it is not clear how to configure the Y signal and the C signal in the search range of the motion detection with as few memories on the LSI as possible. There wasn't. For example, the simple method of simultaneously inputting the Y signal and the C signal in the motion vector search range to the LSI has a drawback that the memory area for the C signal that does not need to be used for motion detection is wasted.

As a second solution, in order to use a low-speed frame memory, an input process, a motion detection process,
There is a method in which the conversion encoding process and the data output process to the next stage are simultaneously operated in parallel. The LSI of IIT does not specifically show the second solution.

An object of the present invention is to provide a low cost image coding apparatus.

[0020]

An image coding apparatus according to the present invention comprises a motion detecting means, an inter-frame predicting means, and a transform coding means, and codes a video signal composed of a luminance signal and a color difference signal. An image encoding device for performing, a first memory for storing a video signal of a current frame, a second memory for storing a search area of a luminance signal of a previous frame for motion detection, and a luminance of a motion detection result. A third memory for storing areas of signals and color difference signals, and the motion detection means detects motions of the brightness signals stored in the first memory and the second memory, and the first memory and the third memory It is characterized in that it is coded by an inter-frame prediction means and a transform coding means using a memory.

Further, the process of inputting the video signal into the first memory and the second memory, and the motion detection of the luminance signal stored in the first memory and the second memory by using the motion detecting means. Processing, encoding processing by the inter-frame prediction means and transform encoding means using the luminance signal and color difference signals stored in the first memory and the third memory, and processing for outputting the encoding result. May be provided with a control means for operating in parallel.

[0022]

In the image coding apparatus of the present invention, when the motion is detected, the Y stored in the first memory and the second memory is stored.
Block matching is performed on the signal using the motion detection means. The Y signal transfers the block corresponding to the obtained motion vector from the second memory to the third memory. The C signal transfers the block corresponding to the motion vector from the previous frame memory to the third memory. For inter-frame prediction and transform coding, Y stored in the first memory and the third memory
Signal and C signal are used.

In the encoding device, a process of inputting the video signal into the first memory and the second memory, and a motion detecting means for the Y signal stored in the first memory and the second memory are provided. A process of detecting a motion using the process, a process of encoding the inter-frame prediction unit by the conversion encoding unit using the Y signal and the C signal stored in the first memory and the third memory, and an encoding result. The output processing can be simultaneously and concurrently operated for each continuous macroblock. The encoding process contents are as follows.

(STEP 1) The Y signal and the C signal are transferred from the external frame memory to the first memory.

(STEP 2) The Y signal is transferred from the external frame memory to the second memory.

(STEP 3) Motion is detected using the Y signals of the first and second memories.

(STEP 4) The block of the Y signal corresponding to the motion vector is transferred from the first memory to the third memory.

(STEP 5) Motion compensation judgment is performed.

(STEP 6) The difference between the Y signals in the first and third memories and the transform coding are performed.

(STEP 7) The block of the C signal corresponding to the motion vector is transferred from the external frame memory to the third memory.

(STEP 8) The difference between the C signals in the first and third memories and the transform coding are performed.

(STEP 9) The Y signal and C signal encoding results are output.

For a certain macroblock m, the time [0
~ T], STEP1 and STEP2 are executed.
STEP3 and STEP4 are performed in time [T-2T]. STEP5 and ST at time [2T-3T]
Steps EP6, STEP7, and STEP8 are executed. Time [3
[T-4T], STEP 9 is executed.

[0034]

EXAMPLES The present invention will be described below based on examples.

FIG. 2 shows an example of the structure of the image coding apparatus of the present invention. The image coding apparatus shown in FIG. 2 has a current frame memory 201 that receives image data, an encoder 202 connected to the current frame memory 201, a previous frame memory 203 connected to the encoder 202, and an encoder 202. And a variable length coding unit 204 connected to the. The encoder 202, as shown in FIG.
Memory RAM connected to 1 and supplied with macroblocks
C101, memory RAMR102 connected to the previous frame memory 203, memory R connected to RAMR102
AMB103, current frame memory 201 and RAMC1
01 and the RAMR 102 connected to the motion detector 10
4, the difference unit 105 connected to the current frame memory 201 and the RAMB, the difference unit 105 and the previous frame memory 2
03, DCT calculator 106, DCT calculator 1
Quantizer / Dequantizer 107 connected to 06, RAMR
102, a motion detector 104, a difference unit 105, and a controller 108 connected to the quantizer / inverse quantizer 107.

First, the H.264 standard international image coding method for coding in 8 × 8 block units. 261 is shown in FIG.
It will be described with reference to FIGS. 2 and 4.

First, a macro block composed of a total of 6 blocks of 4 Y signal blocks and 2 C signal blocks is input from the current frame memory 201 to the RAM C 101 (step S1). At the same time, all the pixels in the range in which the Y signal block is subjected to motion search are read from the previous frame memory 203 to RAMR1.
02 (step S2). If the motion search range of the Y signal block is set to −16 to +15 in both the horizontal and vertical directions, the 48 × 48 Y signal including the Y signal block becomes R.
It is stored in the AMR 102.

Next, block matching is performed using the RAMC 101 and the RAMR 102 to detect the motion vector of the Y signal (step S3). R of the Y signal block matching the obtained motion vector from RAMR 102
The data is transferred to the AMB 103 (step S4).

Next, it is determined whether or not the motion compensation is performed using the Y signals of the RAMC 101 and the RAMB 103 (step S5). If it is determined that motion compensation will be performed, RAMB
The block of the C signal corresponding to the motion vector is input from the external previous frame memory 203 to 103 (step S
6). RAMC101 to RAMB103 Y signal and C
The signals are differentiated (step S7) and input to the DCT unit 106. If it is determined that motion compensation is not performed, the RAMC10
The block of Y and C signals of 1 is input to the DCT unit 106.

Next, DCT calculation is performed (step S
8). Next, the DCT output value is quantized (step S9),
Variable length coding is performed (step S10), and a bit string is output (step S11).

The quantized output value is inversely quantized (step S
12) and inverse DCT is performed (step S13).

Finally, in the case of interblock, inverse DC
Since the Y and C signals of the T result are difference values, RA
The value is added to the value of MB 103 (step S15) and output to the previous frame memory 203 to update the contents of the frame memory (step S16). In the case of an intra block, the output value of the inverse DCT is output to the previous frame memory 203 and the content is updated (step S16).

When the procedures described above are sequentially performed, steps S1, S2, S6, S11 and S15 are input / output with the outside. In order to use the low-speed RAM for the frame memory, the encoder is operated in parallel with each macro block.

FIG. 5 shows an example of concurrent operation of the encoder at 202. For example, steps S1 and S2 are the first step, steps S3, S4, and S5 are the second step, and steps S6, S7, S8, S9, S12, S13, and S14.
Is executed in the third step and step S15 is executed in the fourth step. This is the LSI from the external frame memory of the macro block.
It is shown that the input processing to, the motion detection processing and the transform coding processing, the output processing from the LSI to the external frame memory, and the output processing to the variable length coding are simultaneously operating in parallel. 20 in steps S10 and S11
4 variable length coding unit.

Consecutive macroblocks m-3, m-2,
The processing procedure for m-1, m, m + 1, m + 2, m + 3 is shown in FIG.
Will be explained.

At time (n + 1) T, the macro block m-3 finishes executing step S15, and the macro block m-2 executes steps S6, S7, S8, S9, S12 and S.
13 and S14 are ended, the macroblock m-1 ends steps S3, S4, and S5, and the macroblock m ends steps S1 and S2.

At time (n + 2) T, the macro block m-2 finishes executing step S15, and the macro block m-1 executes steps S6, S7, S8, S9, S12 and S.
13 and S14 are completed, the macroblock m completes steps S3, S4, and S5, and the macroblock m +
1 ends execution of steps S1 and S2.

At time (n + 3) T, the macro block m-1 finishes executing step S15, and the macro block m executes steps S6, S7, S8, S9, S12 and S1.
3 and S14 are completed, the macroblock m + 1 finishes execution of steps S3, S4, and S5, and the macroblock m + 1 is completed.
+2 ends execution of steps S1 and S2.

At time (n + 4) T, the macroblock m finishes executing step S15, and the macroblock m +
1 is steps S6, S7, S8, S9, S12, S1
3 and S14 are completed, the macroblock m + 2 finishes execution of steps S3, S4, and S5, and the macroblock m + 2 is completed.
For +3, execution of steps S1 and S2 ends.

In the conventional image coding apparatus as shown in FIG. 3, 256 bytes of the RAMB 103 need to be accessed to the external frame memory, but according to the present invention, S4 is used.
In Y, since the Y signal is transferred between the on-chip memories, access to the external previous frame memory 203 becomes unnecessary.

When the search range of the motion vector is set to -16 to +15 pixels in the horizontal / vertical direction, 1 is used in the conventional method.
The amount of input / output data required in the previous frame memory per macroblock is 768 bytes from (1), 384 bytes from (2), and 384 bytes from (3), so 768 + 384 + 384 = 1536 (bytes).

According to the present system, the amount of input / output data is 768 + 128 + 384 = 1280 (bytes) due to motion detection and conversion coding on one chip.

Therefore, when it is realized by one LSI, the data access amount to the previous frame memory can be reduced by 16% and a low speed RAM can be used.

Next, the effect obtained by externally inputting a C signal which is not used for motion detection to the RAMB in the case of one chip is shown.

RAMR searches the search range horizontally and vertically--
Since 16 to +15 pixels, the required memory amount of the Y signal on the LSI is 12 times the square of 16 pixels, and (16 + 16 + 16 + 16) × (16 + 16 + 16) =
3072 (bytes).

There are two types of the data amount of the C signal on the LSI, that is, 12 times the square of 8 pixels, (8 + 8 + 8 + 8) × (8 + 8 + 8) × 2 = 1536
(Part-Time Job).

RAMC is 16 × 16 + 8 × 8 × 2 = 384 (bytes).

RAMB has 16 × 16 + 8 × 8 × 2 = 384 (bytes).

The total amount of on-chip memory is 53 in the conventional system.
This is 76 bytes, and since the C signal of RAMR is not necessary in this method, it is 3840 bytes, so a reduction of 29% is possible compared to the conventional method.

According to the present invention, the motion detection and the transform coding are realized by one LSI, the data transfer amount with the previous frame memory is reduced, and the cost of the RAM used for the previous frame memory is reduced. Further, since the data of the C signal irrelevant to the motion detection is not mounted on the LSI, the on-chip memory is reduced.

From the above, according to the present invention, it is possible to reduce the number of LSIs of the image coding apparatus and to realize the cost reduction of the apparatus by using the low-speed RAM.

[0062]

The image coding apparatus of the present invention comprises the motion detecting means, the inter-frame predicting means, and the transform coding means, and codes the video signal composed of the luminance signal and the color difference signal. The device is a first memory for storing a video signal of a current frame, a second memory for storing a search area of a luminance signal of a previous frame for motion detection, a luminance signal and a color difference signal of a motion detection result. And a third memory for storing the area of the first memory, and the motion detecting means performs motion detection of the luminance signals stored in the first memory and the second memory,
Since it is encoded by the inter-frame predicting means and the transform encoding means using the memory and the third memory, the motion detecting section, the inter-frame difference section, the DCT section and the variable length encoder can be realized by one LSI. . Therefore, a low-cost image coding apparatus can be provided.

Further, the process of inputting the video signal into the first memory and the second memory and the motion detection of the luminance signal stored in the first memory and the second memory by using the motion detecting means. Processing, encoding processing by the inter-frame prediction means and transform encoding means using the luminance signal and color difference signals stored in the first memory and the third memory, and processing for outputting the encoding result. Since it is provided with a control means for operating in parallel, it is possible to use a low-speed memory. Therefore, a low-cost image coding apparatus can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of an encoder of an image encoding device of the present invention.

FIG. 2 is a block diagram showing a configuration of an embodiment of an image encoding device of the present invention.

FIG. 3 is a block diagram showing a configuration of an embodiment of a conventional image encoding device.

FIG. 4 is a diagram illustrating a moving picture coding method H.264 using FIG. 26
It is a flowchart when realizing 1.

5 is a video encoding method H.264 using FIG. 1 and FIG. 26
2 is an example of a pipeline operation for realizing 1.

FIG. 6 is a map showing a configuration of an embodiment of RAMR in FIG.

[Explanation of symbols]

 101, 102, 103 RAM 104 motion detection unit 105 difference unit 106 DCT calculator 107 quantizer 108 control unit 201, 203 frame memory 202 encoder 204 variable length encoding unit

Claims (2)

[Claims] 1. An image coding apparatus, comprising a motion detecting means, an inter-frame predicting means, and a transform coding means, for coding a video signal composed of a luminance signal and a color difference signal,
A first memory that stores a video signal of the current frame, a second memory that stores a search region of a luminance signal of a previous frame for motion detection, and a region of a luminance signal and a color difference signal of a motion detection result are stored. A third memory, the motion detecting means detects motion of the luminance signals stored in the first memory and the second memory, and the inter-frame predicting means uses the first memory and the third memory. And an image coding device characterized by coding by a transform coding means. 2. A process of inputting the video signal to a first memory and a second memory, and motion detection of a luminance signal stored in the first memory and the second memory using a motion detecting means. Processing, encoding processing by the inter-frame prediction means and transform encoding means using the luminance signal and color difference signals stored in the first memory and the third memory, and processing for outputting the encoding result. The image coding apparatus according to claim 1, further comprising a control unit that operates the and the same in parallel.