JPH06232344A - Capacitor of semiconductor device - Google Patents
Capacitor of semiconductor deviceInfo
- Publication number
- JPH06232344A JPH06232344A JP5309547A JP30954793A JPH06232344A JP H06232344 A JPH06232344 A JP H06232344A JP 5309547 A JP5309547 A JP 5309547A JP 30954793 A JP30954793 A JP 30954793A JP H06232344 A JPH06232344 A JP H06232344A
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- film
- electrode
- semiconductor device
- dielectric film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/0254—Nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
(57)【要約】 (修正有)
【目的】 半導体装置のキャパシタを提供する。
【構成】 前記第1電極11の上部に高誘電物質及び強
誘電物質の中から選択されたいずれか一つで製造された
誘電体膜13及び前記誘電体膜の上部に耐熱性金属膜又
は耐熱性金属の窒化膜の中から選択されたいずれか一つ
及びその上部に形成された緩衝膜を備える第2電極1
4,15を具備する半導体装置のキャパシタである。こ
れにより、製造工程の中熱負荷による特性の劣化が防止
され優れた特性を有する。
(57) [Summary] (Modified) [Objective] To provide a capacitor for a semiconductor device. A dielectric film 13 made of one of a high dielectric material and a ferroelectric material is formed on the first electrode 11, and a heat-resistant metal film or a heat-resistant metal film is formed on the dielectric film 13. Second electrode 1 having any one selected from a nitride film of a functional metal and a buffer film formed thereon
4 and 15 are capacitors of a semiconductor device. As a result, the characteristics are prevented from deteriorating due to the intermediate heat load in the manufacturing process, and excellent characteristics are provided.
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体装置のキャパシタ
に係り、特に五酸化タンタル( Ta2O5;tantalum pento
xide)キャパシタに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device capacitor, and more particularly to tantalum pentoxide (Ta 2 O 5 ; tantalum pento).
xide) capacitors.
【0002】[0002]
【従来の技術】半導体基板に形成されている記憶装置と
して一つのMOS(metal oxide semiconductor )トラ
ンジスタと一つのMOSキャパシタでメモリセルが構成
されるDRAMにおいては、MOSキャパシタに電荷が
蓄積されているか否かにより情報の記憶が成され、又M
OSトランジスタを媒介としビットラインにMOSキャ
パシタの電荷を放出しその電位変化を検出する方法によ
り情報の判読が成される。2. Description of the Related Art As a memory device formed on a semiconductor substrate, in a DRAM in which a memory cell is composed of one MOS (metal oxide semiconductor) transistor and one MOS capacitor, whether or not charges are accumulated in the MOS capacitor. Information is stored by the
Information can be read by a method of discharging charges of a MOS capacitor to a bit line through an OS transistor and detecting a potential change thereof.
【0003】DRAMにおいてセルキャパシタンスの増
加はメモリセルの読み出し能力を向上させソフトエラ−
率を減少させる役割をするのでセルメモリの特性を向上
させることに大きく寄与する。ところが、DRAM集積
度は約3年毎に4倍ずつ増加しているのに比べチップの
面積は 1.4倍に止まり相対的にメモリセルの面積は1/
3倍減るが、単位セルで要求するセルキャパシタンスは
一定するので、結果的にセルキャパシタンスの減少によ
るメモリ装置の電気的特性が低下する問題が発生する。In the DRAM, the increase of the cell capacitance improves the read capacity of the memory cell and causes a soft error.
Since it plays a role of reducing the rate, it greatly contributes to improving the characteristics of the cell memory. However, while the DRAM integration has increased four times every three years, the area of the chip is only 1.4 times, and the area of the memory cell is 1 / relatively.
Although the cell capacitance required by the unit cell is constant, the cell capacitance is reduced, resulting in a decrease in electrical characteristics of the memory device due to the decrease in cell capacitance.
【0004】既存のキャパシタ構造では限定された面積
内で十分に大きいセル容量が確保できないので、セル容
量を増加させるためにキャパシタの面積を増加させるこ
とが望ましい方法として提案されている。即ち、キャパ
シタの構造を3次元で形成する多くの方法が提案されて
いる。トレンチ形のキャパシタ、スタック形のキャパシ
タ及びスタック−トレンチ併合形のキャパシタは3次元
的なキャパシタの代表的な構造である。ところが、トレ
ンチ形のキャパシタは大きい容量のキャパシタンス確保
のためには有利であるが、トレンチとトレンチ間の漏洩
電流やトレンチの表面に存するMOS寄生トランジスタ
のような複雑な寄生トランジスタにより素子特性が減少
し又製造工程が非常に厳しいという短所がある。反面、
スタック形のキャパシタはトレンチ形に比べ寄生トラン
ジスタが少なく製造工程が容易であるという長所がある
が、十分な静電容量が得られず高集積化に不利であっ
た。従って、素子製造工程が簡単でありながらも大きい
セルキャパシタンスが確保できる新しいキャパシタが要
求された。Since the existing capacitor structure cannot secure a sufficiently large cell capacity within a limited area, it has been proposed to increase the area of the capacitor in order to increase the cell capacity. That is, many methods for forming a capacitor structure in three dimensions have been proposed. A trench type capacitor, a stack type capacitor, and a stack-trench merged type capacitor are typical structures of a three-dimensional capacitor. However, the trench capacitor is advantageous for securing a large capacitance, but the device characteristics are reduced due to the leakage current between the trenches and complicated parasitic transistors such as MOS parasitic transistors existing on the surface of the trenches. In addition, the manufacturing process is very strict. On the other hand,
The stack type capacitor has an advantage that the number of parasitic transistors is smaller than that of the trench type and the manufacturing process is easy, but it is disadvantageous for high integration because a sufficient capacitance cannot be obtained. Therefore, a new capacitor that can secure a large cell capacitance while requiring a simple device manufacturing process has been required.
【0005】セル容量を増加させるための他の方法とし
ては誘電体膜の厚さを薄くしたり誘電率の大きい絶縁膜
を使用する方法等がある。この中で誘電膜を薄くするの
は半導体装置の信頼性を減少させるので望ましくないこ
とと見なされている。既存のキャパシタ誘電体膜に使用
される物質である酸化物、ONO(oxide/nitride/oxid
e) 、NO(nitride/oxide) 等は物質自体の誘電率が少
ないので(oxide の場合約 3.8、nitride の場合約 7.
8)次世代64M級以上のDRAMに適用する時構造が
非常に複雑になったり厚さが薄くなり信頼性が低いとい
う問題がある。これを改善するために高誘電物質や強誘
電物質をキャパシタの誘電体膜の製造に使用する。例と
しては Ta2O5、PLZT、PZT等があるが特に Ta2O5
を誘電体膜の製造に導入しようとする研究が活発に進行
されている。As another method for increasing the cell capacity, there is a method of reducing the thickness of the dielectric film or using an insulating film having a large dielectric constant. Among them, thinning the dielectric film is considered to be undesirable because it reduces the reliability of the semiconductor device. ONO (oxide / nitride / oxid), which is a material used for existing capacitor dielectric films
e), NO (nitride / oxide), etc. have a low dielectric constant of the substance itself (about 3.8 for oxide and about 7. for nitride).
8) When applied to the next generation DRAM of 64M class or higher, there is a problem that the structure becomes very complicated and the thickness is thin and the reliability is low. In order to improve this, a high dielectric material or a ferroelectric material is used for manufacturing a dielectric film of a capacitor. Examples include Ta 2 O 5 , PLZT, PZT, etc., but especially Ta 2 O 5
Research into introducing dielectrics into the production of dielectric films is actively underway.
【0006】ソニ−社では C.Isobe and M.saitoh が A
ppl. Phys.Lett.,vol.56,No.10, pp907 〜 909, 1990年
に“Effect of ozone annealing on the dielectric p
roperties of tantalum oxide thin films grown by ch
emical vapor deposition ”を発表し、シャ−プ社では
Koji Yamagishi 等が IEEE Transaction on electron
device, p2439 , 1988で“Stacked capacitor DRAM pr
ocess using photo-CVD Ta2O5 film”を開示し、日立社
では H. Shinriki等が Tech. Dig. Symp. VLSITech., p
p25〜26, 1989で“Leakage currentreduction and r
eliability improvement of effective 3nm-thick CVD
Ta2O5 film by two-step annealing”を発表した。At Sony Corporation, C. Isobe and M. saitoh are
ppl. Phys. Lett., vol.56, No.10, pp907 ~ 909, 1990 “Effect of ozone annealing on the dielectric p
roperties of tantalum oxide thin films grown by ch
"Shamp Vapor Deposition" was announced at Sharp Corporation.
Koji Yamagishi and others are IEEE Transaction on electron
device, p2439, 1988 “Stacked capacitor DRAM pr
ocess using photo-CVD Ta 2 O 5 film ”and Hitachi. H. Shinriki et al. Tech. Dig. Symp. VLSITech., p.
p25-26, 1989 “Leakage current reduction and r
eliability improvement of effective 3nm-thick CVD
Ta 2 O 5 film by two-step annealing ”was announced.
【0007】ところが、誘電体膜として前記した Ta2O5
のような誘電率の大きい物質を使用すれば誘電率は高い
が、薄膜状態で漏洩電流が高く破壊電圧が低い等の問題
点があり未だ実用化段階には達していない実情である。
これに対し更に詳細に見れば次の通りである。キャパシ
タ誘電膜としてTa2O5 の電気的な特性はキャパシタの電
極材料に依存し、一番良い電気的特性を有する電極材料
は TiNと知られている。 キャパシタの誘電体膜として
Ta2O5 を使用し電極材料として TiNを使用する場合、工
程の適合性のために通常の下部電極は多結晶シリコンを
使用し、上部電極は TiNを使用する。しかしながら、 T
iN電極は多結晶シリコン電極に比べ電気的特性の改善さ
れたTa2O5 誘電体膜を形成させるが、Ta2O5 形成後にD
RAM製造工程で必須工程であるBPSG(borophosph
o-silicate glass)リフロ−工程(通常、約 850℃の温
度で約30分の間遂行される)を経ればキャパシタが劣
化される。従って、 TiN電極の下部にTa2O5 誘電体膜を
形成させたキャパシタの製造においては後続く熱処理工
程に安定した工程の開発が必須である。However, the above-mentioned Ta 2 O 5 is used as the dielectric film.
If a substance having a large dielectric constant such as the above is used, the dielectric constant is high, but there are problems such as high leakage current and low breakdown voltage in a thin film state, and it is a fact that it has not yet reached the stage of practical use.
On the other hand, the details are as follows. The electrical characteristics of Ta 2 O 5 as a capacitor dielectric film depend on the electrode material of the capacitor, and the electrode material with the best electrical characteristics is known as TiN. As a dielectric film for capacitors
When Ta 2 O 5 is used and TiN is used as the electrode material, polycrystalline silicon is used as the usual lower electrode and TiN is used as the upper electrode because of process compatibility. However, T
The iN electrode forms a Ta 2 O 5 dielectric film with improved electrical characteristics compared to the polycrystalline silicon electrode, but after the Ta 2 O 5 formation, D
BPSG (borophosph), which is an essential process in the RAM manufacturing process
An o-silicate glass) reflow process (typically performed at a temperature of about 850 ° C. for about 30 minutes) deteriorates the capacitor. Therefore, in manufacturing a capacitor in which a Ta 2 O 5 dielectric film is formed under the TiN electrode, it is essential to develop a stable process for the subsequent heat treatment process.
【0008】図1は下部電極1に多結晶シリコンを使用
し、上部電極3に TiNを使用し誘電体膜2にTa2O5 を使
用した従来のキャパシタを示した。前記キャパシタ形成
後のBPSGリフロ−工程による誘電体膜の劣化現象を
従来の技術を参照して説明すれば次の通りである。図2
は従来の技術であり高誘電物質 Ta2O5をキャパシタの誘
電体膜として使用し下部電極は多結晶シリコン、上部電
極は TiNで形成したキャパシタ、即ち TiN/ Ta2O5/Poly
-Si システムでの印加された有効電界と漏洩電流との関
係を示した。図面でBPSGリフロ−前の特性を示す
が、グラフaは350℃、bは390℃、cは410℃
及びdは430℃以上の蒸着温度に対応する特性であ
り、gはBPSGリフロ−の後、+&−バイアスの全て
において、全ての蒸着温度での特性を示す。この場合、
最適条件である350℃で蒸着された Ta2O5膜の例を挙
げれば、BPSGリフロ−をしていない蒸着された状態
で±5MV/cmの有効電界で10-8A/cmの漏洩電流を示す
が、650℃以上の温度でBPSG熱処理工程を経れば
漏洩電流が10A/cm以上に増加する。FIG. 1 shows a conventional capacitor in which polycrystalline silicon is used for the lower electrode 1, TiN is used for the upper electrode 3, and Ta 2 O 5 is used for the dielectric film 2. The deterioration phenomenon of the dielectric film due to the BPSG reflow process after forming the capacitor will be described with reference to the related art. Figure 2
Is a conventional technology, in which a high dielectric material Ta 2 O 5 is used as a dielectric film of a capacitor, a lower electrode is made of polycrystalline silicon, and an upper electrode is made of TiN, that is, TiN / Ta 2 O 5 / Poly.
The relationship between the applied effective electric field and the leakage current in the -Si system is shown. In the drawing, the characteristics before BPSG reflow are shown. Graph a is 350 ° C, b is 390 ° C, and c is 410 ° C.
And d are the characteristics corresponding to the vapor deposition temperature of 430 ° C. or higher, and g is the characteristic at all the vapor deposition temperatures after the BPSG reflow and in all + & − biases. in this case,
An example of Ta 2 O 5 film deposited at 350 ° C. which is the optimum condition is as follows: Leakage current of 10 −8 A / cm at effective electric field of ± 5 MV / cm without BPSG reflow. The leakage current increases to 10 A / cm or more when the BPSG heat treatment process is performed at a temperature of 650 ° C. or more.
【0009】前記したようなBPSGリフロ−等の熱処
理によるキャパシタの劣化はTa2O5の蒸着温度と関係な
く発生する。現在Ta2O5 がDRAM製造工程で実際的に
適用されていない理由は後続く熱処理により前記のよう
にキャパシタが劣化するためである。しかしながら、Ta
2O5 を誘電体膜に使用したキャパシタの上部電極及び下
部電極を以て多結晶シリコンを使用する場合、熱処理工
程をしていない蒸着された状態でのTa2O5 の電気的な特
性は TiNを電極として使用したキャパシタより悪くない
がBPSGリフロ−後の特性劣化は一層少ない。The deterioration of the capacitor due to the heat treatment such as the BPSG reflow as described above occurs regardless of the deposition temperature of Ta 2 O 5 . The reason why Ta 2 O 5 is not practically applied in the DRAM manufacturing process at present is that the subsequent heat treatment deteriorates the capacitor as described above. However, Ta
When polycrystalline silicon is used for the upper and lower electrodes of a capacitor that uses 2 O 5 as the dielectric film, the electrical characteristics of Ta 2 O 5 in the as-deposited state without heat treatment are Although not worse than the capacitor used as the electrode, the characteristic deterioration after BPSG reflow is less.
【0010】一方、TiN をキャパシタの電極に利用すれ
ば後続く洗浄工程及び蝕刻工程を金属基準を以て遂行す
べきなので工程の適合性が落ちるという問題点がある。On the other hand, if TiN is used for the electrode of the capacitor, the subsequent cleaning and etching processes should be carried out on the basis of metal, so that the compatibility of the process is deteriorated.
【0011】[0011]
【発明が解決しようとする課題】本発明の目的はBPS
Gリフロ−に従う熱負荷による特性の劣化が防止され性
能の優れた半導体装置のキャパシタを提供することであ
る。SUMMARY OF THE INVENTION The object of the present invention is BPS
It is an object of the present invention to provide a semiconductor device capacitor with excellent performance in which characteristic deterioration due to heat load according to G reflow is prevented.
【0012】[0012]
【課題を達成するための手段】前記目的を達成するため
に本発明では、第1電極、前記第1電極の上部に形成さ
れた誘電体膜及び前記誘電体膜の上部に形成された第2
電極を具備する半導体装置のキャパシタにおいて、前記
誘電体膜が高誘電物質及び強誘電物質の中から選択され
たいずれか一つで製造されたものであり、前記第2電極
は耐熱性金属膜又は耐熱性金属の窒化膜の中から選択さ
れたいずれか一つ及びその上部に形成された緩衝膜より
なることを特徴とする半導体キャパシタを提供する。To achieve the above object, the present invention provides a first electrode, a dielectric film formed on the first electrode, and a second film formed on the dielectric film.
In a capacitor of a semiconductor device having an electrode, the dielectric film is made of one of a high dielectric material and a ferroelectric material, and the second electrode is a heat resistant metal film or Provided is a semiconductor capacitor comprising one of heat-resistant metal nitride films and a buffer film formed on the selected one.
【0013】前記第1電極は多結晶シリコンより成され
たり、前記多結晶シリコンの上部にTiN、Ti、W 、TiW
、Pt及びPdよりなる群から選択された少なくとも一つ
の耐熱性金属、あるいはその化合物よりなる層が形成さ
れるのが望ましい。又、前記多結晶シリコンは望ましく
不純物のドープされた多結晶シリコン又は POCl3処理さ
れた多結晶シリコンを使用する。The first electrode is made of polycrystalline silicon, and TiN, Ti, W, and TiW are formed on the polycrystalline silicon.
Preferably, a layer of at least one refractory metal selected from the group consisting of Pt, Pt and Pd, or a compound thereof is formed. The polycrystalline silicon is preferably polycrystalline silicon doped with impurities or polycrystalline silicon treated with POCl 3 .
【0014】前記第2電極の前記耐熱性金属はTi、W 、
TiW 、Pt、Pd及びAuよりなる群から選択された少なくと
も一つであることが、前記耐熱性金属の窒化膜は TiN、
WN、TiWN及び PtNよりなる群から選択された少なくとも
一つであることが好ましい。前記緩衝膜は多結晶シリコ
ン又はシリサイドであることが望ましいが例としては W
Si、TiSi、TaSi、MoSi、ポリサイド等が挙げられる。The refractory metal of the second electrode is Ti, W,
TiW, Pt, Pd and at least one selected from the group consisting of Au, the nitride film of the refractory metal is TiN,
It is preferably at least one selected from the group consisting of WN, TiWN and PtN. The buffer film is preferably polycrystalline silicon or silicide.
Examples include Si, TiSi, TaSi, MoSi, polycide, and the like.
【0015】前記誘電体膜は Ta2O5、TiO2、HfO2等の高
誘電物質、又はPbTiO3、Pb(Zr,Ti)O 3 等のPZT化合
物、(Pb,La)(Zr,Ti)O3等のPLZT化合物、BaTiO3、Sr
TiO3のようなBST化合物等の強誘電物質より製造され
る。The dielectric film is Ta2OFive, TiO2, HfO2Etc high
Dielectric material or PbTiO3, Pb (Zr, Ti) O 3 PZT compound such as
Thing, (Pb, La) (Zr, Ti) O3PLZT compounds such as BaTiO3, Sr
TiO3Manufactured from ferroelectric materials such as BST compounds
It
【0016】[0016]
【作用】一般に、誘電体膜として高誘電物質及び強誘電
物質の中から選択されたいずれか一つを使用すれば前述
した通りBPSGリフロ−工程を経た後キャパシタが劣
化する問題がある。本発明では、耐熱性金属膜又は耐熱
性金属の窒化膜の中から選択されたいずれか一つよりな
る膜及びその上部に形成された緩衝膜から構成される第
2電極を構成することにより、上記問題を解決する。In general, if one of the high dielectric material and the ferroelectric material is used as the dielectric film, the capacitor deteriorates after the BPSG reflow process as described above. In the present invention, by configuring the second electrode composed of a film made of any one selected from the heat-resistant metal film or the nitride film of the heat-resistant metal and the buffer film formed on the film, The above problem is solved.
【0017】[0017]
【実施例】以下、添付した図面に基づき本発明の実施例
を詳細に説明する。高誘電物質又は強誘電物質よりなる
誘電体膜の上部に耐熱性金属又はこの金属窒化物よりな
る膜を形成することにより誘電体膜との界面特性を向上
させ、前記耐熱性金属又は金属窒化物の上部に緩衝膜を
形成させることにより、後続する熱処理による劣化が防
止できる。前記緩衝膜は従来のキャパシタにおいて誘電
体膜、第2電極及びBPSG膜等の熱的ストレスにより
電気的特性の劣化を補償し結局これを防止する機能をす
ることと判断される。Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. By forming a film made of a heat resistant metal or a metal nitride thereof on a dielectric film made of a high dielectric material or a ferroelectric material, the interface characteristics with the dielectric film are improved, and the heat resistant metal or metal nitride is formed. By forming the buffer film on the top of the substrate, deterioration due to the subsequent heat treatment can be prevented. It is considered that the buffer film has a function of compensating for deterioration of electrical characteristics due to thermal stress of the dielectric film, the second electrode, the BPSG film and the like in the conventional capacitor and eventually preventing the deterioration.
【0018】本発明によるキャパシタの製造方法の実施
例を概略的に説明すれば次の通りである。先ず、第1電
極を形成する。前記第1電極の上部に誘電体膜を形成す
る。例えば、化学気相蒸着法CVDとして60〜 200Åの
厚さで Ta2O5を蒸着しこの Ta2O5の膜質を改善するため
に300℃でUV−O3 処理及び800℃で dry−O 2
処理をそれぞれ遂行する。この際前記紫外線下のオゾン
処理は濃度 100〜 200g/Nm3 で数分〜1時間の間遂行し
前記酸素雰囲気下での熱処理は数分〜1時間の間遂行す
る。Implementation of the method of manufacturing a capacitor according to the present invention
The following is a brief description of an example. First, the 1st Den
Form a pole. Forming a dielectric film on the first electrode
It For example, as a chemical vapor deposition CVD method, 60 to 200 Å
Thickness in Ta2OFiveEvaporate this Ta2OFiveTo improve the film quality of
UV-O at 300 ℃3Treatment and dry-O at 800 ℃ 2
Carry out each processing. At this time, the ozone under the ultraviolet light
Treatment is concentration 100-200g / Nm3For a few minutes to an hour
The heat treatment in the oxygen atmosphere is performed for several minutes to 1 hour.
It
【0019】形成された誘電体膜の上部に耐熱性金属又
はこれの窒化物、例えば窒化チタニウムTiN を 100〜1,
000 Åの厚さで蒸着した後、ドープされたポリシリコン
を1,000 〜2,000 Åの厚さで蒸着し緩衝膜のキャッピン
グされた第2電極を形成する。次いで、上部電極のパタ
ーン形成及び一般的な工程を遂行し本発明のキャパシタ
を完成する。A heat-resistant metal or a nitride thereof, for example, titanium nitride TiN is added to the upper portion of the formed dielectric film in an amount of 100 to 1,
After depositing a thickness of 000Å, doped polysilicon is deposited to a thickness of 1,000 to 2,000Å to form a second electrode capped with a buffer film. Then, patterning of the upper electrode and general processes are performed to complete the capacitor of the present invention.
【0020】以下、本発明によるキャパシタの製造方法
を具体的な実施例を通じて詳細に説明されることにする
が、本発明が下記した実施例にのみ限定されないことが
理解されるべきである。 (実施例1)先ず、第1電極として、面抵抗Rsが30
Ω/□である多結晶シリコンでストレージノードを形成
した。前記ストレージノードの上部に化学気相蒸着法C
VDで100Åの厚さで Ta2O5を蒸着した。蒸着された
Ta2O5の膜質を改善するために300℃でUV−O3 処
理及び800℃で dry−O2 処理をそれぞれ遂行した。
この際前記紫外線下のオゾン処理は濃度 100〜 200g/Nm
3 で30分の間遂行し前記酸素雰囲気下での熱処理は3
0分の間遂行した。形成された Ta2O5誘電体膜の上部に
窒化チタニウム TiNを600Åの厚さで蒸着した後、不
純物のドープされたポリシリコンを1600Åの厚さで
蒸着し緩衝膜のキャッピングされた第2電極を形成す
る。次いで上部電極のパターン形成及び一般的な工程を
遂行し本発明のキャパシタを完成した。Hereinafter, the method of manufacturing a capacitor according to the present invention will be described in detail through specific embodiments, but it should be understood that the present invention is not limited to the embodiments described below. (Example 1) First, as the first electrode, the sheet resistance Rs was 30.
A storage node was formed from polycrystalline silicon having Ω / □. A chemical vapor deposition method C is formed on the storage node.
Ta 2 O 5 was vapor-deposited by VD to a thickness of 100 Å. Vapor deposited
In order to improve the film quality of Ta 2 O 5 , UV-O 3 treatment was performed at 300 ° C. and dry-O 2 treatment was performed at 800 ° C., respectively.
At this time, the ozone treatment under the above-mentioned ultraviolet rays has a concentration of 100 to 200 g / Nm.
And the heat treatment under the oxygen atmosphere is 3 for 30 minutes.
I ran for 0 minutes. After depositing titanium nitride TiN to a thickness of 600 Å on the formed Ta 2 O 5 dielectric film, polysilicon doped with impurities is deposited to a thickness of 1600 Å, and the second electrode is capped with a buffer film. To form. Then, patterning of the upper electrode and general steps were performed to complete the capacitor of the present invention.
【0021】本実施例により完成されたキャパシタの概
略的な断面図を図3に示した。下部電極である第1電極
11の上部に高誘電物質よりなる誘電体膜13があり、
これの上部には耐熱性金属の窒化物である TiN膜14及
び不純物のドープされた多結晶シリコン膜の緩衝膜15
が具備されている構造である。 (比較例1)実施例1の場合と同一の方法で遂行する
が、緩衝膜形成工程は略し TiN膜の上部に緩衝膜が形成
されていない従来のキャパシタ、即ち TiN/Ta2O5/s-pol
y システムのキャパシタを製造した。FIG. 3 shows a schematic cross-sectional view of a capacitor completed according to this embodiment. There is a dielectric film 13 made of a high dielectric material above the first electrode 11 which is a lower electrode,
On top of this, a TiN film 14 made of a refractory metal nitride and a buffer film 15 made of an impurity-doped polycrystalline silicon film.
Is a structure equipped with. (Comparative Example 1) The same method as in Example 1 is performed, but the buffer film forming step is omitted, that is, a conventional capacitor having no buffer film formed on the TiN film, that is, TiN / Ta 2 O 5 / s. -pol
y System capacitors manufactured.
【0022】(実施例2)多結晶シリコン及びその上部
に形成された TiN金属膜よりなる第1電極であるストレ
ージノードを形成した。以下、実施例1の場合と同一の
方法により遂行し本発明のキャパシタを完成した。第1
電極層の上部に耐熱性金属の窒化膜を形成させることに
より後続く熱処理工程によるキャパシタの劣化を更に良
好に防止できたが、これは誘電体膜の上下部に形成され
た耐熱性金属膜が誘電体膜の熱によるストレス増加を更
に効率的に防止するためであると判断される。Example 2 A storage node, which is a first electrode, made of polycrystalline silicon and a TiN metal film formed on the polycrystalline silicon was formed. Then, the same method as in Example 1 was performed to complete the capacitor of the present invention. First
By forming the heat-resistant metal nitride film on the upper part of the electrode layer, the deterioration of the capacitor due to the subsequent heat treatment process could be better prevented. This is because the heat-resistant metal film formed on the upper and lower parts of the dielectric film is It is considered that this is to more efficiently prevent an increase in stress due to heat of the dielectric film.
【0023】本実施例により完成されたキャパシタの概
略的な断面図を図4に示した。これは多結晶シリコンよ
りなる第1電極11、その上部に蒸着形成された TiN膜
12、高誘電物質の誘電体膜13及び第2電極14、1
5から構成された。本発明のキャパシタと従来のキャパ
シタの電気的な特性を見るために図5に実施例1により
形成されたキャパシタと比較例1により製造されたキャ
パシタのI−V曲線を示した。A schematic cross-sectional view of the capacitor completed according to this embodiment is shown in FIG. This is a first electrode 11 made of polycrystalline silicon, a TiN film 12 formed by vapor deposition on top of it, a dielectric film 13 of a high dielectric material and a second electrode 14, 1.
Composed of 5. In order to check the electrical characteristics of the capacitor of the present invention and the conventional capacitor, FIG. 5 shows IV curves of the capacitor formed according to Example 1 and the capacitor manufactured according to Comparative Example 1.
【0024】図5は約3μm3の面積を有するセルが 1,0
00個集まって形成された1Kセルブロックで測定した漏
洩電流−電圧関係を示すグラフであり、BPSGリフロ
−を経た後に測定された結果である。曲線hは実施例1
の方法により製造された本発明のキャパシタ即ち、d-po
ly/TiN/Ta2O5/s-poly システムに対し、iは比較例1に
より製造された従来のキャパシタ即ち、TiN/Ta2O5/s-po
lyシステムに対する。FIG. 5 shows that a cell having an area of about 3 μm 3 is 1,0
It is a graph showing a leakage current-voltage relationship measured with 1K cell blocks formed by collecting 00 pieces, and is a result measured after passing through a BPSG reflow. The curve h is the first embodiment
The capacitor of the present invention manufactured by the method of d.
For the ly / TiN / Ta 2 O 5 / s-poly system, i is the conventional capacitor manufactured according to Comparative Example 1, namely TiN / Ta 2 O 5 / s-po.
for ly system.
【0025】図面によれば従来のキャパシタは 1.7Vで
1EO−2A位の漏洩電流値を示す反面、本発明により
TiN電極の上を不純物のドープされた多結晶シリコンで
キャッピングしたキャパシタの場合には 5.85E-12A位の
漏洩値を示す。図5から本発明のキャパシタは Ta2O5を
誘電体膜に使用しても、後続する熱処理工程により劣化
することが防止できる。According to the drawings, the conventional capacitor shows a leakage current value of about 1 EO-2A at 1.7V, but according to the present invention.
In the case of a capacitor capped with impurity-doped polycrystalline silicon on the TiN electrode, a leakage value of about 5.85E-12A is shown. As shown in FIG. 5, even if Ta 2 O 5 is used for the dielectric film, the capacitor of the present invention can be prevented from being deteriorated by the subsequent heat treatment process.
【0026】[0026]
【発明の効果】以上説明したように、本発明により製造
されたキャパシタによると、高誘電物質又は強誘電物質
を誘電体膜成分に使用するので電気的特性の改善された
ものでありながらも後続く工程の熱処理により劣化され
ず優れた特性を有する。又、従来の Ta2O5誘電体膜の上
部にTiN 等の金属で形成させていた第2電極の場合、金
属基準で後続く洗浄工程及び蝕刻工程を遂行すべきなの
で工程の適合性が落ちたが、本発明のように第2電極の
上部に非金属緩衝膜を具備したキャパシタにおいてはこ
の膜に対し後続く熱処理による劣化防止効果だけでなく
非金属基準で後工程が進行されるので工程の適合性も向
上される。As described above, according to the capacitor manufactured by the present invention, since the high dielectric material or the ferroelectric material is used as the dielectric film component, the electric characteristics are improved, but It has excellent characteristics without being deteriorated by the heat treatment in the subsequent process. Also, in the case of the second electrode, which was formed of metal such as TiN on the top of the conventional Ta 2 O 5 dielectric film, the subsequent cleaning process and etching process should be performed on the basis of metal, so the compatibility of the process deteriorates. However, in the capacitor having the non-metal buffer film on the second electrode as in the present invention, not only the effect of preventing deterioration due to the subsequent heat treatment but also the post-process is performed on the non-metal basis because the post-process proceeds. The suitability of is also improved.
【図1】図1は従来のキャパシタを概略的に示す図面で
ある。FIG. 1 is a schematic view of a conventional capacitor.
【図2】図2は従来の方法により Ta2O5を使用し誘電膜
を製造したキャパシタに対しBPSGリフロ−を行う前
後の電気的特性を比較して示したグラフである。FIG. 2 is a graph showing a comparison of electrical characteristics before and after performing BPSG reflow on a capacitor having a dielectric film manufactured using Ta 2 O 5 according to a conventional method.
【図3】図3は本発明の一実施例によるキャパシタの概
略的な断面図である。FIG. 3 is a schematic cross-sectional view of a capacitor according to an exemplary embodiment of the present invention.
【図4】図4は本発明の他の実施例によるキャパシタの
概略的な断面図である。FIG. 4 is a schematic cross-sectional view of a capacitor according to another embodiment of the present invention.
【図5】図5は本発明の一実施例によるキャパシタの特
性を示すためのI−V曲線であり従来のキャパシタと比
較して示したものである。FIG. 5 is an IV curve showing characteristics of a capacitor according to an embodiment of the present invention, which is shown in comparison with a conventional capacitor.
11 第1電極 12 TiN 膜 13 誘電体膜 14 第2電極 15 第2電極 11 1st electrode 12 TiN film 13 Dielectric film 14 2nd electrode 15 2nd electrode
フロントページの続き (72)発明者 宣 榕斌 大韓民国 京畿道 水原市 長安区 牛滿 洞 129−1番地 現代アパート 19棟 501号Front page continuation (72) Inventor Xuan Yue, Republic of Korea, Gyeonggi-do, Suwon-si, Chang'an-gu, Usubin-dong, 129-1, Hyundai Apartment 19 501
Claims (9)
れた誘電体膜及び前記誘電体膜の上部に形成された第2
電極を具備する半導体装置のキャパシタにおいて、 前記誘電体膜が高誘電物質及び強誘電物質の中から選択
されたいずれか一つで製造されたものであり、前記第2
電極は耐熱性金属膜又は耐熱性金属の窒化膜の中から選
択されたいずれか一つ及びその上部に形成された緩衝膜
よりなることを特徴とする半導体装置のキャパシタ。1. A first electrode, a dielectric film formed on the first electrode, and a second film formed on the dielectric film.
In a capacitor of a semiconductor device having an electrode, the dielectric film is made of one of a high dielectric material and a ferroelectric material.
A capacitor of a semiconductor device, wherein the electrode comprises one of a heat-resistant metal film or a nitride film of a heat-resistant metal and a buffer film formed thereon.
結晶シリコンよりなることを特徴とする請求項1記載の
半導体装置のキャパシタ。2. The capacitor of the semiconductor device according to claim 1, wherein the first electrode is made of impurity-doped polycrystalline silicon.
、TiW 、Pt及びPdよりなる群から選択された少なくと
も一つの耐熱性金属又は耐熱性金属合金よりなる層が形
成されたことを特徴とする請求項2記載の半導体装置の
キャパシタ。3. TiN, Ti, W on top of the polycrystalline silicon
The capacitor of the semiconductor device according to claim 2, wherein a layer made of at least one heat-resistant metal or heat-resistant metal alloy selected from the group consisting of TiW, Pt, and Pd is formed.
及びAuよりなる群から選択された少なくとも一つである
ことを特徴とする請求項1記載の半導体装置のキャパシ
タ。4. The refractory metal is Ti, W 3, TiW 3, Pt or Pd.
2. The capacitor of the semiconductor device according to claim 1, wherein the capacitor is at least one selected from the group consisting of Au and Au.
WN及び PtNよりなる群から選択された少なくとも一つで
あることを特徴とする請求項1記載の半導体装置のキャ
パシタ。5. The refractory metal nitride is TiN, Wn, or Ti.
The capacitor of the semiconductor device according to claim 1, wherein the capacitor is at least one selected from the group consisting of WN and PtN.
イドであることを特徴とする請求項1記載の半導体装置
のキャパシタ。6. The capacitor of the semiconductor device according to claim 1, wherein the buffer film is polycrystalline silicon or silicide.
中少なくとも一つであることを特徴とする請求項6記載
の半導体装置のキャパシタ。7. The capacitor of the semiconductor device according to claim 6, wherein the buffer film is at least one of WSi, TiSi, MoSi and TaSi.
O2及びHfO2よりなる群から選択されたいずれか一つであ
ることを特徴とする請求項1記載の半導体装置のキャパ
シタ。8. The high dielectric material of the dielectric film is Ta 2 O 5 , Ti
The capacitor of the semiconductor device according to claim 1, wherein the capacitor is any one selected from the group consisting of O 2 and HfO 2 .
物、PLZT化合物、BST化合物よりなる群から選択
された少なくともいずれか一つであることを特徴とする
請求項1記載の半導体装置のキャパシタ。9. The capacitor of the semiconductor device according to claim 1, wherein the ferroelectric substance of the dielectric film is at least one selected from the group consisting of PZT compounds, PLZT compounds, and BST compounds. .
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920023806A KR960000953B1 (en) | 1992-12-10 | 1992-12-10 | Semiconductor memory device and the manufacturing method |
KR1992P23806 | 1992-12-10 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH06232344A true JPH06232344A (en) | 1994-08-19 |
Family
ID=19345137
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5309547A Pending JPH06232344A (en) | 1992-12-10 | 1993-12-09 | Capacitor of semiconductor device |
Country Status (2)
Country | Link |
---|---|
JP (1) | JPH06232344A (en) |
KR (1) | KR960000953B1 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5956595A (en) * | 1996-07-15 | 1999-09-21 | Nec Corporation | Method of fabricating a semiconductor integrated circuit having a capacitor with lower electrode comprising titanium nitride |
US6103566A (en) * | 1995-12-08 | 2000-08-15 | Hitachi, Ltd. | Method for manufacturing semiconductor integrated circuit device having a titanium electrode |
KR20000074727A (en) * | 1999-05-25 | 2000-12-15 | 윤종용 | Method for forming a ferroelectric capacitor using O3 annealing |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100355379B1 (en) * | 1995-06-07 | 2002-12-16 | 삼성전자 주식회사 | Ferroelectric memory device and driving method thereof |
KR19980060601A (en) * | 1996-12-31 | 1998-10-07 | 김영환 | Capacitor Manufacturing Method of Semiconductor Device |
WO2021125006A1 (en) * | 2019-12-20 | 2021-06-24 | 京セラ株式会社 | Film capacitor element and film capacitor |
-
1992
- 1992-12-10 KR KR1019920023806A patent/KR960000953B1/en not_active Expired - Fee Related
-
1993
- 1993-12-09 JP JP5309547A patent/JPH06232344A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6103566A (en) * | 1995-12-08 | 2000-08-15 | Hitachi, Ltd. | Method for manufacturing semiconductor integrated circuit device having a titanium electrode |
US5956595A (en) * | 1996-07-15 | 1999-09-21 | Nec Corporation | Method of fabricating a semiconductor integrated circuit having a capacitor with lower electrode comprising titanium nitride |
KR20000074727A (en) * | 1999-05-25 | 2000-12-15 | 윤종용 | Method for forming a ferroelectric capacitor using O3 annealing |
Also Published As
Publication number | Publication date |
---|---|
KR960000953B1 (en) | 1996-01-15 |
KR940016755A (en) | 1994-07-25 |
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