JPH06232251A - Separated region and its formation - Google Patents

Abstract

(57) [Abstract] [Objective] In a semiconductor integrated circuit composed of a large number of elements, an isolation region for effectively isolating each element without adversely affecting the characteristics and reliability of the element, and a method for forming the isolation region. I will provide a. A mask is formed on a portion of a semiconductor surface where an element is to be formed, a region made of an isolation material is formed on the semiconductor surface where the mask is not formed, and the semiconductor surface is doped through the isolation material region. At this time, the mask prevents impurities due to doping from diffusing into the semiconductor surface under the mask.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates generally to semiconductor devices, and more particularly to isolation regions and methods of forming the same.

[0002]

2. Description of the Related Art An integrated circuit is formed on a semiconductor substrate,
Further, it has a large number of elements internally connected so as to have a predetermined function. An element or a group of elements needs to be separated from each other so that the operation of the element does not affect the operation of other elements. The most common element isolation method is a field isolation method including a step of forming an insulator region on the semiconductor surface. The most common method for performing field isolation is to form a silicon nitride mask on a portion of the substrate and heat in an oxygen atmosphere to form a silicon dioxide region on the exposed portion, which is a selective oxidation method (L
OCOS, partial oxidation of silicon). It is common practice to form a lightly doped region below the oxide region to further strengthen the isolation between the devices.

However, as semiconductor devices become more complex, the need for smaller isolation regions increases. Therefore, field oxide (bird's beak)
Several methods have been proposed to prevent regions and lightly doped regions from physically penetrating into the "recess" where the device is to be formed. However, these attempts have the drawback of adversely affecting either the performance or reliability of the device.

Therefore, in this industrial field, there is a need to obtain an isolation region and a method for forming the isolation region that do not adversely affect the characteristics or reliability of the device.

[0005]

SUMMARY OF THE INVENTION The present invention provides a separation area and a method for forming the separation area that substantially eliminates the problems of the conventional separation area.

[0006]

A mask is formed on the semiconductor surface to define the contour of the area where the active device is to be formed. An isolation material region is formed on the unmasked portion of the semiconductor surface. The semiconductor surface is doped through the isolation region while the mask prevents the semiconductor surface extending below the mask from being doped.

[0007]

The present invention provides superior effects over the prior art. A doped region is formed below the isolation material region by a self-aligned method. This self-alignment method serves to prevent the intrusion into the recessed areas caused by the misalignment in the mask process. In addition, this self-aligned method provides a doped region that extends very close to the ends of the depression for maximum isolation.

In a second embodiment of the invention, a sidewall region is formed adjacent to the mask and the semiconductor surface is doped once more through the isolation material region. This feature of the invention creates a second high density field implant region off the edge of the depression so that the narrow channel effect is minimized. This second doped region is likewise formed by a self-aligned method, so that the symmetry of the device is maintained. Since this high-concentration region is far from the end of the depression, the influence of this region on the junction breakdown and the junction capacitance is reduced.

[0009]

The preferred embodiment of the present invention and its effect are as follows.
It is best understood by referring to FIGS. In each figure, the same reference numerals are used for similar and corresponding parts.

1a and 1b are side sectional views of a prior art field separation method. In FIG. 1 a, the doped region 10 is formed in a portion of the semiconductor substrate 12 whose contour is specified by the nitride region 14. Nitride region 14 is formed on pad oxide region 16.

In FIG. 1b, field oxide region 1
8 is formed by heating the semiconductor substrate in an oxygen atmosphere in the selective oxidation method. The selective oxidation method forms a silicon dioxide region (“oxide region”) 18 in the exposed silicon portion. Then, the nitride region 14 and the pad oxide region 16 are removed.

The disadvantages of this method are as follows. That is, the doped portion 10 diffuses and expands around the field oxide region 18 as the substrate 12 is heated, thus degrading the properties of the device formed in the recessed region adjacent the silicon dioxide region 18. This effect is called the narrow channel effect. Therefore, this method
It is used only when forming a device having a size larger than μm.

FIG. 2 is a side sectional view showing a separation region according to the second conventional technique. This method is the same as the method shown in Figures 1a and 1b, except that a blanket-like low-density implant 20 is performed after the removal of the nitride regions 14. The blanket implant layer is designed to have a peak concentration at or slightly below the silicon and silicon dioxide boundary below the field oxide layer, and further the device is formed on top of the recessed region 22. As such, it must be formed deep enough within the recessed area. If the recessed region 22 is not deep enough, the device characteristics deteriorate due to the large substrate effect. However, since it is necessary to reduce the field penetration into the recessed area caused by the bird's beak associated with the miniaturization of the device, the field oxide layer has a small thickness (for the technology of 1.0 to 1.2 μm). 70
From 00Å to 300 for technology of 0.4-0.6 μm
0-4000Å). By thinning the field oxide layer, the implanted impurities will be located on the upper surface of the depression layer, increasing the substrate effect of the device formed therein.

FIG. 3 is a side cross-sectional view showing the proposed method for limiting the penetration of the doped region 10 into the recessed region 22. In this method, the field oxide region 1
8 is formed in the semiconductor substrate 12 prior to the formation of all doping regions below this region 18. After removing the silicon nitride 14 and the pad oxide layer 16,
A mask 24 is formed on the exposed portion of the substrate 12 using photolithography.
To form. Impurities are implanted through the field oxide regions 18 to form the doped regions 26 below the field oxide regions 18. The photoresist mask prevents impurities from entering the recessed area. After that, the photoresist mask 24 is removed.

This method has serious drawbacks. First of all, due to the misalignment of the photoresist mask 24,
Impurity implants may occur in the recessed regions 22 rather than through the field oxide regions 18. Therefore, the doped region 26 expands into the recessed region 22 and seriously affects the operation of the device formed therein. Second, the formation of the photoresist mask 24 is limited by the resolution of the photolithography technique, which affects the size of the doped regions 26 and the recessed regions 22.

4a-4d are side cross-sectional views showing the method of the present invention and the isolation regions formed thereby.
In FIG. 4a, a pad oxide layer 28 and a silicon nitride layer 30 are formed on a semiconductor substrate 31, shown here as a P-type silicon substrate. The silicon nitride layer 30 is approximately 270
It has a thickness of 0Å, and the pad oxide layer 28 has a thickness of about 120.
Has a thickness of Å. For a final recess width of 0.3 μm and a field width of 0.5 μm, the silicon nitride regions have a width of 0.4 μm and the spacing between the silicon nitride regions is 0.4 μm wide. The width of the depression and the field may be narrower than this.

In FIG. 4b, the field oxide region 3
2 is formed to a thickness of about 2000Å. In the preferred embodiment, the field oxide regions are formed using selective oxidation techniques. However, it goes without saying that other methods can be used as well. As such a method, there is a multi-buffer selective oxidation technique. A low concentration channel implant is performed through this region 32 to form a doped region 34 under the field oxide region 32. This concentration is
It is on the order of 1 × 10 ¹² ions / cm ² . For the P-type substrate 31, the boron material is a suitable impurity. The purpose of this implant is to dope the region under the field oxide near the edge of the recess to prevent spurious leakage currents if a MOSFET is formed in the recess region in a later step.

It should be noted that this method is self-aligning because the silicon nitride region 30 is used to isolate impurities from the recess 36.
That is, the same mask is used to define the contours of field oxide regions 32 and dopings 34.
However, during the implantation, the implantation energy of boron and the thickness of the oxide and masking nitride layers must be selected appropriately to prevent impurities from reaching the recessed regions. In this preferred embodiment, the field oxide thickness is much less than the mask nitride thickness. Oxide and nitride thicknesses of 2000 and 2700Å, respectively
In the example under consideration, 60 KeV boron energy is optimal. In addition, by normally adjusting the channel V _t adjustment or punch-through implantation, which is usually performed in a later step for manufacturing a MOSFET,
It is also possible to design to compensate for the small amount of implanted boron reaching the recessed area.

In FIG. 4c, sidewall region 38 is formed adjacent to silicon nitride region 30. This sidewall region 38
Deposits a well-matched polycrystalline silicon layer on the structure, and about 0.10 to 0.15 μ around the silicon nitride region 30.
It is formed by performing anisotropic etching to form a spacer having a width of m. A high concentration implantation of boron is performed on the structure. In the silicon nitride region 30 and the sidewall region 38, the implanted material is a thermally oxidized region 32.
Limit penetration to exposed parts of. In this way, the heavily doped region 40 is formed below the exposed portion of the field oxide region 32 in the substrate 31. This concentration is approximately 5 × 10 ¹² ions / cm.

Since the polycrystalline silicon used to form the sidewall regions 38 is very well matched,
The width of the high concentration region 40 can be controlled very accurately.

In FIG. 4d, the silicon nitride region 30, the sidewall region 38, and the pad oxide layer 28 are removed for device formation after forming the isolation region, and the N ⁺ region 4 is further removed.
2 is formed in one well and gate 44 and gate oxide 46 are formed in the other well.

In each of the above manufacturing steps, a nitride spacer may be used instead of the polycrystalline spacer. Because the spacer formation can reduce the thickness of the field oxide or mask layer, and for other reasons, the implant energy in the first implant step and the second implant step (after the sidewall spacer region 38 formation) is performed. Be different) energy. It is possible to reduce the implantation energy required for the first implantation by reducing the thickness of the grown oxide in the portion close to the end of the nitride mask layer (shown by the dotted line 33). The main purpose of this implantation is to implant impurities in the field region near the edge of the recessed field.

Further, the boron used in the second implantation step performed after the spacer formation diffuses outward in the subsequent heating step. This outward diffusion can also eliminate the need for the first implantation step. If the first implanting step is omitted, the spacer width before the second implanting step and the heating cycle is
It is an important parameter that affects the diffusion of boron to the edge of the field depression. In some cases, the first implant concentration is higher than the concentration during the second implant step performed after spacer formation. In yet another case, the first
The field separation can be sufficiently performed only by the step of implanting, and thereby the need for the spacer formation and the second implanting step is eliminated. It should be noted that although the present invention has been described in the context of a P-type substrate, this technique can be applied to N-type substrates as well. In the case of an N-type substrate, phosphorus and / or arsenic are suitable as impurities to be implanted into the field region.

FIGS. 5a and 5b show the layout of a DRAM cell and its cross section using the field isolation technique described above to obtain a high density (64 megabyte) memory array. As described above, after formation of the recessed regions, a dummy gate oxide is grown in the recessed regions 48 and a channel implant is made in the recessed regions 48 to adjust the doping level near the top of the recesses 48. Then strip off the dummy oxide and grow about 100Å of gate oxide. On this gate oxide layer 50,
A gate polycrystalline silicon layer 52 and an oxide layer 54 having a thickness of 2000 Å are formed. The bilayer of oxide 54 and polycrystalline silicon 52 is etched with a gate pattern to repair the damage caused to the gate edge dielectric by this etching.
Then, a source / drain region 5 is formed by a drain manufacturing method (LLD) by low-concentration doping for performing an oxidation process.
5 is formed. In this step, low concentration impurity implantation is performed on the source and drain regions, then about 1000 Å oxide spacers 56 are formed, and high concentration impurity implantation is further performed on the source and drain regions.

Usually, in a DRAM array, implantation of high concentration impurities by the LDD method is omitted. The oxide in the self-aligned contact area 49 is then etched to expose the underlying recessed area. About 5000 Å doped polycrystalline silicon (pad polycrystalline silicon) layer 58 is deposited, and this is etched to a thickness of 3000 Å. The contour of the pad pattern is specified and the pad polysilicon is etched. The pad polycrystalline silicon has recessed regions 48 exposed by self-aligned contact etching.
And for making electrical contact in the region 49. After depositing BPSG oxide 61, it is cleaned and further etched to planarize the surface, and contact 61 for bit line is formed.
Is etched, and then about 2000 Å doped polycrystalline silicon 59 for bit lines is deposited. The bit line polycrystalline silicon 59 contacts the pad polycrystalline silicon 58 in the contact region 61. The polycrystalline silicon for bit lines is contoured and etched using a combination of anisotropic and isotropic etching, the line width of which is about .5 on the wafer for printed lines of about 0.35 .mu.m. It is reduced to 2 μm to improve the margin of separation from the storage node contact, which will be defined later.

Next, the bit line polycrystalline silicon is silicidized to form titanium silicide (titanium silicide). Depositing another BPSG oxide layer, B
The PSG oxide layer 60 delineates the storage node contacts 62, thereby forming a new layer. The oxide is etched to expose the pad polysilicon layer at the contact points. About 8000 Å storage polycrystalline silicon layer 63 of doped polycrystalline silicon is deposited, patterned and further etched. In order to increase the area of the polycrystalline silicon node for memory, it is also possible to deposit uneven or hemispherical polycrystalline silicon and perform blanket etching to separate the island 63 of polycrystalline silicon for memory node. is there. A dielectric layer 64 formed by depositing about 60 Å of silicon nitride and then performing steam oxidation to improve dielectric properties is formed on the polycrystalline silicon island 63. A plate-like polycrystalline silicon layer 66 for storage made of approximately 2000 liters of polycrystalline silicon
Are formed on the dielectric layer 64. The memory plate-shaped polycrystalline silicon layer 66 is etched to complete the formation of the cell capacitor. After further deposition of oxide, a multi-layer metal process is performed to complete the circuit formation.

[0027]

As described above, according to the present invention, the isolation region can be formed without deteriorating the characteristics or reliability of the device. While the invention has been described in detail above, it should be noted that many modifications, substitutions and alterations are possible without departing from the spirit and scope of the invention defined in the claims. .

With respect to the above description, the following items will be further disclosed. (1) A method of forming isolation regions between active elements, a step of forming a mask for defining the contour of a region on the semiconductor surface where elements are to be formed, and an unmasked portion of the semiconductor surface, which comprises the following steps. Forming an isolation material region, and doping the semiconductor surface through the isolation region while preventing the semiconductor surface under the mask from being doped by the mask.

(2) The doping step comprises the step of doping the semiconductor surface to a first doping level, further forming a sidewall region adjacent to the mask and extending over the isolation material region, and between the sidewall regions. Doping the semiconductor surface to a second doping level through the region of isolation material.

(3) The method according to claim 2, wherein the side wall forming step comprises a step of forming a side wall of polycrystalline silicon.

(4) The method according to claim 2, wherein the side wall forming step includes a step of forming a nitride side wall.

(5) The step of doping the semiconductor surface to the second level comprises the step of doping the semiconductor surface to a level higher than the first level.
Method described in section.

(6) The method of claim 1 further including the step of removing the mask to expose the semiconductor surface under the mask.

(7) The method of claim 2 further including the step of removing the mask and sidewalls to expose the semiconductor surface beneath the mask and sidewall regions.

(8) The method according to claim 6, further comprising the step of forming an element on the exposed semiconductor surface.

(9) The method according to claim 1, wherein the step of forming the isolation material region comprises the step of forming a thermal oxidation region in an unmasked portion of the semiconductor surface.

(10) The method according to claim 1, wherein the step of forming the mask comprises the step of forming a nitride mask that specifies the contour of the first region on the semiconductor surface where the active element is to be formed.

(11) The doping step comprises the step of doping the semiconductor surface by implanting boron through the isolation region while blocking the doping of the semiconductor surface thereunder by the mask. the method of.

(12) The method according to claim 2, wherein the step of doping to the second level comprises the step of doping the semiconductor surface by implanting boron through the isolation region between the sidewall regions.

(13) A method of forming an isolation region between active elements, a step of forming a mask for specifying the contour of a portion of the semiconductor surface where elements are formed, and a step of masking the semiconductor surface. Forming a region of isolation material in the non-existing portion, forming a sidewall region adjacent to the mask and extending above the isolation material region, and blocking doping of the semiconductor surface under the mask by the mask and the sidewall region. While doping the semiconductor surface through the isolation region between the sidewall regions.

(14) The method according to claim 13, wherein the step of forming the side wall comprises a step of forming a side wall of polycrystalline silicon.

(15) The method according to claim 13, wherein the step of forming the side wall comprises a step of forming a side wall of nitride.

(16) The method of claim 13 further including the step of removing the mask and sidewall regions to expose the semiconductor surface beneath the mask and sidewall regions.

(17) The method according to item 16, further comprising the step of forming an element on the exposed semiconductor surface.

(18) The method according to claim 13, wherein the step of forming the isolation material region comprises the step of forming a thermal oxidation region in an unmasked portion of the semiconductor surface.

(19) The method according to claim 13, wherein the step of forming the mask comprises the step of forming a nitride mask for specifying the contour of a region on the semiconductor surface where an active element is to be formed.

(20) The doping step is a step of implanting boron through the isolation region between the sidewall regions.
The method according to paragraph 13.

(21) The isolation region, the insulating material region extending over the semiconductor surface, the low-concentration doping region formed in the semiconductor surface below the insulating material region, and the low concentration region, each of which comprises the following components. A heavily doped region that extends into the heavily doped region.

(22) The isolation region according to item 21, wherein the lightly doped region has the same conductivity type as the semiconductor surface.

(23) The isolation region according to item 21, wherein the lightly doped region is self-aligned with the insulating material region.

(24) The high-concentration doping region is self-aligned with the low-concentration doping region so as to be separated from an end of the insulating material region by a predetermined distance.
Separation area described in paragraph.

(25) The insulating material area is approximately 2000 Å
The isolation region of claim 21, having a thickness of.

(26) The isolation region according to item 21, wherein the insulating material region is a silicon dioxide region.

(27) The isolation region according to item 26, wherein the silicon dioxide region is a thermally grown oxide region.

(28) A memory cell comprising the following components, extending over a semiconductor surface, and defining an outline of a portion of the semiconductor surface where an element can be formed, and an insulating material region under the insulating material region. A lightly doped region formed in the semiconductor region, a heavily doped region extending into the lightly doped region, and a memory cell formed in the specified portion of the semiconductor surface.

(29) The memory cell according to item 28, wherein the lightly doped region has the same conductivity type as that of the semiconductor surface.

(30) The memory cell according to item 28, wherein the lightly doped region is self-aligned with the insulating material region.

(31) The high-concentration doping region is self-aligned with the low-concentration doping region so as to be separated from an end of the insulating material region by a predetermined distance.
The memory cell according to the item.

(32) A method of forming a memory cell, a step of forming a mask for specifying the contour of a region on the semiconductor surface where a memory cell is to be formed, and a step of separating the unmasked portion of the semiconductor surface. Forming a material region, doping the semiconductor surface through the isolation region while blocking the doping of the semiconductor surface under the mask by the mask, and forming a memory cell in the specified region .

(33) The doping step comprises the step of doping the semiconductor surface at a first doping level, and further forming a sidewall region adjacent to the mask and extending over the isolation material region, and between the sidewall regions. 33. Doping the semiconductor surface to the second doping level through the region of isolation material according to claim 32.

(34) The method according to Item 33, wherein the side wall forming step comprises a step of forming a side wall of polycrystalline silicon.

(35) The method according to Item 33, wherein the side wall forming step comprises a step of forming a nitride side wall.

(36) The step of doping the semiconductor surface to the second level comprises the step of doping the semiconductor surface to a level higher than the first level.
The method according to item 3.

(37) A method of forming a memory cell comprising the following steps, a step of forming a mask for specifying the contour of a region on the semiconductor surface where a memory cell is to be formed, and a non-masked portion of the semiconductor surface. Forming an isolation material region, forming a sidewall region adjacent to the mask and extending above the isolation material region, and blocking the semiconductor surface extending below the mask by the mask and sidewall region, Doping the semiconductor surface through the isolation region between the sidewall regions and forming a memory cell in the identified region of the semiconductor surface.

(38) The method according to Item 37, wherein the side wall forming step comprises a step of forming a side wall of polycrystalline silicon.

(39) The method according to Item 37, wherein the sidewall forming step comprises a step of forming a nitride sidewall.

(40) The method of claim 37, further comprising the step of removing the mask and sidewall regions to expose the semiconductor surface beneath the mask and sidewall regions.

(41) The isolation region is formed by using a mask for specifying the contour of the region on the semiconductor surface where the element is to be formed. A region of isolation material is formed in the unmasked portion of the semiconductor surface, which mask prevents doping of the semiconductor surface extending below the mask,
Doping is performed via the isolation region.

[Brief description of drawings]

FIG. 1 is a side sectional view showing a field separation method according to a first prior art technique.

FIG. 2 is a side sectional view showing a field separation method according to a second conventional example technique.

FIG. 3 is a side sectional view showing the proposed field separation method.

FIG. 4 is a side sectional view showing the field separation method of the present invention and the resulting separation region.

FIG. 5 is a diagram showing a layout of a DRAM cell using a field separation technique.

[Explanation of symbols]

 28 Pad Oxide Region 30 Silicon Nitride Layer 31 Semiconductor Substrate 32 Field Oxide Region 34 Doping Region 40 High Concentration Region

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[Procedure amendment]

[Submission date] November 24, 1993

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 5

[Correction method] Change

[Correction content]

[Figure 5]

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication H01L 21/318 C 7352-4M

Claims (2)

[Claims] 1. A method of forming an isolation region between active devices, comprising the steps of: forming a mask that defines the contour of a region of a semiconductor surface where an element is to be formed; and unmasking the semiconductor surface. Forming an isolation material region in the portion, and doping the semiconductor surface through the isolation region while preventing the semiconductor surface under the mask from being doped by the mask. 2. An isolation region, an insulating material region extending over a semiconductor surface, a low-concentration doping region formed in the semiconductor surface below the insulating material region, and the low-concentration region, which comprises the following components. A heavily doped region that extends into the doped region.