JPH06225287A - Arithmetic circuit - Google Patents

Abstract

PURPOSE:To reduce a hardware quantity, external adding circuit and the number of the ports of a memory. CONSTITUTION:Among the respective outputs of arithmetic units 190 to 201 respectively determining difference absolute value arranged in the shape of 3X4 matrix, the outputs of the respective even number-th arithmetic units 190, 192, 194, 196. 198 and 200 are respectively connected in pipe line by way of respective first adders 321 to 325 and the output of the respective odd number-th arithmetic units 191. 193, 195, 197, 199 and 201 are respectively connected in pipe line by way of respective second adders 326 to 330. The output of the first adder 325 on a final stage becomes the sum of difference absolute values at an even field and the output of the second adder 330 on the final stage becomes the sum of the difference absolute values at an odd field. The sum of the difference absolute values in a frame is obtained by adding them by an adder 341.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic circuit suitable for use in a motion vector detection process used in image compression encoding of digital image processing, and more particularly to a full search by a so-called block matching method. The present invention relates to an arithmetic circuit for detecting a motion vector.

[0002]

2. Description of the Related Art Conventionally, so-called block matching method and gradient method have been used as methods that have been generally put to practical use in motion vector detection processing used for image compression encoding of digital image processing.

The block matching method will be described below. The block matching method is widely used for motion compensation prediction of image compression coding.

First, an image frame (or field)
Is divided into thin blocks. As the block size at this time, a size of 8 × 8 pixels or 16 × 16 pixels is generally used. Here, the motion vector detection process is basically a process of detecting from which region of the previous frame the target block (referred to as a reference block) of the current frame has moved. That is, specifically, in the motion vector detection process, for example, as shown in FIG. 8, a block that is most similar to the reference block Bp of the current frame Fp is set as a set of candidate blocks Bb within the search range E of the previous frame Fb. More specifically, it is a process of detecting the positional shift between the detected candidate block Bb and the reference block Bp as a motion vector.

The determination of the block most similar to the reference block Bp in the motion vector detection processing is performed as follows. That is, first, as a first determination operation, the difference between each pixel value c of a certain candidate block Bb and the corresponding pixel value r of the reference block Bp is calculated, and the sum of absolute values (or sum of squares) is calculated.

Next, as the second determination operation, the first determination operation is performed for all candidate blocks Bb in the search range E, and the sum of absolute differences (or the sum of squared differences) obtained respectively is calculated. Find the smallest one. The candidate block Bb that gives the smallest sum of absolute differences (or sum of squared differences) is the block most similar to the reference block Bp.

Specifically, when the block size of the reference block Bp is M × N pixels and the number of candidate blocks Bb is K × L, the motion vector detection process is performed by the following mathematical expression (1). 1) and the following formula (2). In addition,
In these equations (1) and (2), not the sum of squared differences but the sum of absolute differences D (i, j) is obtained. Further, r in the formula (1) represents the pixel value of the reference block Bp of the current frame,
In the equation (1), c represents the pixel value of the previous frame. Further, in the equation (2), (x, y) is (i, when the minimum absolute difference sum (minD (i, j)) is given.
j) is meant. (X, y) in the equation (2) becomes the motion vector MV (x, y).

[0008]

[Equation 1]

[0009]

MV (x, y) = minD (i, j) (2)

From the above, when the block size of the reference block Bp is 4 × 4 pixels and the number of candidate blocks Bb is 7 × 7, the sum of absolute difference D (5,3) is the smallest. In the example of FIG. 8, the motion vector MV is (5,
3).

Next, a conventional circuit configuration in a process of detecting a motion vector in units of frames (hereinafter referred to as a motion vector detection process of only a frame) will be described. First, in order to describe the conventional circuit configuration, an example of motion vector detection processing will be given and the example will be described. Furthermore, a conventional circuit configuration and control method will be described along with the example.

Here, as an example, the motion vector detecting process in the case where the block size of the reference block Bp is 3 × 4 pixels and the number of candidate blocks Bb is also 3 × 4 will be described with reference to FIG. In FIG. 9, lowercase numbers a, for each pixel value r of the reference block Bp of the current frame Fp, b, c, are given the · · · (r _a, r _b, r _c, · ...). Also, the previous frame F
For each pixel value c of b, numeral numbers 0, 1, 2, ...
・ Is attached (c ₀ , c ₁ , c ₂ , ...). The procedure of the motion vector detection processing for only the above frame will be described below with reference to FIG.

[0013] First, as the first process step, pixel values r of the reference block Bp0 and (r _a ~r _l), the reference block B
All candidate blocks Bb within the search range E0 for p0
For pixel values c (c _{0 to} c ₃₄ ) of ₀ (there are 12), the following formulas (3) to (3) are calculated based on the above formula (1).
The calculation as shown in (14) is performed, and the sum of absolute differences D (i, j) (0 ≦
i <2,0 ≦ j <3) is obtained.

[0014]

## EQU3 ## D (0,0) = | r _a −c ₀ | + | r _b −c ₁ | + | r _c −c ₂ | + | r _d −c ₃ | + | r _e −c ₇ | ＋ ・ ・ ・ ・ ＋ ｜ r _l −c ₁₇ ｜ ・ ・ ・ ・ (3)

[0015]

Equation 4] _{D (0,1) = | r a} -c 1 | + | r b -c 2 | + | r c -c 3 | + | r d -c 4 | + | r e -c 8 | + ・ ・ ・ ・ + ｜ r _l −c ₁₈ | ・ ・ ・ ・ (4)

[0016]

Equation 5] _{D (0,2) = | r a} -c 2 | + | r b -c 3 | + | r c -c 4 | + | r d -c 5 | + | r e -c 9 | + ・ ・ ・ ・ ＋ ｜ r _l −c ₁₉ | ・ ・ ・ ・ (5)

[0017]

[6] _{D (0,3) = | r a} -c 3 | + | r b -c 4 | + | r c -c 5 | + | r d -c 6 | + | r e -c 10 | ＋ ・ ・ ・ ・ ＋ ｜ r _l −c ₂₀ ｜ ・ ・ ・ ・ (6)

[0018]

Equation 7] _{D (1,0) = | r a} -c 7 | + | r b -c 8 | + | r c -c 9 | + | r d -c 10 | + | r e -c 14 | + ・ ・ ・ ・ + ｜ r _l −c ₂₄ | ・ ・ ・ ・ (7)

[0019]

Equation 8] _{D (1,1) = | r a} -c 8 | + | r b -c 9 | + | r c -c 10 | + | r d -c 11 | + | r e -c 15 | ＋ ・ ・ ・ ・ ＋ ｜ r _l −c ₂₅ ｜ ・ ・ ・ ・ (8)

[0020]

[Equation 9] D (1,2) = | r _a −c ₉ | + | r _b −c ₁₀ | + | r _c −c ₁₁ | + | r _d −c ₁₂ | + | r _e −c ₁₆ | ＋ ・ ・ ・ ・ ＋ ｜ r _l −c ₂₆ ｜ ・ ・ ・ ・ (9)

[0021]

Equation 10] _{D (1,3) = | r a} -c 10 | + | r b -c 11 | + | r c -c 12 | + | r d -c 13 | + | r e -c 17 | ＋ ・ ・ ・ ・ ＋ ｜ r _l −c ₂₇ ｜ ・ ・ ・ ・ (10)

[0022]

Equation 11] _{D (2,0) = | r a} -c 14 | + | r b -c 15 | + | r c -c 16 | + | r d -c 17 | + | r e -c 21 | + ・ ・ ・ ・ + ｜ r _l −c ₃₁ | ・ ・ ・ ・ (11)

[0023]

Equation 12] _{D (2,1) = | r a} -c 15 | + | r b -c 16 | + | r c -c 17 | + | r d -c 18 | + | r e -c 22 | ＋ ・ ・ ・ ・ ＋ ｜ r _l −c ₃₂ ｜ ・ ・ ・ ・ (12)

[0024]

Equation 13] _{D (2,2) = | r a} -c 16 | + | r b -c 17 | + | r c -c 18 | + | r d -c 19 | + | r e -c 23 | ＋ ・ ・ ・ ・ ＋ ｜ r _l −c ₃₃ ｜ ・ ・ ・ ・ (13)

[0025]

D (2,3) = | r _a −c ₁₇ | + | r _b −c ₁₈ | + | r _c −c ₁₉ | + | r _d −c ₂₀ | + | r _e −c ₂₄ | + ・ ・ ・ ・ + ｜ r _l −c ₃₄ | ・ ・ ・ ・ (14)

Next, as a second processing step, the sum of all absolute differences D (i, j) (0≤i obtained in the first processing step)
For <2,0 ≦ j <3), the minimum difference absolute value sum minD (i, j) is obtained based on the above-described equation (2), and the motion vector MV (x, y) is obtained.

As the third processing step, the reference block Bp
Pixel values r _{a ′ to} r of the reference block Bp1 adjacent to 0
_{l ′} and the pixel value c ₂₁ of all candidate blocks Bb1 (there are 12) within the search range E1 of the reference block Bp1.
For c ₅₅ , as in the first processing step described above, formula (1)
Calculation is performed based on the sum of absolute differences D ′ (i, j) (0 ≦
i <2,0 ≦ j <3) is obtained.

Then, as the fourth processing step, the above-mentioned third step is carried out.
Sum of all absolute differences D ′ (i, j) (0
For ≤i <2, 0≤j <3, the minimum sum of absolute difference values minD '(i, j) is obtained based on the equation (2), and the motion vector MV (x, y) is obtained.

Finally, as the fifth processing step, the above operation is similarly repeated for all reference blocks Bp of the current frame Fp to obtain the motion vector MV (x, y).

Conventionally, the above-described motion vector detection processing is realized by the circuit configuration shown in FIGS. 10, 11 and 12.

Here, FIG. 10 shows the overall structure of a conventional motion vector detecting circuit (arithmetic circuit for detecting a motion vector). 10, the arithmetic circuit includes a plurality of arithmetic units (PE) 10 to 21, a plurality of pixel value storage registers (Reg) 22 to 38, and a plurality of multiplexer-attached pixel value storage registers (M & R) 39. To 44 are interconnected.

That is, in FIG. 10, the pixel value r of the reference block Bp is supplied to the terminal 1 and sent to each of the arithmetic units 10 to 21 connected in cascade. Also, terminal 2
Is supplied with the pixel value c of the candidate block Bb in the upper half of the search range E, sent to the input terminals of the first-stage register 22 of the cascaded pixel value storage registers 22 to 25, and these pixel value storage It is sequentially stored in the registers 22 to 25.

The outputs of the pixel value storage registers 22 to 25 are also sent to the corresponding arithmetic units 10 to 13 of the arithmetic units 10 to 21. The output of the arithmetic unit 13 among these arithmetic units 10 to 13 is
The pixel value storage registers 30 to 32 connected in cascade are sent to the input terminal of the register 30 at the first stage, and are sequentially stored in the pixel value interpolation registers 30 to 32. The outputs of the respective pixel value storage registers 30 to 32 are also sent to the corresponding arithmetic units 15 to 17 of the arithmetic units 10 to 21.

Further, the output of the arithmetic unit 17 of the arithmetic units 15 to 17 is sent to the input terminal of the first stage register 33 of the cascaded pixel value storage registers 33 to 35 for interpolating these pixel values. Registers 33-3
Sequentially stored at 5. Each pixel value storage register 33
The outputs of ~ 35 are also sent to the corresponding operation units 19-21 of the operation units 10-21.

Further, for example, the pixel value c of the lower half candidate block Bb of the search range E is supplied to the terminal 3 and is sent to the input terminal of the first-stage register 26 of the cascaded pixel value storage registers 26 to 29. And are sequentially stored in the pixel value storage registers 26 to 29. The output of the register 27 of the pixel value storage registers 26 to 29 is also sent to the pixel value storage register 36, and the output of the register 28 is provided with a multiplexer in which the output of the register 36 is supplied to one input terminal. The output of the register 29 is sent to the other input terminal of the pixel value storage register 39, and is also sent to the other input terminal of the multiplexer-attached pixel value storage register 40 to which the output of the register 39 is supplied to one input terminal.

The output of the pixel value storage register 40 with the multiplexer is sent to the input terminal of the arithmetic unit 10 of the arithmetic units 10 to 21. The output of the arithmetic unit 10 is sent to the next arithmetic unit 11 and also to the input terminal of the pixel value storage register 37. The output of the register 37 is supplied to the other input terminal of the multiplexer-equipped pixel value storage register 41 to which the output of the arithmetic unit 11 is supplied to one input terminal, and the output of the register 41 is supplied to one input terminal. The output of the arithmetic unit 12 is supplied to the other input terminal of the pixel value storage register 42 with a multiplexer. The output of the arithmetic unit 13 is sent to the pixel value storage register 30 and also to the arithmetic unit 14.

Further, the output of the arithmetic unit 14 is
It is sent to the next arithmetic unit 15 and also to the input terminal of the pixel value storage register 38. The register 3
The output of 8 is supplied to the other input terminal of the pixel value storage register 43 with a multiplexer to which the output of the arithmetic unit 15 is supplied to one input terminal.
The output of the arithmetic unit 16 is supplied to one input terminal of the output of the above, and is supplied to the other input terminal of the pixel value storage register 44 with a multiplexer. The output of the arithmetic unit 17 is sent to the pixel value storage register 33 and also to the arithmetic unit 18.

Here, each of the arithmetic units 10 to 21 in FIG. 10 described above is specifically configured as shown in FIG. In FIG. 11, the terminal 51 is shown in FIG.
The output from the other arithmetic unit 0 or the pixel value storing register of 0 is supplied, and the output from the other arithmetic unit of FIG. 10 or the pixel value storing register with a multiplexer is supplied to the terminal 55. The signals passed through the terminals 51 and 55 are sent to the pixel value storage register 58 after being multiplexed by the multiplexer (MPX) 57. The output of the pixel value storage register 58 is output from the terminals 52 and 54, and is also supplied to one input terminal of a difference absolute value calculator (| r−c |) 59. This difference absolute value calculator 5
9 to the other input terminal of FIG.
The pixel value r of the reference block Bp is supplied via the terminal 1 of. The output of the difference absolute value calculator 59 is the accumulator (A
CC) 60, cumulatively added by the accumulator 60, and then output from the terminal 56 as the sum of absolute difference D (i, j).

Further, the above-mentioned multiplexer-equipped pixel value storage registers 39 to 44 shown in FIG. 10 are specifically constructed as shown in FIG. This FIG.
11, the output of the pixel value storage register of FIG. 10 or the pixel value storage register with a multiplexer of the preceding stage is supplied to the terminal 72, and the terminal 73 of the corresponding image value storage register of FIG. Terminal 5
The output from 4 is supplied. The signals through the terminals 72 and 73 are sent to the pixel value storage register 76 after being multiplexed by the multiplexer 75. The output of the pixel value storage register 76 is sent to the subsequent stage configuration via the terminal 71.

Next, regarding the control method for realizing the motion vector detection processing by using the circuit configurations shown in FIGS. 10, 11, and 12, the timing of the motion vector detection control will be described with reference to FIG. explain.

As shown in FIG. 13, reference block B
The pixel value r of p is given to every arithmetic unit every clock cycle. That is, the reference block B
With respect to the pixel value r of p, each arithmetic unit operates on the same pixel value r in a certain clock cycle.

Further, the pixel value c of the candidate block Bb is divided into two regions, an upper half and a lower half of the search range E,
The signals are sequentially input to the two input terminals 2 and 3 shown in FIG. Further, the pixel value c of the candidate block Bb is transferred to the pixel value storage register in the subsequent stage every clock cycle. However, it is transferred to the pixel value storage register 58 of the arithmetic unit shown in FIG. 11 once every four clock cycles. In this way, with respect to the pixel value c of the candidate block Bb, as shown in FIG. 13, each arithmetic unit operates on a different pixel value c in a certain clock cycle.

In the conventional arithmetic circuit, by performing the above-mentioned control, each arithmetic unit outputs the sum of absolute differences simultaneously every 12 clock cycles (output from the output terminal 56 of FIG. 10). ). After that, by comparing the magnitudes of these sums of absolute differences D (i, j),
The motion vector MV (x, y) is calculated. At this time, FIG.
In the next clock cycle, the accumulator 60 shown in No. 1 outputs the sum of absolute differences D for the next reference block Bp.
Since the accumulation of (i, j) is started without interruption, it is necessary to store all the difference absolute value sums D (i, j) in the register and then perform the magnitude comparison operation.

The above is the description of the conventional circuit configuration for performing the motion vector detection processing of only the frame.

On the other hand, a conventional circuit configuration that can also be applied to a field-based motion vector detection process (hereinafter referred to as a field-based motion vector detection process) will be described below. In this field-based motion vector detection processing, three motion vectors are obtained for each of the even field, the odd field, and the frame. Here, the example used in the above description of the motion vector detection processing of only the frame is used again (see FIG. 9).

Here, as a premise, the reference block Bp0
The pixel values r _{a to} r _{l of} are classified into the following two groups corresponding to even and odd fields. That is, for example, in an even field, {r _a , r _c ,
r _e , r _g , r _i , r _k }, and the odd fields are divided into groups {r _b , r _d , r _f , r _h , r _j , r _l }.

Based on the above premise, the procedure of the field corresponding motion vector detecting process will be described below with reference to FIG.

First, the case of an even field will be described. In this case, the pixel value r of the even field of the reference block Bp0 and the search range E0 for the reference block Bp0
Using the pixel values c _{0 to} c ₃₄ of all the candidate blocks Bb0 (there are 12) in the above, the following formulas (15) to (26) are calculated based on the above formula (1). And the sum of absolute differences in even fields D _e (i, j) (0 ≦ i <
2,0 ≦ j <3) is calculated.

[0049]

D _e (0,0) = | r _a −c ₀ | + | r _c −c ₂ | + | r _e −c ₇ | + | r _g −c ₉ | + | r _i −c ₁₄ │ + │r _k −c ₁₆ │ ・ ・ ・ ・ (15)

[0050]

D _e (0,1) = | r _a −c ₁ | + | r _c −c ₃ | + | r _e −c ₈ | + | r _g −c ₁₀ | + | r _i −c ₁₅ | + | R _k −c ₁₇ | ··· (16)

[0051]

D _e (0,2) = | r _a −c ₂ | + | r _c −c ₄ | + | r _e −c ₉ | + | r _g −c ₁₁ | + | r _i −c ₁₆ │ + │r _k −c ₁₈ │ ・ ・ ・ ・ (17)

[0052]

D _e (0,3) = | r _a −c ₃ | + | r _c −c ₅ | + | r _e −c ₁₀ | + | r _g −c ₁₂ | + | r _i −c ₁₇ │ + │r _k -c ₁₉ │ ・ ・ ・ ・ (18)

[0053]

D _e (1,0) = | r _a −c ₇ | + | r _c −c ₉ | + | r _e −c ₁₄ | + | r _g −c ₁₆ | + | r _i −c ₂₁ │ + │r _k -c ₂₃ │ ・ ・ ・ ・ (19)

[0054]

D _e (1,1) = | r _a −c ₈ | + | r _c −c ₁₀ | + | r _e −c ₁₅ | + | r _g −c ₁₇ | + | r _i −c ₂₂ │ + │r _k −c ₂₄ │ ・ ・ ・ ・ (20)

[0055]

[Equation 21] D _e (1,2) = | r _a −c ₉ | + | r _c −c ₁₁ | + | r _e −c ₁₆ | + | r _g −c ₁₈ | + | r _i −c ₂₃ │ + │r _k −c ₂₅ │ ・ ・ ・ ・ (21)

[0056]

D _e (1,3) = | r _a −c ₁₀ | + | r _c −c ₁₂ | + | r _e −c ₁₇ | + | r _g −c ₁₉ | + | r _i −c ₂₄ │ + │r _k -c ₂₆ │ ・ ・ ・ ・ (22)

[0057]

D _e (2,0) = | r _a −c ₁₄ | + | r _c −c ₁₆ | + | r _e −c ₂₁ | + | r _g −c ₂₃ | + | r _i −c ₂₈ │ + │r _k −c ₃₀ │ ・ ・ ・ ・ (23)

[0058]

D _e (2,1) = | r _a −c ₁₅ | + | r _c −c ₁₇ | + | r _e −c ₂₂ | + | r _g −c ₂₄ | + | r _i −c ₂₉ │ + │r _k −c ₃₁ │ ・ ・ ・ ・ (24)

[0059]

D _e (2,2) = | r _a −c ₁₆ | + | r _c −c ₁₈ | + | r _e −c ₂₃ | + | r _g −c ₂₅ | + | r _i −c ₃₀ │ + │r _k -c ₃₂ │ ・ ・ ・ ・ (25)

[0060]

D _e (2,3) = | r _a −c ₁₇ | + | r _c −c ₁₉ | + | r _e −c ₂₄ | + | r _g −c ₂₆ | + | r _i −c ₃₁ │ + │r _k -c ₃₃ │ ・ ・ ・ ・ (26)

Next, the case of odd fields will be described. Pixel value r of odd field of reference block Bp0
As for the even field described above,
Pixel values c _{0 to} c of all candidate blocks Bb0 (there are 12) in the search range E0 with respect to the reference block Bp0
Based on the above equation (1) using ₃₄ and
Calculations such as (27) to (38) are performed, and the sum of absolute differences D _o (i, j) in the odd field (0 ≦ i <2, 0 ≦ j <
3) is asked.

[0062]

[Number 27] _{D o (0,0) = | r} b -c 1 | + | r d -c 3 | + | r f -c 8 | + | r h -c 10 | + | r j -c 15 _{| + | r l -c 17 |} ···· (27)

[0063]

Equation 28] _{D o (0,1) = | r} b -c 2 | + | r d -c 4 | + | r f -c 9 | + | r h -c 11 | + | r j -c 16 │ + │r _l −c ₁₈ ｜ ・ ・ ・ ・ (28)

[0064]

[Number 29] _{D o (0,2) = | r} b -c 3 | + | r d -c 5 | + | r f -c 10 | + | r h -c 12 | + | r j -c 17 │ + │r _l −c ₁₉ ｜ ・ ・ ・ ・ (29)

[0065]

Equation 30] _{D o (0,3) = | r} b -c 4 | + | r d -c 6 | + | r f -c 11 | + | r h -c 13 | + | r j -c 18 │ + │r _l −c ₂₀ │ ・ ・ ・ ・ (30)

[0066]

[Number 31] _{D o (1,0) = | r} b -c 8 | + | r d -c 10 | + | r f -c 15 | + | r h -c 17 | + | r j -c 22 │ + │r _l −c ₂₄ │ ・ ・ ・ ・ (31)

[0067]

[Number 32] _{D o (1,1) = | r} b -c 9 | + | r d -c 11 | + | r f -c 16 | + | r h -c 18 | + | r j -c 23 _{| + | r l -c 25 |} ···· (32)

[0068]

[Number 33] _{D o (1,2) = | r} b -c 10 | + | r d -c 12 | + | r f -c 17 | + | r h -c 19 | + | r j -c 24 │ + │r _l −c ₂₆ │ ・ ・ ・ ・ (33)

[0069]

Equation 34] _{D o (1,3) = | r} b -c 11 | + | r d -c 13 | + | r f -c 18 | + | r h -c 20 | + | r j -c 25 │ + │r _l −c ₂₇ │ ・ ・ ・ ・ (34)

[0070]

[Number 35] _{D o (2,0) = | r} b -c 15 | + | r d -c 17 | + | r f -c 22 | + | r h -c 24 | + | r j -c 29 │ + │r _l −c ₃₁ │ ・ ・ ・ ・ (35)

[0071]

Equation 36] _{D o (2,1) = | r} b -c 16 | + | r d -c 18 | + | r f -c 23 | + | r h -c 25 | + | r j -c 30 │ + _│rl- c ₃₂ │ ・ ・ ・ ・ (36)

[0072]

[Number 37] _{D o (2,2) = | r} b -c 17 | + | r d -c 19 | + | r f -c 24 | + | r h -c 26 | + | r j -c 31 │ + │r _l −c ₃₃ │ ・ ・ ・ ・ (37)

[0073]

Equation 38] _{D o (2,3) = | r} b -c 18 | + | r d -c 20 | + | r f -c 25 | + | r h -c 27 | + | r j -c 32 │ + │r _l −c ₃₄ │ ・ ・ ・ ・ (38)

Finally, the case of the frame is similar to the case of the motion vector detection processing of only the frame described above, and the pixel values c (c ₀ ~) of all candidate blocks Bb0 within the search range E0 with respect to the reference block Bp0. c ₃₄ ) is calculated based on the above-mentioned mathematical expression (1) as in the mathematical expressions (3) to (14), and the sum of absolute differences D (i, j) in the frame (0 ≦ i <2 0 ≦ j <3) is calculated.

Next, for all of the sums of absolute differences D _e (i, j) (0 ≦ i <2, 0 ≦ j <3) in the even field, the minimum difference based on the above equation (2). The sum of absolute values minD _e (i, j) is obtained, and the motion vector MV _e (x, y) in the even field is obtained.

Further, for all of the sums of absolute differences D _o (i, j) (0 ≦ i <2, 0 ≦ j <3) in the above-mentioned odd field, the minimum absolute difference is calculated based on the equation (2). The value sum minD _o (i, j) is obtained to obtain the motion vector MV _o (x, y) in the odd field.

Similarly, for all of the sums of absolute differences D (i, j) (0≤i <2, 0≤j <3) in the frame, the sum of absolute differences is minimized based on the equation (2). m
inD (i, j) is calculated, and the motion vector M in the frame
Get V (x, y).

Next, the pixel values r _{a ′ to} r _{l ′} of the reference block Bp1 adjacent to the reference block Bp0 and all the candidate blocks Bb1 within the search range E1 of the reference block Bp1.
For the pixel values c _{21 to} c _{55 of} (there are twelve), the sum of absolute differences D ′ _e (i, j) (0 ≦ i < 2,0 ≦
j <3), the sum of absolute difference values D ′ _o (i, j) (0 ≦ i <2, 0 ≦ j <3) in the odd field, and the sum of absolute difference values D ′ (i, j) (0 ≤ i <2, 0 ≤ j <
3) is asked.

Here, all the sums of absolute differences D ′ _e (i, j) (0 ≦ i <2, 0 ≦ j <3) obtained as described above,
D' _o (i, j) (0≤i <2, 0≤j <3), D '(i, j)
For (0 ≦ i <2, 0 ≦ j <3), the minimum absolute difference sum minD ′ is obtained based on the equation (2).
_e (i, j), minD ' _o (i, j), minD' (i, j) are obtained, and three types of motion vectors MV _e (x, y) and MV in the even field, the odd field, and the frame, respectively. _o
(x, y) and MV (x, y) are obtained.

Similarly, the above operation is repeated for all reference blocks Bp of the current frame Fp, and three kinds of motion vectors MV _e (x, y) and MV _o (even fields, odd fields and frames) x, y),
Calculate MV (x, y).

Conventionally, the field-based motion vector detection processing as described above is also realized by the circuit configuration shown in FIGS. 10, 11 and 12. That is, FIG.
0, FIG. 11 and FIG. 12 are provided with three motion vector detection circuits (arithmetic circuits) for performing motion vector detection processing in even fields, motion vector detection processing in odd fields, and motion vector detection processing in frames. , These three motion vector detection circuits are separately performed.

[0082]

As described above, in the circuit configuration of the conventional field-based motion vector detection processing, the sum of absolute differences between the even field, the odd field and the frame is obtained by separately provided circuits. I am trying.

That is, conventionally, in order to perform the field-based motion vector detection processing, three motion vector detection circuits are required for each of the even field, the odd field, and the frame, thus increasing the amount of hardware.

Further, conventionally, in order to perform the field-based motion vector detection processing, by preparing three motion vector detection circuits as described above, the reference block is provided for each of these three motion vector detection circuits. It becomes necessary to separately supply the pixel value of P and the pixel value of the candidate block. Therefore, in comparison with the circuit configuration in the case of performing the motion vector detection processing of only the frame described above, the circuit configuration for performing the field corresponding motion vector detection processing is
An external additional circuit becomes necessary and complicated, and the number of ports of the frame memory that supplies each pixel value to the motion vector detection circuit also increases.

Therefore, an object of the present invention is to provide an arithmetic circuit capable of reducing the amount of hardware, the number of external additional circuits, and the number of ports of the frame memory.

[0086]

The present invention has been proposed in order to achieve the above-mentioned object. The block size of the reference block of the current frame is M × N pixels, and the number of candidate blocks of the previous frame is An arithmetic circuit that performs a full search by M × N and performs a motion vector detection by a block matching method, and a register that holds each pixel value of a reference block sequentially input every clock cycle for a predetermined clock cycle. , A multiplexer that appropriately switches the pixel value of the candidate block between an odd-numbered column and an even-numbered column, and a difference absolute value (or difference) between the pixel value of the reference block output from the register and the pixel value of the candidate block output from the multiplexer. A calculation unit having a difference absolute value calculator (or a difference square calculator) for calculating a square value is M × N. In addition to providing the arithmetic units, the arithmetic units are arranged in a matrix of M × N, the outputs of the even-numbered arithmetic units are pipeline-connected via the first adders, and the outputs of the odd-numbered arithmetic units are respectively output. Pipeline connection is made via the second adder of a different system from the first adder, and the pixel values of the reference block and the candidate block are arranged in a certain order in the difference absolute value calculator (or difference The difference absolute value sum in the even field (or the difference sum of squares) and the difference absolute value sum in the odd field (or the difference square sum) are supplied to the even-numbered field. Absolute difference value in the frame obtained by adding the sum of values (or sum of squared differences) and the sum of absolute difference in odd fields (or sum of squared differences) Then, the sum (or the sum of squared differences) is obtained, and then the sum of the absolute difference values (or the sum of the squared differences) in the even field and the sum of the absolute difference values (or the sum of the squared difference) in the odd field and the absolute value of the difference in the frame are obtained. The minimum difference absolute value sum (or difference square sum) is obtained from the sum (or difference square sum) to obtain three types of motion vectors in the even field, the motion vector in the odd field, and the motion vector in the frame. The motion vector detecting process is performed to simultaneously obtain the motion vector.

Further, the arithmetic circuit of the present invention uses a register for holding each pixel value of the reference block sequentially input every one clock cycle for a predetermined clock cycle, and a pixel value of the candidate block in an odd column and an even column. A multiplexer that switches appropriately, and a difference absolute value calculator (or difference) that calculates a difference absolute value (or difference square value) between the pixel value of the reference block output from the register and the pixel value of the candidate block output from the multiplexer. Squared arithmetic unit), an even-numbered accumulator that cumulatively adds even-numbered outputs from the difference absolute value arithmetic unit (or difference squared arithmetic unit), and the difference absolute value arithmetic unit (or difference squared arithmetic unit)
M × N arithmetic units having an odd-numbered accumulator for cumulatively adding the odd-numbered outputs from M to N are arranged, and the arithmetic units are arranged in a matrix of M × N to be interconnected, And by supplying the pixel values of the candidate blocks in a fixed order, the difference absolute value sum in the even field (or the difference squared sum) and the difference absolute value sum in the odd field (or the difference squared sum) are obtained. The difference absolute value sum (or difference square sum) in the frame obtained by adding the difference absolute value sum (or difference square sum) in these even fields and the difference absolute value sum (or difference square sum) in the odd field is calculated. , And then the sum of absolute differences (or the sum of squared differences) in the even fields and the sum of absolute difference (or the difference squares) in the odd fields. Multiply sum) and the sum of absolute differences between frames (or the sum of squared differences) to obtain the minimum sum of absolute differences (or the sum of squared differences) to obtain a motion vector in an even field and a motion vector in an odd field. , And a motion vector detection process for simultaneously obtaining three types of motion vectors in a frame.

Here, the arithmetic circuit of the present invention further calculates the sum of absolute differences (or the sum of squared differences) with respect to the reference block for all the candidate blocks obtained in each of the odd field, the even field, and the frame. It has a memory for storing, and from each sum of absolute difference values (or sum of squared differences) stored in this memory, obtains the minimum sum of absolute difference (or sum of squared differences) for obtaining the motion vector. I am trying.

[0089]

According to the arithmetic circuit of the present invention, the arithmetic units for obtaining the absolute difference are arranged in a matrix of M × N, and among the outputs of these arithmetic units, the outputs of the even-numbered arithmetic units are respectively output as the first output. 1 is connected in a pipeline through an adder, and the outputs of the odd-numbered arithmetic units are connected in pipeline through a second adder in a system different from that of the first adder. The output of the first adder of is the sum of absolute differences (or the sum of squared differences) in the even field, and the output of the second adder in the final stage is the sum of the absolute difference (or the sum of squared differences) in the odd fields. . If these are further added, the sum of absolute differences (or the sum of squared differences) in the frame can be obtained.

Further, according to the arithmetic circuit of the present invention, an arithmetic unit for accumulating the odd-numbered difference absolute values and the even-numbered difference absolute values separately to obtain the difference absolute value sum is M × N.
Since they are arranged in a matrix form and are connected to each other, from each arithmetic unit, there are two sums of difference absolute values (or sum of squared differences) in even fields and sums of difference absolute values (or sum of squared differences) in odd fields. Output is obtained. If these are further added, the sum of absolute differences (or the sum of squared differences) in the frame can be obtained.

[0091]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the arithmetic circuit of the present invention will be described below with reference to the drawings.

The arithmetic circuit of the embodiment of the present invention uses the current frame F
The block size of the reference block Bp of p is M × N pixels (for example, 3 × 4 pixels in this embodiment), and the previous frame F
The number of candidate blocks Bb of b is M × N (for example, 3 × 4 in this embodiment), and is an arithmetic circuit that performs a full search by a block matching method to detect a motion vector.

Here, in the arithmetic circuit of the first embodiment of the present invention, as shown in FIGS. 1 and 2, each pixel value r of the reference block Bp, which is sequentially input every one clock cycle, is converted into a predetermined clock cycle. Between (for example, 12 clock cycles)
A register 182 for holding, a multiplexer 184 for appropriately switching the pixel value c of the candidate block Bb between an odd column and an even column, a pixel value r of the reference block Bp output from the register 182, and the multiplexer 18
The calculation unit (PE) having a difference absolute value calculator 185 (or a difference square calculator) for calculating a difference absolute value (or a difference square value) with respect to the pixel value c of the candidate block Bb outputted from No. 4 is M ×. N (3 × 4 = 12 arithmetic units 190 to 201) are provided and the arithmetic unit 1
90 to 201 are arranged in a matrix of M × N (that is, 3 × 4).

Further, the arithmetic circuit of the first embodiment has the even-numbered arithmetic units 190, 192, 194, 196 and.
The outputs of 198 and 200 are pipeline-connected via the corresponding first adders 321 to 325, and the odd-numbered arithmetic units 191, 193, 195, 197, 1 are connected.
The outputs of 99 and 201 are respectively output to the first adder 321.
˜325 and pipelines via second adders 326 to 330 of different systems, and the pixel values of the reference block and the candidate block are arranged in a fixed order in the arithmetic units 190.
By supplying to the difference absolute value calculator 185 ～201 (or squared difference calculator), sum of absolute differences D _e in the even field (i, j) (or the sum of squared differences), absolute differences in the odd field The sum D _o (i, j) (or the sum of the difference squares) is obtained, and the sum of the difference absolute values (or the sum of the difference squares) in the even fields and the sum of the difference absolute values (or the sum of the difference squares) in the odd fields are obtained. By adding in the adder 341, the sum of absolute differences D (i, j) (or the sum of squared differences) in the frame is obtained.

In the arithmetic circuit of this embodiment, after that,
Sum of absolute differences D obtained in these even fields
_e (i, j) (or sum of squared differences) and sum of absolute difference in odd fields D _o (i, j) (sum of squared differences) and sum of absolute difference in frame D (i, j) (or squared difference) The sum of the absolute differences (or the sum of the squared differences) that minimizes the sum of the motion vectors MV _e (x, y) in the even field and the motion vector MV _o (x, y) in the odd field. Thus, it is possible to realize the motion vector detection processing for simultaneously obtaining three types of motion vectors MV (x, y) of the motion vectors in the frame.

Although not shown, the arithmetic circuit of the present embodiment further includes the sum of absolute differences between the reference blocks of all candidate blocks obtained in each of the odd field, the even field, and the frame. D _e
(i, j), D _o (i, j), D (i, j) (or a sum of squared differences) is included in the memory, and the sum of absolute differences (or the difference) stored in the memory is included. Sum of squares), the minimum sum of absolute differences (or the sum of squared differences) for obtaining the above motion vectors MV _e (x, y), MV _o (x, y), and MV (x, y)
I'm trying to ask.

In the following embodiments, the configuration for performing the difference absolute value calculation is described.

Here, the circuit of this embodiment realizes an arithmetic circuit for carrying out the field-based motion vector detection processing based on the following points.

That is, the sum of absolute differences D _e (i, j) (0 ≦ i <2, 0 ≦ j <in the even field described above
3), sum of absolute difference D in the odd field
_o (i, j) (0 ≦ i <2, 0 ≦ j <3), sum of absolute difference in frame D (i, j) (0 ≦ i <2, 0 ≦ j <3)
Holds the relationship as shown in the following mathematical expression (39).

[0100]

(39) D (i, j) = D _e (i, j) + D _o (i, j) (39)

From this equation (39), the sum of absolute differences D (i, j) in the frame is the sum of absolute differences D _e (i, j) in the even field and the sum of absolute differences D _o (i in the odd field. , j).

The arithmetic circuit of the first embodiment of the present invention will be described in detail below with reference to FIGS. In the present embodiment, the circuit configuration and control method of the present invention will be described using an example of the motion vector detection processing given for explaining the above-mentioned conventional circuit configuration.

In the embodiment of the present invention, the above-mentioned field-based motion vector detection processing is realized by the circuit configuration shown in FIGS. FIG. 1 shows the overall configuration of an arithmetic circuit that performs motion vector detection processing according to the embodiment of the present invention. As described above, the circuit includes the arithmetic units 190 to 201.
Are arranged in a 3 × 4 matrix.

In FIG. 1, the terminal 180 is supplied with the pixel value c of the candidate block Bb in the odd column of the previous frame Fb, and the pixel value c is supplied to each of the arithmetic units 190 to 20.
1 to the first input terminal. Also, the pixel value c of the candidate block Bb in the even column of the previous frame Fb is supplied to the terminal 189, and the pixel value c is supplied to each arithmetic unit 190.
~ 201 to the second input terminal. The pixel value r of the reference block Bp is supplied to the terminal 181, and is sent to the third input terminal of each of the arithmetic units 190 to 201. The absolute difference value is output from the output terminals of each of the arithmetic units 190 to 201.

Here, each of the arithmetic units 190 to 20
1 has an internal configuration as shown in FIG. That is, the arithmetic units 190 to 201 are the multiplexer 1
84, a pixel value storage register 182, and a difference absolute value calculator 185. In FIG. 2, the pixel value c of the odd block candidate block Bb of the previous frame Fb is supplied to the first input terminal 172 through the terminal 180 of FIG. 1, and the second input terminal 173 is supplied. Terminal 1 of FIG. 1 above
The pixel value c of the candidate block Bb in the even column of the previous frame Fb is supplied via 89. These pixel values c are appropriately switched by the multiplexer 184 and then sent to one input terminal of the difference absolute value calculator 185. Further, the pixel value r of the reference block Bp is supplied to the third terminal 171 via the terminal 181 of FIG. The pixel value r is sent to the other input terminal of the difference absolute value calculator 185 via the pixel value storage register 182. The absolute difference value calculated by the absolute difference value calculator 185 is output from the terminal 183.

Returning to FIG. 1, in the apparatus of this embodiment, as described above, each of the even-numbered arithmetic units 190, 192,
The outputs of 194, 196, 198, and 200 are the first
Of the odd-numbered arithmetic units 191, 193, 19
The outputs of 5, 197, 199, and 201 are the second output, respectively.
Pipelined through adders 326 to 330.

That is, starting from each of the even-numbered arithmetic units, in the apparatus of this embodiment, the output of the arithmetic unit 190 and the output of the arithmetic unit 192 are added by the adder 321, and the addition output of the adder 321 and the above arithmetic operation. The output of the unit 194 is added by the adder 322, the added output of the adder 322 and the output of the arithmetic unit 196 are added by the adder 323, and the added output of the adder 323 and the output of the arithmetic unit 198 are added. And are added by the adder 324, and the addition output of the adder 324 and the output of the arithmetic unit 200 are added by the adder 325. As a result, the addition output of the first adder 325 at the final stage becomes the difference absolute value sum D _e (i, j) in the even field. The sum of absolute differences D _e (i, j) in this even field is
It is output from the even field output terminal 342 of the circuit of this embodiment.

In each odd-numbered arithmetic unit, the output of the arithmetic unit 191 and the output of the arithmetic unit 193 are added by the adder 326, and the addition output of the adder 326 and the output of the arithmetic unit 195 are added. Bowl 32
7, the addition output of the adder 327 and the output of the arithmetic unit 197 are added by the adder 328, and the addition output of the adder 328 and the output of the arithmetic unit 199 are added by the adder 329. , The addition output of the adder 329 and the output of the arithmetic unit 201 are the adder 3
It is added at 30. As a result, the addition output of the second adder 330 in the final stage becomes the difference absolute value sum D _o (i, j) in the odd field. The sum of absolute differences D _o (i, j) in the odd field is output from the odd field output terminal 343 of the circuit of this embodiment.

In FIG. 1, registers 301 to 319 connected to the input terminal side and output terminal side of the first and second adders (inserted and connected between the adders).
Is a pipeline register.

Further, the sum of absolute differences D _e (i, j) in the even field and the sum of absolute differences D _o (i, j) in the odd field are added by the adder 341. The addition output of the adder 341 becomes the sum of absolute differences D (i, j) in the frame. The sum of absolute differences D (i, j) in this frame is output from the frame output terminal 344 of the circuit of this embodiment.

Next, a control method for realizing the field-based motion vector detection processing by using the circuit configurations shown in FIGS. 1 and 2 will be described. FIGS. 3 and 4 show operation timings in the field-based motion vector detection control using the circuit configurations shown in FIGS. 1 and 2.
Note that FIG. 3 shows the processing timing in the even field, and FIG. 4 shows the processing timing in the odd field.

3 and 4, the pixel value r of the reference block Bp of the current field Fb is sequentially input to the pixel value storage register 182 of each of the arithmetic units 190 to 201 of FIG. 1 every clock cycle. It The register 182 receives the pixel value r of the input reference block Bp.
Is held for 12 clock cycles. Therefore, each of the arithmetic units 190 to 201 performs the absolute difference calculation for the pixel value r of the same reference block Bp for 12 clock cycles. However, in each of the arithmetic units 190 to 201, the absolute difference calculation is performed on the different pixel values r of the reference block Bp.

Further, the pixel value c of the candidate block Bb is divided into two areas, an even column and an odd column of the previous frame Fb, and the two input terminals 180 and 182 shown in FIG.
Is sequentially input to each of the arithmetic units 190 to 201 in a fixed order. In each arithmetic unit 190 to 201, FIG.
Alternatively, the multiplexer 1 in the arithmetic unit is supplied so that the pixel values c of the candidate block Bb are supplied in the order shown in FIG.
The two pixel values c are appropriately switched by 84. By doing so, with respect to the pixel value c of the candidate block Bb, as shown in FIG. 3 or 4, in each clock cycle, each of the arithmetic units 190 to 201 performs an arithmetic operation on the two pixel values c. .

Further, in the circuit of this embodiment, the even-numbered arithmetic units 190, 192, 194, 196, 198,
The output from each differential absolute value calculator 185 of 200 is the first adder 321 pipeline-connected as described above.
˜325 are sequentially added to calculate the difference absolute value sum D _e (i, j) in the even field. On the other hand, odd-numbered arithmetic units 191, 193, 195, 197, 1
The outputs from the differential absolute value calculators 185 of 99 and 201 are also sequentially added using the second adders 326 to 330 connected in the pipeline as described above, and the difference absolute value sum D _o (in the odd field) i, j) is calculated. Further, in the circuit of the present embodiment, the sums of absolute differences D _e (i, j) and D _o (i,
j) is added by adder 341 as described above,
The sum of absolute differences D (i, j) in the frame is calculated.

By performing the control as described above, in the circuit of this embodiment, there are three types of absolute difference from the even field output terminal 342, the odd field output terminal 343, and the frame output terminal 344 for each clock cycle. The sum of values will be output. By comparing the magnitudes of these sums of absolute differences, three types of motion vectors M in each of the even field, the odd field, and the frame
V _e (x, y), MV _o (x, y), and MV (x, y) can be obtained.

Next, in the arithmetic circuit of the second embodiment of the present invention, as shown in FIGS. 5 and 6, each pixel value r of the reference block Bp, which is sequentially input every clock cycle, is converted into a predetermined clock cycle. Between (for example, 12 clock cycles)
A register 232 for holding, a multiplexer 234 that appropriately switches the pixel value c of the candidate block Bb between an even column and an odd column, a pixel value r of the reference block Bp output from the register 232, and the multiplexer 23.
From the difference absolute value calculator 235 (or difference square calculator) for calculating the difference absolute value (or difference square value) with the pixel value c of the candidate block Bb output from 4; An even-numbered accumulator 245 that cumulatively adds even-numbered outputs and an odd-numbered accumulator 246 that cumulatively adds odd-numbered outputs from the difference absolute value calculator 235.
M × N (3 × 4 arithmetic units 210 to 221) arithmetic units (PE) having and are provided, and the arithmetic units 210 to 221 are arranged in a matrix of M × N (3 × 4). Interconnected.

Here, in the circuit of this embodiment, by supplying the pixel values r and c of the reference block Bp and the candidate block Bb in a fixed order, the sum of absolute differences between even fields D _e (i, j) (Or sum of squared differences) and sum of absolute differences D _o (i, j) in odd fields (or sum of squared differences), and further sum of absolute differences (or sum of squared differences) in these even fields and odd number The sum of absolute differences (or the sum of squared differences) in the field is added to obtain the sum of absolute differences D (i, j) (or the sum of squared differences) in the frame.

Also in the arithmetic circuit of the second embodiment,
After that, the sum of absolute differences D _e (i, j) (or the sum of squared differences) in the even field and the sum D _o (i, j) of absolute differences in the odd fields (or the sum of squared differences) and the frame From the sum of absolute differences D (i, j) (or the sum of squared differences), the minimum sum of absolute differences (or the sum of squared differences) is calculated to obtain the motion vector MV _e (x, y) in the even field. , It is possible to realize the motion vector detection processing for simultaneously obtaining three kinds of motion vectors of the motion vector MV _o (x, y) in the odd field and the motion vector MV (x, y) in the frame.

Although not shown in the figure, the arithmetic circuit of the present embodiment further includes the sum of absolute differences D between all the candidate blocks obtained in each of the odd field, the even field, and the frame and the reference block. _e
(i, j), D _o (i, j), D (i, j) (or the sum of squared differences) is included in the memory, and the sum of absolute differences (or the difference) stored in this memory is included. Sum of squares), the minimum sum of absolute differences (or the sum of squared differences) for obtaining the above motion vectors MV _e (x, y), MV _o (x, y), and MV (x, y)
I'm trying to ask.

In FIG. 5, the pixel value c of the candidate block Bb in the odd column of the previous frame Fb is supplied to the terminal 236, and the pixel value c is supplied to each arithmetic unit 210.
~ 221 first input terminals. Also, the terminal 23
8 is a candidate block Bb in the even column of the previous frame Fb.
Is supplied to the second input terminal of each of the arithmetic units 210 to 221. Terminal 23
7 is supplied with the pixel value r of the reference block Bp, is sent to the third input terminal of the arithmetic unit 210 of the first stage of the arithmetic units 210 to 221 that are connected in cascade, and sequentially,
It is sent to the third input terminal of the arithmetic unit in the next stage. From each of the two output terminals 247 and 248 corresponding to each of the arithmetic units 210 to 221, the sum of absolute differences D _e (i, j) in the even field and D _o in the odd field are outputted.
(i, j) is output.

Further, each of the arithmetic units 210 to 210 shown in FIG.
221 is a multiplexer 234, as shown in FIG.
Pixel value storage register 232, difference absolute value calculator 23
5 and the sum of absolute differences D _e (i, i
An accumulator (ACC) 245 for obtaining j) and an accumulator (ACC) 246 for obtaining the difference absolute value sum D _o (i, j) in the odd field.

In FIG. 6, the first input terminal 2 is
41 includes a front frame F through the terminal 236 of FIG.
The pixel value c of the candidate block Bb of the odd column of b is supplied, and the second input terminal 234 receives the candidate block Bb of the even column of the previous frame Fb via the terminal 238 of FIG.
Pixel value c of is supplied. These pixel values c are appropriately switched by the multiplexer 234 and then sent to one input terminal of the difference absolute value calculator 235. Further, the pixel value r of the reference block Bp or the pixel value r from the terminal 244 of the preceding arithmetic unit is supplied to the third input terminal 241 via the terminal 237 of FIG. The pixel value r is sent to the other input terminal of the difference absolute value calculator 235 via the pixel value storage register 232, and is also sent from the terminal 244 to the calculation unit of the next stage. The output of the difference absolute value calculator 235 is an accumulator 245 for obtaining the difference absolute value sum D _e (i, j) in the even field and the difference absolute value sum D _o in the odd field.
It is sent to the accumulator 246 for obtaining (i, j), and after being accumulated in these accumulators 245 and 246, these accumulators 24
It is output from terminals 247 and 248 corresponding to 5,246 as the sum of absolute differences D _e (i, j) in the even field and the sum of absolute differences D _o (i, j) in the odd field.

Next, a control system for realizing field-based motion vector detection using the circuit configuration of the second embodiment shown in FIGS. 5 and 6 will be described. In Figure 7,
The operation timing in the field-based motion vector detection control using the circuit configurations shown in FIGS. 5 and 6 is shown.

As shown in FIG. 7, the reference block Bp
The pixel value r of is sequentially input to the pixel value storage register 232 of the arithmetic unit 210 at the first stage of FIG. 5 every clock cycle. The input pixel value r of the reference block Bp is supplied to all the arithmetic units 210 to 221 in FIG. 5 in 12 clock cycles. That is, in each arithmetic unit 210-221, the reference block B
The difference absolute value calculation is performed on the pixel values r having different p.

Further, the pixel value c of the candidate block Bb is divided into two areas of even-numbered columns and odd-numbered columns of the previous frame Fb, and the two input terminals 236 and 238 shown in FIG.
Is sequentially input to each arithmetic unit 210 to 221 in a fixed order. In each of the arithmetic units 210 to 221, FIG.
Two pixel values c are appropriately switched by the multiplexer 234 in the arithmetic unit so that the pixel values c of the candidate block Bb are supplied in the order shown in FIG. By doing so, for the pixel value c of the candidate block Bb, as shown in FIG. 7, each arithmetic unit 210 to 221 performs an arithmetic operation on the two pixel values c in a certain clock cycle.

Further, in each of the arithmetic units 210 to 221, the even-numbered output from the difference absolute value calculator 235 is sent to the accumulator 245. Thereby, the accumulator 245
Then, the sum of absolute differences in even fields D _e (i, j)
Is calculated. On the other hand, the odd-numbered output from the absolute difference value calculator 235 is sent to the accumulator 246. As a result, the accumulator 246 calculates the sum of absolute differences D _o (i, j) in the odd field.

By performing the control as described above, in the present embodiment, the sum of absolute differences D _e (i, j) in even fields is sequentially obtained from each of the arithmetic units 210 to 221 in FIG. 5 every clock cycle. ) And the sum of absolute differences D _o (i, j) in the odd field are output (output terminal 24
7, 248). These difference absolute value sums D _e (i, j) and D _o (i, j) are compared in size to obtain two types of motion vectors MV _e (x, y) in each of the even field and the odd field. , MV _o (x, y)
Can be asked.

Furthermore, in the circuit of this embodiment, the sum of absolute differences D in these even and odd fields is used.
_e (i, j) and D _o (i, j) are added to obtain the difference absolute value sum D (i, j) in the frame, and the difference absolute value sum D (i, j) in this frame is compared in magnitude. Thus, the motion vector MV (x, y) in the frame can be obtained.

In each of the above-described embodiments, the field-based motion vector detection processing in the case where the size of the reference block Bp is 3 × 4 pixels and the number of candidate blocks Bb is also 3 × 4 has been described. The invention is not limited to these examples, and the size of the reference block Bp and the candidate block Bb
With the same number of, the motion vector detection process of any size of the reference block Bp can be realized.

As described above, according to the arithmetic circuits of the respective embodiments of the present invention, the even-numbered field, the odd-numbered field, and the difference absolute value sum in the frame shown in the equation (39) are used to obtain an even number. Sum of absolute differences in field D _e
(i, j) and the sum of absolute differences between odd fields D _o (i,
It is possible to obtain the sum of absolute differences D (i, j) in the frame from j).

In each of the circuits of the embodiments, by devising the pipeline connection (or the accumulator connection),
It is possible to perform the difference absolute value sum calculation in the even field and the difference absolute value sum calculation in the odd field using the pixel value c of the same candidate block Bp by one motion vector detection circuit.

Therefore, according to the arithmetic circuit of this embodiment, in the motion vector detection processing for a field, three types of motion vectors MV _e (x, y) and MV _o (x in each of an even field, an odd field and a frame are used. , y), M
It is possible to obtain V (x, y) with one motion vector detection circuit, and the hardware amount is 1/1 of the conventional circuit configuration.
It can be reduced to 3.

Further, the external additional circuit in the circuit configuration of the present embodiment has the same circuit configuration as in the case of performing the motion vector detection processing of only the frame, and the number of ports of the frame memory is the motion of only the frame. Since the circuit configuration is the same as in the case of performing the vector detection processing, the field-based motion vector detection processing can be realized without increasing the number of ports of the frame memory.

[0134]

As described above, according to the present invention, the reference block size is M × N, and the number of candidate blocks is also M × N.
If it is N, there are M × N number of difference absolute value calculators (or difference square calculators) for calculating the difference absolute value (or difference square value) between the pixel value of the reference block and the pixel value of the candidate block. Arithmetic units are arranged in a matrix of M × N, outputs of even-numbered arithmetic units are pipeline-connected via first adders, and outputs of odd-numbered arithmetic units are respectively subjected to first addition. Pipeline connection through a second adder of a different system from the operation unit, and in each operation unit, the pixel values of the reference block and the candidate block are supplied to the difference absolute value operation unit (or difference square operation unit) in a fixed order. By doing so, the difference absolute value (or the difference square value) between the pixel value of the reference block and the pixel value of the candidate block is accumulated by two accumulators for even number and odd number respectively, and the sum of absolute difference values is obtained. (Or the difference itself The M × N arithmetic units for obtaining the sum of multiplications are arranged in an M × N matrix and interconnected, and the pixel values of the reference block and the candidate block are supplied in a fixed order, so that an odd field, an even field , It is possible to obtain the sum of absolute differences between frames. Therefore, the arithmetic circuit of the present invention can reduce the amount of hardware, reduce the number of external additional circuits, and prevent the number of ports of the frame memory from increasing.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing an overall configuration of an arithmetic circuit of a first embodiment that performs a field-based motion vector detection process.

FIG. 2 is a block circuit diagram showing a specific configuration of an arithmetic unit of the arithmetic circuit of the first embodiment.

FIG. 3 is a diagram for explaining the control timing of motion vector detection processing in an even field in the arithmetic circuit of the first embodiment.

FIG. 4 is a diagram for explaining a control timing of a motion vector detection process in an odd field in the arithmetic circuit of the first embodiment.

FIG. 5 is a block circuit diagram showing an overall configuration of an arithmetic circuit of a second embodiment that performs field-based motion vector detection processing.

FIG. 6 is a block circuit diagram showing a specific configuration of an arithmetic unit of the arithmetic circuit according to the second embodiment.

FIG. 7 is a diagram for explaining the control timing of field-based motion vector detection processing in the arithmetic circuit of the second embodiment.

FIG. 8 is a diagram illustrating the principle of motion vector detection processing.

FIG. 9 is a diagram for explaining a motion vector detection process when the size of a reference block is 3 × 4 pixels and the number of candidate blocks is 3 × 4.

FIG. 10 is a block circuit diagram showing an overall configuration of a conventional arithmetic circuit that performs motion vector detection processing only for frames.

FIG. 11 is a block circuit diagram showing a specific configuration of an arithmetic unit of a conventional example circuit.

FIG. 12 is a block circuit diagram showing a specific configuration of a pixel value storage register with a multiplexer in a conventional circuit.

FIG. 13 is a diagram for explaining a control timing of a conventional motion vector detection process.

[Explanation of symbols]

190-201, 210-221 ... arithmetic unit 182, 232 ... register for storing pixel value 184, 234 ... multiplexer 185, 235 ... ··· Difference absolute value calculator 245, 246 ··· Accumulators 301 to 319 ··· Pipeline registers 321 to 330, 341・ ・ ・ ・ ・ Adder

Claims (6)

[Claims] 1. The block size of a reference block is M × N.
It is an arithmetic circuit that performs a full search by a block matching method to detect a motion vector with pixels and the number of candidate blocks is M × N, and the difference between the pixel value of the reference block and the pixel value of the candidate block is absolute. M × N arithmetic units having at least a difference absolute value arithmetic unit for calculating a value are provided, the arithmetic units are arranged in a matrix of M × N, and the outputs of the even-numbered arithmetic units are respectively added to the first addition. Connected in a pipeline through an adder, and the outputs of the odd-numbered arithmetic units are connected in a pipeline via the first adder and the second adder of another system, respectively, and the pixels of the reference block and the candidate block By supplying the values in a fixed order to the difference absolute value calculator of each of the above calculation units, the motion vector in the even field and the Operation circuit and performs a motion vector, at the same time obtaining the motion vector detection processing Three motion vector of the motion vectors in the frame. 2. The block size of the reference block is M × N.
An arithmetic circuit for performing a full search by a block matching method to detect a motion vector with pixels as the number of candidate blocks of M × N, and a squared difference between the pixel value of the reference block and the pixel value of the candidate block. M × N arithmetic units having at least a difference square arithmetic unit for calculating a value are provided, the arithmetic units are arranged in a matrix of M × N, and the output of each even-numbered arithmetic unit is a first adder. And the output of each odd-numbered arithmetic unit is pipeline-connected via the first adder and the second adder of another system, and the pixel values of the reference block and the candidate block are connected. Are supplied to the difference square calculator of each of the above arithmetic units in a fixed order, the motion vector in the even field and the motion vector in the odd field are Operation circuit and performs a vector, simultaneously obtains motion vector detection processing Three motion vector of the motion vectors in the frame. 3. The block size of the reference block is M × N
It is an arithmetic circuit that performs a full search by a block matching method to detect a motion vector with pixels and the number of candidate blocks is M × N, and the difference between the pixel value of the reference block and the pixel value of the candidate block is absolute. M × N calculation units for calculating a value and accumulating the odd-numbered difference absolute value and the even-numbered difference absolute value separately to obtain the difference absolute value sum are provided, and the calculation unit is an M × N matrix. Of the reference block and the candidate block are supplied in a fixed order, so that the motion vector in the even field, the motion vector in the odd field, and the motion vector in the frame are classified into three types. An arithmetic circuit characterized by performing motion vector detection processing for simultaneously obtaining motion vectors. 4. The block size of the reference block is M × N.
An arithmetic circuit for performing a full search by a block matching method to detect a motion vector with pixels as the number of candidate blocks of M × N, and a squared difference between the pixel value of the reference block and the pixel value of the candidate block. M × N calculation units for calculating a value and accumulating the odd-numbered difference square value and the even-numbered difference square value separately to obtain the sum of difference squares are provided, and the calculation units are arranged in a matrix of M × N. Are arranged and interconnected, and the pixel values of the reference block and the candidate block are supplied in a fixed order, so that there are three types of motion: a motion vector in an even field, a motion vector in an odd field, and a motion vector in a frame. An arithmetic circuit characterized by performing motion vector detection processing for simultaneously obtaining vectors. 5. The odd field, the even field,
The arithmetic circuit according to claim 1 or 3, further comprising a memory that stores a sum of absolute differences between the reference blocks and all the candidate blocks in each frame. 6. The odd field, the even field,
The arithmetic circuit according to claim 2 or 4, further comprising a memory that stores a sum of squared differences with reference blocks for all candidate blocks in each frame.