JPH06224948A - Data demodulator - Google Patents

Abstract

PURPOSE:To attain demodulation with high accuracy by providing a couple of BPFs of a narrow band, a couple of integration circuits to obtain an integration value for a prescribed period, a comparator receiving a difference between the integration values, and a discrimination circuit discriminating the polarity of the output of the comparator in the demodulator. CONSTITUTION:A narrow band BPF 4 extracts a frequency component whose space is expressed in 0, and a narrow band BPF 5 extracts a frequency component whose mark is expressed in 1 similarly. Output data from the BPFs 4, 5 are integrated respectively by integration circuits 6, 7, the integration values are compared by a comparator 8 and a discrimination circuit 9 is used to make demodulation based on the comparison difference. In order to improve the accuracy of demodulation of a noisy FSK signal, at first a noise signal component should be eliminated. The noise is eliminated by using the comparator 8 to take a difference between outputs of the circuits 6, 7. Thus, stable demodulation immune to noise is attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to transmission data "1" /
FSK (Fr, which is coded by assigning "0" information to two types of predetermined carrier frequencies corresponding thereto,
equency Shift Keying: A data demodulator that demodulates a signal modulated by the frequency shift keying method into a signal represented by the original mark / space (“1” / “0”),
For example, it is suitable for application to an automatic meter-reading terminal using a distribution line as a communication path.

[0002]

2. Description of the Related Art An FSK signal assigns _two frequencies f ₁ and f ₂ to "1" and "0" of transmission data, as shown in FIG. 8, and assigns a logical value "1" (mark) to the frequency. f
₁ is a kind of frequency modulation method in which a logical value "0" is assigned to a frequency f ₂ (where f ₁ ≠ f ₂ ) is represented by a modulated signal.

FIG. 9 shows an original mark / space ("1" / "0") of an FSK signal when such an FSK signal is used for transmission data of an automatic meter-reading terminal using a distribution line. This shows an FSK signal demodulating device for demodulating into a signal, for example, the one shown in Japanese Patent Laid-Open No. 3-85974.

The FSK signal demodulator shown in FIG.
The phase comparison circuit 1 for comparing the phase of the signal from the signal A _in and the signal from the voltage controlled oscillator circuit (VCO) 3, the low pass filter (L
PF) 2 and a voltage controlled oscillator circuit 3 whose oscillation frequency changes in proportion to the output voltage of the low pass filter 2, and the frequency of the input FSK signal A _in and the voltage controlled oscillator circuit 3
The demodulated signal A _out is obtained by configuring an analog PLL (phase locked loop) circuit in which feedback is performed so as to always keep the oscillation frequency of the same.

Next, the operation will be described. The phase comparison circuit 1 compares the phase difference between the input signal A _in modulated by the FSK method and the oscillation frequency of the voltage controlled oscillator circuit 3, and the high frequency component of the difference signal voltage corresponding to the phase difference is passed through the low pass circuit. The voltage control oscillator circuit 3 is removed at 2 and the voltage control oscillator circuit 3 is controlled. When the analog PLL circuit is locked (phases match), the output of the voltage controlled oscillator circuit 3 becomes a signal _in which the phase and frequency are synchronized with the input signal A _in , so the demodulated signal A _out To occur.

[0006]

The conventional FSK signal demodulator used in the automatic meter-reading terminal is configured as described above and uses the analog technique. Therefore, a large number of operational amplifiers for analog filters are required, the circuit configuration is complicated and the number of parts is increased, and in analog circuits, there are drawbacks such as the need for an adjustment function due to variations in parts accuracy, and the like. There was a problem that the analog circuit could not be changed easily.

The present invention has been made to solve the above problems, and is a general-purpose digital signal processor (D) for performing digital signal processing capable of high-speed product-sum calculation.
By performing digital signal processing for demodulating a frequency shift keying signal using (SP), the number of hardware parts is reduced, the manufacturing is easy, the circuit can be downsized, and the cost can be reduced. The purpose is to obtain a vessel.

[0008]

A data demodulator according to claim 1 of the present invention is data for demodulating a frequency shift keying signal by using a general-purpose digital signal processor that performs digital signal processing capable of high-speed product-sum calculation. In the demodulator, a pair of narrow bandpass filters for extracting the two carrier frequency components constituting the frequency shift keying signal and a pair of outputs of each of these filters for obtaining an integral value for a certain period of time. It is characterized in that it is provided with an integrating circuit, a comparator for obtaining a difference between integrated values of these integrating circuits, and a judging circuit for judging and outputting demodulated data depending on whether the value output from the comparator is positive or negative.

The data demodulator according to claim 2 is a data demodulator that demodulates a frequency shift keying signal using a general-purpose digital signal processor that performs digital signal processing capable of high-speed product sum calculation. A narrow band-pass filter that extracts two carrier frequency components that form a transmodulation signal, a pair of oscillators that oscillate a sine wave having the same frequency as the two carrier frequency components, an output of the band-pass filter, and the above A multiplier that multiplies the sine wave outputs generated by a pair of oscillators, a low-pass filter that removes high-frequency components from the output of this multiplier, and an output from the pair of oscillators based on the output of this low-pass filter. A frequency switching circuit that determines whether any of the sine wave frequencies is selected and outputs demodulated data is provided. It is an.

Further, the data demodulator according to claim 3 is
In a data demodulator that demodulates a frequency shift keying signal by using a general-purpose digital signal processor that performs digital signal processing capable of high-speed product-sum calculation, a narrow band that extracts two carrier frequency components that form the frequency shift keying signal. A band-pass bandpass filter, a zero-crossing counter that counts the interval between zero-crossing points of the output of this band-pass filter based on a clock signal, and a frequency determination circuit that determines and outputs demodulated data based on the output of this zero-crossing counter. A data demodulator comprising:

[0011]

In the data demodulator according to the first aspect of the present invention, the two carrier frequency components forming the frequency shift keying signal are extracted by the pair of band pass filters,
The pair of integrating circuits obtains the integrated value of each of these filter outputs for a certain period. Then, the comparator obtains the difference between the integrated values of these integrator circuits, and the decision circuit decides and outputs the demodulated data according to whether the value output from the comparator is positive or negative.

Further, in the data demodulator according to the second aspect, the two carrier frequency components forming the frequency shift keying signal are extracted by the band pass filter, and
A pair of oscillators oscillates a sine wave having the same frequency as the two carrier frequency components, and a multiplier multiplies the output of the band pass filter by the sine wave output of the pair of oscillators. Then, a low pass filter removes high frequency components from the output of the multiplier,
The frequency conversion circuit determines whether any of the frequencies of the sine waves output from the pair of oscillators is selected based on the output of the low pass filter, and outputs demodulated data.

Further, the data demodulator according to claim 3 is
The band-pass filter extracts two carrier frequency components forming the frequency shift keying signal, and the zero-crossing counter counts the interval between the zero-crossing points of the output of the band-pass filter based on the clock signal. Then, the frequency discrimination circuit determines and outputs the demodulated data based on the output of the zero-crossing counter.

[0014]

EXAMPLES Example 1. Embodiment 1 of the present invention will be described below with reference to FIG.
2 will be described. FIG. 1 shows F according to the first embodiment.
It is a block diagram which shows a SK signal demodulator. In FIG. 1, 4
Is a narrow band pass filter (BPF) for extracting a carrier frequency component forming an FSK signal represented by a space "0" from the input modulation signal, and 5 is a carrier frequency component represented by a mark "1". It is a narrow band pass filter (BPF) for extraction.

Reference numeral 6 is an integrating circuit for integrating the output of the bandpass filter 4 for a certain period of time, and reference numeral 7 is also the bandpass filter 5.
Is an integration circuit for integrating the output of the above for a certain period of time, 8 is a comparator that takes the difference between the values of the integration circuits 6 and 7, and 9 is a determination circuit. If the value of the comparator 8 is positive, it is demodulated as space "0" If so, the mark is demodulated as "1".

Next, the operation will be described with reference to the signal waveforms shown in FIGS. When demodulating the data, the other data adoption sections are compared without integrating the switching portion of the transmission data (see FIG. 2A). Figure 2
(C) and (d) are output data of the band pass filters 4 and 5 for the input modulated signal (FIG. 2 (b)).
(E) is data that the comparator 8 compares the integrated values of the output data of the band-pass filters 4 and 5 by the integration circuits 6 and 7 by the comparator 8 and demodulates it by the determination circuit 9 based on the comparison difference.

Further, in FIG. 3, (a) is an FSK signal buried in noise, and since this FSK signal is demodulated,
In order to improve the accuracy, first, the noise signal must be removed, and in the case of white noise, it is uniform in all frequency bands. Therefore, as shown in FIGS. It is considered that there is noise in the output of 5. Therefore, the difference between the outputs of the integrating circuits 6 and 7 is calculated by the comparator 8
According to the above, noise can be removed (see FIGS. 3D to 3F), and as a result, demodulation that is strong against noise and always stable can be performed.

Therefore, according to the first embodiment, by using the general-purpose DSP, the operational amplifier for constructing the analog filter is not required, the circuit configuration can be simplified, the adjusting function is not required, and the cost can be reduced. . In addition, the characteristics of the filter can be easily changed simply by changing the filter coefficient, and digital signal processing is performed using a general-purpose DSP that can perform high-speed product-sum operation on FSK demodulated signals in automatic meter-reading terminals that use distribution lines. Is suitable for performing.

Example 2. In the first embodiment, two types of band pass filters 4 and 5 for extracting two carrier frequency components forming the FSK signal are provided, and demodulated data is extracted by comparing the integrated values of the outputs of the filters 4 and 5. Having shown the FSK signal demodulator, a second embodiment using a DPLL (digital PLL) circuit will be described next with reference to FIGS. 4 and 5.

FIG. 4 is a block diagram of an FSK signal demodulator according to the second embodiment of the present invention. In FIG. 4, 10 is FSK
A narrow band pass filter (BPF) for extracting two carrier frequency components that make up a signal, 11 is a low pass filter (LPF) that removes high frequency components, and 12 is an FSK signal represented by a space "0". An oscillator that outputs the same oscillation frequency as the carrier frequency component f ₀ constituting
13 is the carrier frequency component f ₁ represented by the mark “1”
An oscillator that outputs the same oscillation frequency as the above, 14 is a frequency switching circuit that alternately switches the frequencies, and 15 is a multiplier.

Next, the operation will be described. The demodulation operation includes the output of the band pass filter 10 and the two internal oscillators 1.
By multiplying the sine waves generated by 2 and 13 by using the multiplier 15 under the control of the feedback system, when the frequency component of the low-pass filter 11 to which the output of the multiplier 15 is input disappears, the frequency switching circuit 14 determines which internal oscillator is selected and generates a demodulated signal.

This utilizes the property that the frequency component disappears when the same frequency is multiplied by the multiplier 15 and the high frequency component is removed by the low pass filter 11. For example, assuming that the input signal is the carrier frequency component f ₁ forming the FSK signal, the frequency switching circuit 14
First selects the oscillator 12 that generates the frequency component f ₀ , and the multiplier 15 performs multiplication processing.

However, since there is a frequency component, the frequency switching circuit 14 switches from the oscillator 12 to the oscillator 13 which generates the frequency component f ₁ and performs the multiplication process. Since its output does not include a frequency component due to the above properties, the oscillator 13 selected by the frequency switching circuit 14 is viewed and the demodulation signal "1" is output. That is, the frequency switching circuit 14 causes the oscillator 12 to
When is selected, the demodulated signal “0” is obtained and the oscillator 13
When is selected, the demodulated signal "1" is obtained.

Next, the operation will be described with reference to the signal waveform diagram shown in FIG. When demodulating data, the values of other data adoption sections are compared without integrating the switching portion of the transmission data shown in FIG. 5B shows the input modulation signal, and FIG. 5C shows the output signal of the low-pass filter 11. Here, the frequency switching circuit 14 always operates so as to have no frequency component of the output signal of the low-pass filter 11. The frequency switching circuit 14 includes the oscillator 12
5D, "0" is obtained as the demodulated data, and "1" is obtained as the demodulated data when the oscillator 13 is selected, as shown in FIG.

Therefore, according to the second embodiment, as in the first embodiment, the use of the general-purpose DSP eliminates the need for an operational amplifier for forming an analog filter, simplifies the circuit structure, and adjusts the function. Is unnecessary,
Cost reduction can be achieved. Further, there is an effect that the characteristics of the filter and the frequency characteristics of the frequency shift keying signal can be easily changed only by changing the filter coefficient and the oscillation frequency of the oscillator.

Example 3. Next, a third embodiment of the present invention will be described. FIG. 6 is a configuration diagram of an FSK signal demodulator according to the third embodiment, and the third embodiment is an embodiment using a zero crossing point. In FIG. 6, reference numeral 16 is a narrow band pass filter (BPF) for extracting two carrier frequency components constituting the FSK signal, and 17 is a digital signal processor (DSP) for determining the interval between zero crossings of the output of the band pass filter 16. ) A zero-crossing counter that counts with a clock output from the inside, 18 has two kinds of count thresholds, and outputs "0" when the count value is within a certain threshold,
It is a frequency discriminating circuit that outputs "1" when it is within another threshold.

Next, description will be made with reference to the waveform chart shown in FIG. When demodulating data, the transmission data (Fig. 7 (a)
The values of other data adoption sections are compared without integrating the switching part of (see). The interval from the zero-crossing point to the zero-crossing point of the modulation signal shown in FIG. 7B is counted by the zero-crossing counter 17 by using the clock output from the inside of the DSP. Then, when the frequency discriminating circuit 29 determines that the count value is within a certain threshold value, “0” is output as demodulation data as shown in FIG. 7C, and it is determined that the count value is within another threshold value. At this time, "1" is output as demodulation data.

Therefore, according to the third embodiment, by utilizing the zero crossing point, the operational amplifier for constructing the analog filter by using the general-purpose DSP becomes unnecessary as in the first and second embodiments. The circuit configuration can be simplified, and the adjustment function is not required, so that the cost can be reduced. Further, there is an effect that the characteristics of the filter can be easily changed simply by changing the filter coefficient.

[0029]

As described above, according to the first aspect of the present invention, a pair of narrow band pass filters for extracting two carrier frequency components constituting the frequency shift keying signal, and these filters. A pair of integrator circuits that obtain the integrated value of each output of a certain period, a comparator that obtains the difference between the integrated values of these integrator circuits, and the demodulated data that is determined and output according to whether the value output from this comparator is positive or negative. Since the demodulator that demodulates data is configured by including the judgment circuit, a demodulator that does not use an analog filter and has stable parts and high accuracy with no variations in parts accuracy can be realized, and the number of parts of the hardware is reduced. It is easy to manufacture, the circuit can be downsized, and the cost can be reduced. Further, there is an effect that the characteristics of the filter can be easily changed only by changing the filter coefficient.

According to a second aspect of the present invention, a narrow band pass filter for extracting two carrier frequency components forming the frequency shift keying signal and a sine wave having the same frequency as the two carrier frequency components are oscillated. A pair of oscillators,
A multiplier that multiplies the output of the band pass filter and the sine wave output generated from the pair of oscillators, and a low pass filter that removes high frequency components from the output of the multiplier,
Based on the output of the low-pass filter, a frequency switching circuit that determines which of the frequencies of the sine wave output from the pair of oscillators is selected and outputs demodulated data is provided, and the data is demodulated. Since the demodulator that complies with the present invention is configured, the analog filter is not used, a stable and highly accurate demodulator can be realized without variations in component accuracy, and the number of hardware parts is reduced, which is similar to the first aspect. The circuit can be easily reduced, and the cost can be reduced. Further, there is an effect that the filter characteristic and the frequency characteristic of the shift keying signal can be easily changed by changing the filter coefficient and the oscillation frequency.

According to a third aspect of the present invention, a narrow band pass filter for extracting two carrier frequency components constituting the frequency shift keying signal and an interval between zero crossing points of outputs of the band pass filter are clocked. The demodulator for demodulating data is configured by including a zero-crossing counter that counts based on a signal and a frequency discriminating circuit that determines and outputs demodulated data based on the output of the zero-crossing counter. As in 2, the analog filter is not used, and a stable and highly accurate demodulator with no variations in component accuracy can be realized, the number of hardware parts is reduced, the manufacturing is easy, the circuit can be downsized, and the cost can be reduced. It can be reduced. Further, there is an effect that the filter characteristic can be easily changed by changing the filter coefficient.

[Brief description of drawings]

FIG. 1 is a block diagram showing an FSK signal demodulator using two types of bandpass filters according to a first embodiment of the present invention.

FIG. 2 is an output waveform diagram of each part of FIG.

FIG. 3 is an output waveform diagram of each part for explaining the noise removal effect of FIG.

FIG. 4 is a block diagram showing an FSK signal demodulator using two types of oscillators according to the second embodiment of the present invention.

5 is an output waveform diagram of each part of FIG.

FIG. 6 is a block diagram showing an FSK signal demodulator using a zero-crossing method according to a third embodiment of the present invention.

FIG. 7 is an output waveform diagram of each part of FIG.

FIG. 8 is a waveform diagram illustrating an FSK modulation method according to the present invention.

FIG. 9 is a block diagram showing a conventional FSK signal demodulator.

[Explanation of symbols]

 4 band pass filter (BPF) 5 band pass filter (BPF) 6 integrating circuit 7 integrating circuit 8 comparator 9 determination circuit 10 band pass filter (BPF) 11 low pass filter (LPF) 12 oscillator 13 oscillator 14 frequency switching circuit 16 band Pass filter (BPF) 17 Zero-crossing counter 18 Frequency discrimination circuit

Claims (3)

[Claims] 1. A data demodulator that demodulates a frequency shift keying signal by using a general-purpose digital signal processor that performs digital signal processing capable of high-speed multiply-accumulate operation, and two carrier frequencies that constitute the frequency shift keying signal. A pair of narrow bandpass filters for extracting the components,
A pair of integrator circuits that obtain the integrated value of each output of these filters for a certain period of time, a comparator that obtains the difference between the integrated values of these integrator circuits, and the demodulated data is determined according to the sign of the value output from this comparator. A data demodulator, comprising: a determination circuit for outputting. 2. A data demodulator that demodulates a frequency shift keying signal by using a general-purpose digital signal processor that performs digital signal processing capable of high-speed product-sum calculation, and two carrier frequencies that constitute the frequency shift keying signal. A narrow band pass filter for extracting components, a pair of oscillators that oscillate a sine wave having the same frequency as the two carrier frequency components, an output of the band pass filter, and a sine wave output generated from the pair of oscillators. A multiplier to be multiplied, a low-pass filter that removes high-frequency components from the output of this multiplier, and one of the frequencies of the sine waves output from the pair of oscillators is selected based on the output of this low-pass filter. And a frequency switching circuit for determining whether or not the data is output and outputting the demodulated data. 3. A data demodulator that demodulates a frequency shift keying signal using a general-purpose digital signal processor that performs digital signal processing capable of high-speed multiply-accumulate operation, and two carrier frequencies that constitute the frequency shift keying signal. A narrow band-pass filter that extracts the component, a zero-crossing counter that counts the interval of the zero-crossing points of the output of this band-pass filter based on the clock signal, and a demodulated data judgment output based on the output of this zero-crossing counter And a frequency discriminating circuit for performing the data demodulation.