JPH06224424A - Mos transistor and manufacture thereof - Google Patents

Abstract

(57) [Summary] [Object] The present invention aims to extend the effective channel length to eliminate the influence of the short channel effect, and to reduce the junction leak in the source / drain regions. Further, in a high voltage MOS transistor, the occurrence of punch through is reduced. [Structure] As an example, after forming a LOCOS oxide film (not shown) on the semiconductor substrate 11 by the LOCOS method,
By removing it, a groove 12 is formed on the upper layer of the semiconductor substrate 11,
The gate electrode 14 is formed on the semiconductor substrate 11 including the inner wall of 12 with the gate insulating film 13 interposed therebetween, and the source / drain regions 17 and 18 are formed in the upper layer of the semiconductor substrate 11 on both sides thereof. A channel forming region 19 having a concentration higher than that of the semiconductor substrate 11 is provided between the regions 18. Although not shown, first and second gate electrodes are formed in parallel on the semiconductor substrate via a gate insulating film, and an impurity diffusion region having a concentration higher than that of the semiconductor substrate is formed in the semiconductor substrate below the electrodes. Is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS transistor and its manufacturing method.

[0002]

2. Description of the Related Art As semiconductor devices have become smaller and smaller, M
The influence of the short channel effect of the OS transistor is increasing. As a countermeasure, M having a structure as shown in FIG.
An OS transistor 80 has been proposed. That is, the gate electrode 83 is formed on the substrate 81 via the gate insulating film 82. Source / drain regions 86 and 87 are formed in the upper layer of the semiconductor substrate 81 on both sides of the gate electrode 83 via LDD diffusion layers 84 and 85. Further, a diffusion layer region 88 having an impurity concentration higher than that of the semiconductor substrate 81 is formed so as to cover the LDD diffusion layer 85 acting as a drain and the source / drain region 87 from the semiconductor substrate 81 side.

Although not shown, a high breakdown voltage transistor used in a non-volatile memory device uses a gate electrode having a long gate length in order to withstand a high breakdown voltage. Alternatively, the drain region may have a so-called offset structure.

[0004]

Problems to be Solved by the Invention
In the OS transistor, the junction leak of the source / drain region increases, and the breakdown voltage of the source / drain region (particularly the source / drain region that acts as the drain region) decreases. Further, it is difficult to form a diffusion layer region having a high impurity concentration.

In the high breakdown voltage transistor, a MOS transistor having a long gate length or a MOS transistor having an offset structure has a large formation area. Therefore, high integration is hindered. If the gate length and the offset length are shortened to reduce the formation area, punch through occurs.

An object of the present invention is to provide a MOS transistor which is not easily affected by the short channel effect and which is excellent in high integration, or a MOS transistor which has a high breakdown voltage and which is unlikely to cause punch through.

[0007]

SUMMARY OF THE INVENTION The present invention is a MOS transistor and a method for manufacturing the same made to achieve the above object. That is, as the first MOS transistor, the gate insulating film is formed on the inner wall of the groove formed in the semiconductor substrate and the upper surface of the semiconductor substrate on both sides of the inner wall. A gate electrode is formed on the upper surface of the gate insulating film,
Source / drain regions are formed in the upper layer of the semiconductor substrate on both sides of the gate electrode. Further, in the upper layer of the semiconductor substrate below the gate electrode, a channel formation region having a concentration higher than the impurity concentration of the semiconductor substrate is formed.

In the first method of manufacturing the MOS transistor, in the first step, a groove is formed in the upper layer of the semiconductor substrate, and a gate insulating film is formed on the inner wall of the groove and the upper surface of the semiconductor substrate on both sides of the groove. Then, in a second step, a gate electrode is formed on the upper surface of the gate insulating film. Subsequently, in a third step, source / drain regions are formed on the semiconductor substrate on both sides of the gate electrode. Then, in a fourth step, a channel formation region in which an impurity having a higher concentration than that of the semiconductor substrate is diffused is formed in the upper layer of the semiconductor substrate below the gate electrode. Alternatively, in the first step, a LOCOS oxide film is formed on the upper layer of the semiconductor substrate by the LOCOS method, and then the LOCOS film is formed.
A groove is formed in the upper layer of the semiconductor substrate by removing the S oxide film, and then the second and subsequent steps are performed.

As the structure of the second MOS transistor, a first gate electrode and a second gate electrode are formed in parallel on the upper surface of a semiconductor substrate with a gate insulating film interposed therebetween. A first source / drain region is provided in an upper layer of the semiconductor substrate opposite to the second gate electrode side with respect to the first gate electrode, and the first source / drain region is provided with respect to the second gate electrode.
The second layer on the upper layer of the semiconductor substrate opposite to the gate electrode side of
Source / drain regions are provided. Furthermore, an impurity diffusion region having a higher concentration than the impurity concentration of the semiconductor substrate is formed in the semiconductor substrate below the first and second gate electrodes.

As a method of manufacturing the second MOS transistor, in the first step, a gate insulating film and an electrode forming film are formed on the upper surface of the semiconductor substrate. Then in the second step,
After forming an etching mask on the electrode formation film and forming an opening for ion implantation in the electrode formation film, by ion implantation using the electrode formation film as an ion implantation mask, the concentration is higher than the impurity concentration of the semiconductor substrate. An impurity diffusion region is formed in the semiconductor substrate. Then, in a third step, the first and second gate electrodes are formed by the electrode forming films on both sides of the impurity diffusion region. Then, in a fourth step, the first source / drain regions are formed in the upper layer of the semiconductor substrate on the side opposite to the second gate electrode side with respect to the first gate electrode, and the second gate electrode is formed. A second source / drain region is formed in the upper layer of the semiconductor substrate on the side opposite to the first gate electrode side.

[0011]

In the structure of the first MOS transistor described above, since the gate electrode is formed in the groove formed in the semiconductor substrate via the gate insulating film, the channel formation region becomes long. That is, since the gate length becomes long, the short channel effect is alleviated. Further, since it is not necessary to form a region having a higher impurity concentration than the semiconductor substrate in the semiconductor substrate around the source / drain region, no junction leak occurs in the source / drain region. Further, since the impurity concentration of the semiconductor substrate below the gate electrode is increased, punch-through hardly occurs, so that the breakdown voltage can be increased.

In the first MOS transistor manufacturing method described above, the LOCOS method for forming the element isolation region can form the LOCOS oxide film for forming the groove, so that the groove is formed in particular. Just L
There is no need to perform OCOS oxidation. The semiconductor substrate and LO
Impurities in the semiconductor substrate are deposited at the interface with the COS oxide film. Therefore, when the source / drain regions are formed, the deposited impurities are re-diffused into the upper layer of the semiconductor substrate to have a higher concentration than the semiconductor substrate. A channel forming region is formed. Therefore, it is not necessary to increase the number of steps to form the high-concentration channel formation region.

In the structure of the second MOS transistor described above, the impurity diffusion layer having a higher concentration than the impurity concentration of the semiconductor substrate is formed in the semiconductor substrate between the first and second gate electrodes. Punch through between the channel forming regions formed on both sides of the diffusion region can be prevented.

In the second method for manufacturing a MOS transistor described above, conductive impurities are introduced into the semiconductor substrate through the opening provided in the electrode forming film to form an impurity diffusion region, and the opening is utilized to make a first The first and second gate electrodes are divided.
Therefore, the impurity diffusion region is formed in self-alignment with the first and second gate electrodes only by adding the ion implantation process.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the first invention will be described with reference to the schematic sectional view of the first embodiment shown in FIG. In the figure, a MOS transistor 1 having an LDD structure is shown as an example. As shown in the figure, a groove 12 is formed in the semiconductor substrate 11. The groove 12 is formed by removing a LOCOS oxide film (not shown in FIG. 1) formed by the LOCOS method, for example. A gate insulating film 13 is formed on the inner wall of the groove 12 and on the upper surface of the semiconductor substrate 11 on both sides of the inner wall. A gate electrode 14 is formed on the upper surface of the gate insulating film 13. LDD diffusion layers 15 and 1 are formed on the semiconductor substrate 11 on both sides of the gate electrode 14.
Source / drain regions 17 and 18 are formed through the line 6. In the upper layer of the semiconductor substrate 11 below the gate electrode 14, a channel forming region 19 having a concentration higher than that of the semiconductor substrate 11 is formed. The MOS transistor 1 is configured as described above.

In the first MOS transistor 1 described above, a groove 12 is provided in the semiconductor substrate 11, and the semiconductor is formed on the upper layer of the semiconductor substrate 11 below the gate electrode 14 formed in the groove 12 via the gate insulating film 13. By forming the channel forming region 19 having a higher concentration than the impurity concentration of the substrate 11, the channel forming region 19 becomes longer. That is, since the gate length becomes long, the short channel effect is alleviated. Further, in the semiconductor substrate 11 around the source / drain regions 17 and 18, a region having a higher impurity concentration than the semiconductor substrate 11 is not formed, so that no junction leak occurs in the source / drain regions 17 and 18.

Next, a method of manufacturing the MOS transistor 1 will be described with reference to the manufacturing process diagram of the first embodiment shown in FIG. In the figure, an LDD structure is shown as an example.
As shown in (1) of FIG. 2, in the first step, for example, p
A groove 12 is formed in an upper layer of a semiconductor substrate 11 made of a single crystal silicon substrate having a rectangular shape. As the forming method, for example,
The LOC is formed on the upper layer of the semiconductor substrate 11 by the LOCOS method.
The OS oxide film 21 is formed. This LOCOS oxide film 21
(A portion indicated by a two-dot chain line) is formed. At the same time, L
An element isolation region 22 made of an OCOS oxide film is formed.

Then, by the photolithography technique,
The etching mask 23 that covers the element isolation region 22 is formed of, for example, a resist. Then by etching, 2
The LOCOS oxide film 21 shown by the dotted line is removed. Thus, the groove 12 is formed in the upper layer of the semiconductor substrate 11.

During the LOCOS oxidation, the semiconductor substrate 11 is formed on the interface between the LOCOS oxide film 21 and the semiconductor substrate 11.
Impurities (for example, boron) diffused therein are deposited (not shown). After that, a silicon nitride film (not shown) used as an antioxidant film when performing the LOCOS method,
The silicon oxide film (not shown) formed to relieve the stress generated during the LOCOS oxidation is removed.

Then, the second step shown in FIG. 2B is performed. In this step, for example, by chemical vapor deposition,
A gate insulating film 13 is formed on the inner wall of the groove 12 and the upper surface of the semiconductor substrate 11 on both sides of the inner wall. The gate insulating film 13 may be formed by, for example, a thermal oxidation method.

Subsequently, the third step shown in FIG. 2C is performed. In this step, for example, by chemical vapor deposition,
An electrode forming film 24 is formed on the upper surface of the gate insulating film 13.
Then, the portion shown by the chain double-dashed line of the electrode forming film 24 is removed by the photolithography technique and etching, and the gate electrode 14 is formed by the remaining electrode forming film (24).

Further, a fourth step shown in FIG. 2 (4) is performed. In this step, L is formed on the upper layer of the semiconductor substrate 11 on both sides of the gate electrode 14 by, for example, an ion implantation method.
For example, an n-type impurity (not shown) for forming the DD diffusion layer is introduced. Next, a side wall forming film 25 is formed by chemical vapor deposition so as to cover the gate electrode 14. Subsequently, by etching back, the portion indicated by the chain double-dashed line of the side wall forming film 25 is removed, and the side walls 26 and 27 are formed by the remaining side wall forming film (25). Then, for example, an n-type impurity (not shown) for forming a source / drain region in the upper layer of the semiconductor substrate 11 by an ion implantation method using the gate electrode 14 and the sidewalls 26 and 27 as an ion implantation mask. To introduce.

After that, a fifth step shown in FIG. 2 (5) is performed. In this step, the LOC
Boron deposited at the interface between the OS oxide film (21) and the semiconductor substrate 11 is diffused to the upper layer of the semiconductor substrate 11 below the gate electrode 14 to form a channel formation region 19 having a higher concentration than the semiconductor substrate 11. To do. At this time, LD
The impurities introduced to form the D diffusion layer and the impurities introduced to form the source / drain regions are diffused to a predetermined position of the semiconductor substrate 11, and are diffused to the upper layer of the semiconductor substrate 11 on both sides of the gate electrode 14. , LDD diffusion layer 1
Source / drain regions 17 and 18 are formed via 5 and 16. The MOS transistor 1 is completed by the above manufacturing process.

In the first method of manufacturing a MOS transistor, the groove 12 is formed in the semiconductor substrate 11 by forming the LOCOS oxide film 21 and removing it, so that the element isolation region 22 is formed and the LOCOS is formed at the same time. It is possible to form the oxide film 21. Therefore, the LOCOS oxide film 21 can be formed without increasing the number of steps. Impurities (boron) in the semiconductor substrate 11 are formed at the interface between the semiconductor substrate 11 and the LOCOS oxide film 21.
When the source / drain regions 17 and 18 are formed, the deposited impurities are re-diffused into the upper layer of the semiconductor substrate 11 to form a high-concentration channel formation region 19. Therefore, the high concentration channel forming region 1
There is no need to increase the number of steps to form 9.

Next, an embodiment of the second invention will be described with reference to the schematic sectional view of the configuration of the second embodiment shown in FIG. In the figure,
An example of an LDD structure is shown. As shown in the figure,
A gate insulating film 32 is formed on the upper surface of the semiconductor substrate 31. A first gate electrode 33 and a second gate electrode 34 are formed in parallel on the upper surface of the gate insulating film 32. A first source / drain region 36 is formed on the upper layer of the semiconductor substrate 31 on the side opposite to the second gate electrode 34 side with respect to the first gate electrode 33, with a first LDD diffusion layer 35 interposed therebetween. Has been formed. Further, a second source / drain region 38 is formed in the upper layer of the semiconductor substrate 31 on the side opposite to the first gate electrode 33 side with respect to the second gate electrode 34, with a second LDD diffusion layer 37 interposed therebetween. Has been done. Moreover, in the semiconductor substrate 11 below the first and second gate electrodes 33 and 34, the impurity diffusion region 39 having a higher concentration than the impurity concentration of the semiconductor substrate 11 is formed.
Are formed.

An impurity diffusion layer 40 having the same conductivity type as the source / drain regions 36 and 38 may be formed in the upper layer of the semiconductor substrate 11 between the first and second gate electrodes 33 and 34. As described above, the MOS transistor 2
Is configured.

In the structure of the second MOS transistor, the impurity diffusion layer 39 having a concentration higher than that of the semiconductor substrate 11 is formed in the semiconductor substrate 11 between the first and second gate electrodes 33 and 34. By doing so, punch through can be prevented.

Next, a method of manufacturing the MOS transistor 2 will be described with reference to the manufacturing process diagram of the second embodiment shown in FIG. In the first step shown in (1) of FIG. 4, the gate insulating film 32 is formed on the upper surface of the semiconductor substrate 31 by a film forming technique such as a thermal oxidation method or a chemical vapor deposition method. Further, the electrode forming film 51 is formed on the upper surface of the gate insulating film 32 by, for example, a chemical vapor deposition method.

Then, a second step shown in FIG. 4B is performed. In this step, the opening 52 for ion implantation is formed at a predetermined position of the electrode forming film 51 by, for example, the photolithography technique and etching. To form the opening 52, first, an electrode forming film 51 is formed by a film forming technique.
A silicon oxide film 53 and a polycrystalline silicon film 54, for example, are formed on the upper surface of the. Then, the opening 55 is formed in the polycrystalline silicon film 54 by the usual photolithography technique and etching. After that, a side wall 56 made of polycrystalline silicon nitride is formed on the side wall of the polycrystalline silicon film 54 in which the opening 55 is formed by a film forming technique by a normal chemical vapor deposition method and an etch back process. Then, the opening 52 for ion implantation is formed in the silicon oxide film 53 and the electrode forming film 51 by etching using the polycrystalline silicon film 54 and the sidewalls 56 as an etching mask.

After that, an impurity diffusion region 39 having a concentration higher than that of the semiconductor substrate 11 is formed in the semiconductor substrate 11 by an ion implantation method using the electrode forming film 51 as an ion implantation mask. Then, the polycrystalline silicon film 54, the sidewalls 56, and the silicon oxide film 53 are removed by etching, for example.

Subsequently, the third step shown in FIG. 4C is performed. In this process, by photolithography technology,
While the opening 52 is filled, an etching mask 58 made of, for example, a resist is formed on the electrode forming film 51 on both sides of the opening 52. After that, the electrode formation film 51 in the portion indicated by the chain double-dashed line is removed by etching, and the remaining electrode formation film (51) forms the first and second gate electrodes 33, 34.

Thereafter, a fourth step shown in FIG. 4 (4) is performed. In this step, the first and second gate electrodes 33,
By an ion implantation method using 34 as an ion implantation mask,
A conductive impurity (not shown) for forming an LDD diffusion layer is introduced into the upper layer of the semiconductor substrate 11. Then, a silicon oxide film 59 is filled in between the first and second gate electrodes 33 and 34 by a film forming technique and an etchback process by a normal chemical vapor deposition method, and the first and second gate electrodes 33 and 34 are buried. A sidewall 60 is formed on the sidewalls of the gate electrodes 33 and 34.

Next, the first and second gate electrodes 33,
The first source / drain is formed on the upper layer of the semiconductor substrate 31 on the side opposite to the second gate electrode 34 side with respect to the first gate electrode 33 by the ion implantation method using the ion implantation masks 34 and the sidewalls 60. A conductive impurity (not shown) that forms a region is introduced, and a second source / drain is formed in the upper layer of the semiconductor substrate 31 on the side opposite to the first gate electrode 33 side with respect to the second gate electrode 34. A conductive impurity (not shown) for forming the region is introduced. After that, a diffusion process is performed to form L on the upper layer of the semiconductor substrate 31.
DD diffusion layers 35 and 37 and source / drain regions 36 and 3
8 is formed. The first and second gate electrodes 33, 3
Also in the upper layer of the semiconductor substrate 31 between the four layers, the diffusion layer region 6
1 is formed.

In the second method for manufacturing a MOS transistor, conductive impurities are introduced into the semiconductor substrate 31 through the opening 52 provided in the electrode forming film 51 to form the impurity diffusion region 39, and the opening 57 is used. Then, the first and second gate electrodes 33 and 34 are divided. For this reason, the impurity diffusion region 39 is formed with respect to the first and second gate electrodes 33 and 34.
It is formed in a self-aligned manner only by adding an ion implantation process.

[0035]

As described above, according to the invention of claim 1, since the gate electrode is formed in the groove formed in the semiconductor substrate via the gate insulating film, the channel forming region becomes long. That is, since the gate length becomes long, the short channel effect can be mitigated. Further, since it is not necessary to form a region having a higher impurity concentration than the semiconductor substrate in the semiconductor substrate around the source / drain region, no junction leak occurs in the source / drain region. Therefore, the reliability can be improved. Further, since the channel forming region having a high impurity concentration is formed in the upper layer of the semiconductor substrate below the gate electrode, punch through hardly occurs. Therefore, the breakdown voltage can be increased.

According to the invention of claim 2 or claim 3,
By the LOCOS method for forming the element isolation region,
Since the LOCOS oxide film for forming the groove can be formed, it is not necessary to perform the LOCOS oxidation only for forming the groove. Therefore, the groove can be easily formed. Further, impurities in the semiconductor substrate are deposited at the interface between the semiconductor substrate and the LOCOS oxide film. Therefore, when the source / drain regions are formed, the deposited impurities are re-diffused into the upper layer of the semiconductor substrate, so that the semiconductor substrate A channel forming region having a higher concentration than that of the above can be formed. Therefore, a high-concentration channel formation region can be easily formed without increasing the number of steps.

According to the fourth aspect of the invention, since the impurity diffusion layer having a higher concentration than the impurity concentration of the semiconductor substrate is formed in the semiconductor substrate between the first and second gate electrodes, the impurity diffusion region concerned. Punch-through does not occur between the channel forming regions formed on both sides of the pin. As a result, it is not necessary to form a long gate length or a long offset region, so that the formation area of the MOS transistor can be reduced. Therefore, it is possible to achieve high integration without generating punch through.

According to the invention of claim 5, a conductive impurity is introduced into the semiconductor substrate through the opening provided in the electrode forming film,
Since the impurity diffusion region is formed and the first and second gate electrodes are divided by utilizing the opening, the impurity diffusion region can be formed by adding the ion implantation process to the first and second gate electrodes. Can be formed in a self-aligned manner. Therefore, it is possible to form the impurity diffusion region that prevents punch-through with a slight manufacturing burden.

[Brief description of drawings]

FIG. 1 is a schematic configuration sectional view of a first embodiment.

FIG. 2 is a manufacturing process diagram of the first embodiment.

FIG. 3 is a schematic configuration sectional view of a second embodiment.

FIG. 4 is a manufacturing process diagram of the second embodiment.

FIG. 5 is a schematic configuration sectional view of a conventional example.

[Explanation of symbols]

 1 MOS Transistor 2 MOS Transistor 11 Semiconductor Substrate 12 Groove 13 Gate Insulating Film 14 Gate Electrode 17 Source / Drain Region 18 Source / Drain Region 19 Channel Forming Region 21 LOCOS Oxide Film 31 Semiconductor Substrate 32 Gate Insulating Film 33 First Gate Electrode 34 Second gate electrode 36 First source / drain region 38 Second source / drain region 39 Impurity diffusion region 51 Electrode forming film 52 Opening

Claims (5)

[Claims] 1. An inner wall of a groove formed in a semiconductor substrate, a gate insulating film formed on the upper surface of the semiconductor substrate on both sides of the groove, a gate electrode formed on the upper surface of the gate insulating film, and both sides of the gate electrode. And a source / drain region formed in the upper layer of the semiconductor substrate, and a channel formation region having a higher concentration than the impurity concentration of the semiconductor substrate and formed in the upper layer of the semiconductor substrate below the gate electrode. A MOS transistor characterized in that 2. A first step of forming a groove in an upper layer of a semiconductor substrate, a second step of forming a gate insulating film on an inner wall of the groove and an upper surface of the semiconductor substrate on both sides of the inner wall of the groove, and the gate insulating film. A third step of forming a gate electrode on the upper surface of the semiconductor substrate, a fourth step of forming source / drain regions on the upper layer of the semiconductor substrate on both sides of the gate electrode, and an upper layer of the semiconductor substrate below the gate electrode. And a fifth step of forming a channel formation region by diffusing impurities into the semiconductor substrate at a concentration higher than the impurity concentration of the semiconductor substrate. 3. The method of manufacturing a MOS transistor according to claim 2, wherein in the first step, a LOCOS oxide film is formed on the upper layer of the semiconductor substrate by the LOCOS method, and then the LOCOS oxide film is removed, Form a groove in the upper layer of the semiconductor substrate,
After that, the method of manufacturing a MOS transistor is characterized in that the second and subsequent steps are performed. 4. A gate insulating film formed on the upper surface of a semiconductor substrate, a first gate electrode formed on the upper surface of the gate insulating film, and formed on the upper surface of the gate insulating film in parallel with the first gate electrode. A second gate electrode, a first source / drain region formed in an upper layer of the semiconductor substrate on the side opposite to the second gate electrode side with respect to the first gate electrode, and the second A second source / drain region formed in an upper layer of the semiconductor substrate opposite to the first gate electrode side with respect to the gate electrode, and having a concentration higher than an impurity concentration of the semiconductor substrate, A MOS transistor comprising an impurity diffusion region formed in the semiconductor substrate below the first and second gate electrodes. 5. A first step of forming a gate insulating film and an electrode forming film on an upper surface of a semiconductor substrate; and after forming an opening for ion implantation in the electrode forming film,
A second step of forming an impurity diffusion region having an impurity concentration higher than that of the semiconductor substrate in the semiconductor substrate by an ion implantation method using the electrode forming film as an ion implantation mask; A third step of forming first and second gate electrodes with the electrode forming films on both sides of the semiconductor substrate, and the semiconductor substrate on the side opposite to the second gate electrode side with respect to the first gate electrode. A first source / drain region on the upper layer, and a second source / drain region on the upper layer of the semiconductor substrate opposite to the first gate electrode side with respect to the second gate electrode. And a fourth step of forming the MOS transistor.