JPH06224376A - Cmos semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent latchup by forming a titanium silicide layer over regions in close proximity to source regions, drains, and a polysilicon gate electrode. CONSTITUTION:A p-conductivity type diffusion region 13 is formed at a region in close proximity to a source region of a PMOS by ion implantation. An n- conductivity type diffusion region 14 is formed in close proximity to a source region of an NMOS by ion implantation. Titanium is deposited on the entire surface of a wafer by sputtering. Exposed silicon and titanium, on source regions 4 and 6, the diffusion regions 13 and 14 in close proximity to the source regions 4 and 6, drain regions 5 and 7 and the polysilicon gate electrode 9, react with each other by a heat treatment. As a result of this reaction, a titanium silicide layer 21 is formed over the source regions 4 and 9, the diffusion regions 13 and 14 in close proximity to the source regions 4 and 6, the drains 5 and 7 and the polysilicon gate electrode 9. A layer insulating film, a contact hole and lines are also formed on this assembly. Thus, it is possible to obtain a sufficient capacity to withstand latchup.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a complementary MOS semiconductor device and its manufacturing method.

[0002]

2. Description of the Related Art FIG. 9 shows, for example, JP-A-60-111145.
FIG. 7 is a cross-sectional view showing the structure of a conventional complementary MOS semiconductor device disclosed in Japanese Patent Publication No. 4 publication.

In FIG. 9, 102b is an N-type diffusion region which is a sixth semiconductor region provided on the semiconductor substrate 101 other than the N-type diffusion region 102 which is the first semiconductor region, and 10
4d is an N ⁺ type diffusion region provided in the N type diffusion region 102b, and 103d is a P ⁺ type diffusion region formed in the surface region of the semiconductor substrate 101 in contact with the N ⁺ type diffusion region 104d. 120 contacts the N-type diffusion region 102b,
This is an aluminum electrode provided so as to form the Schottky diode 114, the aluminum electrode 120 is also in contact with the fifth semiconductor region 104b, and the fifth semiconductor region 104b and the sixth semiconductor region 102b are connected to each other. Are connected. Reference numeral 121 is an aluminum electrode serving as a ground terminal provided in contact with the surfaces of the N ⁺ type diffusion region 104d and the P ⁺ type diffusion region 103d. The Schottky diode 114 directly connects the aluminum electrode 1 to the sixth semiconductor region 102b.
It is realized by forming 20. The sixth semiconductor region 102b has a low concentration so that the Schottky diode 114 can be formed.

Since the low impurity concentration region is grounded and the Schottky diode 114 between the low impurity concentration region and aluminum is inserted between the parasitic transistors, the parasitic transistors forming the parasitic thyristor almost do not operate, and the latch is performed. It has a structure that makes it difficult to raise.

Further, a CMOS type semiconductor device using a metal silicide widely is not limited to aluminum as a material, and is disclosed in Japanese Patent Laid-Open No. Sho 59-59.
-35465 publication.

FIG. 10 is a sectional view showing a CMOS type semiconductor device described in JP-A-59-35465.

In FIG. 10, 201 is a P ^- type semiconductor substrate, 202 is an N ^- type well, and 203 is a P-channel MOS.
P ⁺ type source region and drain region of transistor, 2
Reference numeral 04 denotes a P ⁺ type source region and a drain region of the N channel MOS transistor. It should be noted that the emitter injection efficiency is focused on so as not to reduce the integration degree.
In a normal CMOS device, the impurity concentration of the substrate or well is 10 ¹⁵ to 10 ¹⁶ / cm ³ , and the impurity concentration of the source and drain regions is 10 ²⁰ / cm ³ or more. Under these conditions, the emitter injection efficiency is 0.99 or higher,
A parasitic bipolar transistor having a current amplification factor of 200 or more has been generated.

The emitter injection efficiency depends on the base impurity concentration and the emitter impurity concentration. This emitter impurity concentration is lowered to lower the emitter injection efficiency and prevent the operation of the parasitic bipolar transistor. Therefore, the impurity concentration of the source and drain regions of the MOS element that functions as an emitter is set to 10 ¹⁹ / cm ³ or less. This prevents latch-up.

Here, the latch-up mechanism will be described in detail.

FIG. 6 is a sectional view showing a conventional CMOS type transistor.

In FIG. 6, 1 is a P-conductivity type semiconductor substrate, 2 is an N-conductivity type diffusion region formed in the P-conductivity type semiconductor substrate 1, 3 is a field oxide film, and 4 and 5.
Are the source and drain of the PMOS formed in the N-conductivity type diffusion region 2 and are P-conductivity type diffusion regions, and have an impurity concentration of 10 ¹⁹ / cm ³ or less. 6
Sources and drains 7 and 7 of the NMOS are N conductivity type diffusion regions, and have an impurity concentration of 10 ²⁰ / cm ³ or more. Reference numeral 8 is a gate oxide film, 9 is a gate electrode, 10 is a protective insulating film, 11 is a power supply, and 11 'is a drain power supply.

The CMOS type transistor having the drain diffusion layer having the impurity concentration as described above has a problem due to latch-up due to miniaturization of the element.

FIG. 7 is a sectional view of a CMOS type transistor using an N well. In the figure, a bipolar transistor Q parasitic in CMOS is shown. The subscripts v and l indicate that the transistors are parasitic in the vertical and horizontal directions, respectively. FIG. 8 is an equivalent circuit diagram of a latch-up structure composed of parasitic bipolar transistors, where R _n and R _p are spreading resistances of the N well and P substrate, respectively.

Consider a case where energy having a positive potential is applied as noise from the output terminal.
This energy becomes a trigger that causes latch-up. The process until latch-up is triggered is as follows.

(1) When the potential of the output terminal exceeds V _cc , Q _V1 is turned on and a current flows inside the P substrate, and R _p
A potential difference occurs at both ends of the.

(2) When the potential difference across R _p exceeds 0.6 V, Q ₁₂ turns on. As a result, current flows in the N well, causing a voltage drop across R _n .

(3) When the voltage across R _n exceeds 0.6 V, Q _V2 turns on. As a result, a current path is formed between _Vcc and GND.

(4) As a result, the voltage across R _n is 0.
Q ₁₂ is turned on is maintained at or over 6V, V
_A large current flows between _cc and GND. Latch-up occurs at this time.

In addition to the above mechanism, there is an internal latch-up that may occur when a switching operation is performed at a high voltage. This is because carriers having a polarity opposite to that of channel carriers are generated due to a high electric field near the drain of the MOS transistor. Among the electron-hole pairs (impact ionization), holes flow through the well to the source side, and this current triggers latch-up.

[0020]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
As described above, the conventional CMOS semiconductor device disclosed in Japanese Patent Publication 54 has a Schottky diode formed of aluminum. Aluminum has a Schottky barrier height of N-type or P-type silicon. However, they are extremely unbalanced with 0.70 eV and 0.42 eV, respectively, and the Schottky barrier for an N-type semiconductor is sufficiently high, but when applied to a P-channel MOS transistor,
There was a problem that a sufficient effect cannot be expected.

Further, in the CMOS type semiconductor device described in JP-A-59-35465, the impurity concentration of the source and drain regions is set to 10 ¹⁹ / cm ³ or less, and injected carriers are There was a problem that there was almost no clamping effect.

The present invention has been made in order to solve the above problems, and is a P channel type MOS, N
An object of the present invention is to provide a CMOS type semiconductor device having sufficient resistance to latch-up in both channel type MOS.

[0023]

The present invention has been made in view of the above circumstances, and a CMOS type semiconductor device according to the present invention is a semiconductor substrate of a first conductivity type and a semiconductor substrate of a first conductivity type. A first semiconductor region of a second conductivity type provided above, a second semiconductor region of a first conductivity type provided in the first semiconductor region of a second conductivity type, and a first semiconductor region on a semiconductor substrate. Second semiconductor region of the second conductivity type provided outside the semiconductor region and a fourth semiconductor region of the second conductivity type provided outside the source region in the second semiconductor region in proximity to the third semiconductor region or the third semiconductor region.
A fifth semiconductor region of the first conductivity type provided outside the source region in the semiconductor region of the second semiconductor region, at least on the second semiconductor region and the fourth semiconductor region, or on the third semiconductor region and the fifth semiconductor region. A first layer made of a refractory metal or a refractory metal silicide, which is connected to the semiconductor region while forming a Schottky diode.

Further, the present invention is characterized by including a gate electrode and a second layer made of refractory metal or refractory metal silicide on the gate electrode.

Further, in the method of manufacturing a CMOS type semiconductor device according to the present invention, a step of forming a first conductivity type first semiconductor region on a first conductivity type semiconductor substrate, and a step of forming an element isolation region and then forming a gate A step of forming an electrode, a step of forming a second semiconductor region of a first conductivity type in a first semiconductor region of a second conductivity type, and a step of forming a second conductivity type outside a first semiconductor region on a semiconductor substrate. Forming the third semiconductor region, forming a fourth semiconductor region of the second conductivity type on the outer side of the source region in the second semiconductor region in the vicinity of the source region, and forming a source in the third semiconductor region. Forming a fifth semiconductor region of the first conductivity type on the outer side in close proximity to the region, and on the gate electrode,
Forming a layer of refractory metal or refractory metal silicide on the second semiconductor region, the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region; and forming an interlayer insulating film. And a step of later forming a wiring pattern.

[0026]

According to the above-mentioned structure, the CMOS semiconductor device according to the present invention has at least the second semiconductor region and the fourth semiconductor region, or the third semiconductor region, by the layer made of refractory metal or refractory metal silicide. And a Schottky diode formed on the fifth semiconductor region while being connected,
Insert a Schottky diode in parallel with the source electrode,
The carriers injected by the Schottky diode are clamped to prevent latch-up.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

1 to 4 are views showing a method of manufacturing a semiconductor device according to the present invention, for example, a CMOS type transistor.

Phosphorus and boron are implanted into a P-conductivity type silicon substrate 1 as the first conductivity type to form an N well 2 and a P well 2 ', an element isolation oxide film 3 is formed, and a threshold value of a transistor is formed. After the adjustment ion implantation, the gate oxide film 8 and the polysilicon gate electrode 9 are formed (see FIG. 1). Then, after forming the sidewall 12, the source and drain regions 4, 5, 6, and 7 are formed by ion implantation. The source and drain regions 4, 5 of the PMOS
The average impurity concentration of 5 × 10 ¹⁹ / cm ³
Source and drain regions 7 and 6 have an average impurity concentration of 1 ×
It is 10 ²⁰ / cm ³ . The impurity concentration of the source / drain regions may be in a concentration range that forms a Schottky junction with the metal deposited on the source / drain regions.

After that, at a position close to the source region of the PMOS, 1 × 10 ¹⁶ / cm ³ of P-conductivity type diffusion region 1 is formed.
3 is formed by ion implantation, and N having an impurity concentration of 5 × 10 ¹⁶ / cm ³ is formed at a position close to the source region of the NMOS.
The conductivity type diffusion region 14 is formed by ion implantation. Then, titanium 22 is deposited on the entire surface of the wafer by the sputtering method (see FIG. 2). After depositing titanium, the silicon exposed on the source, the diffusion region near the source, the drain, and the polysilicon gate electrode is reacted with the titanium by heat treatment, and the titanium silicide layer 21 is brought into the region close to the source and the source. , Drain and polysilicon gate electrode (see FIG. 3). Then, an interlayer insulating film, contact holes, and wiring are formed (see FIG. 4).

Therefore, as shown in FIG. 5, holes generated by impact ionization in the vicinity of the drain 7 are easily transferred to the P-conductivity type diffusion region 13 provided in the vicinity of the source at a voltage lower than the built-in voltage of silicon. It pulls in holes and prevents latch-up.

In the CMOS type transistor thus formed, the diffusion regions 13 and 14 close to the source are formed.
And the effect of inserting a Schottky diode in parallel with the source electrode
It can be improved about 5 times or more as compared with the conventional CMOS type transistor. Further, since the titanium silicide layer is formed on the source / drain regions and the polysilicon gate electrode, the resistance of these regions can be significantly reduced.

In the above-mentioned embodiments, titanium is used as the metal forming the silicide layer, but the present invention is not limited to the kind of metal, and N is not limited thereto.
Any metal or silicide having substantially the same Schottky barrier for both P-type and N-type semiconductors such as i and Pt may be used.

Further, in the above-mentioned embodiment, the silicide layer is formed on the region close to the source region and the low concentration impurity diffusion layer, but the silicide layer may be formed on the substrate or the well.

[0035]

As described above, according to the present invention,
A layer of refractory metal or refractory metal silicide on at least the second semiconductor region and the fourth semiconductor region,
Alternatively, a Schottky diode is formed on and connected to the third semiconductor region and the fifth semiconductor region, a Schottky diode is inserted in parallel with the source electrode, and carriers injected by the Schottky diode are clamped. Therefore, it is possible to obtain a sufficient resistance against latch-up, to significantly reduce the sheet resistance of the source and drain regions, and to simultaneously form a low resistance silicide layer on the gate polysilicon.
The drive capability of the transistor can be significantly reduced to allow the device to operate at very high speeds.

[Brief description of drawings]

FIG. 1 is a diagram showing a method for manufacturing a CMOS transistor according to the present invention.

FIG. 2 is a diagram showing a method for manufacturing a CMOS transistor according to the present invention.

FIG. 3 is a diagram showing a method of manufacturing a CMOS transistor according to the present invention.

FIG. 4 is a diagram showing a method for manufacturing a CMOS transistor according to the present invention.

FIG. 5 is a diagram for explaining the operation of the present invention.

FIG. 6 is a cross-sectional view showing a conventional CMOS transistor.

FIG. 7 is a diagram for explaining a latch-up mechanism in a conventional CMOS transistor.

FIG. 8 is a circuit diagram showing an equivalent circuit of a latch-up structure in a conventional CMOS transistor.

FIG. 9 is a cross-sectional view showing a conventional CMOS transistor.

FIG. 10 is a cross-sectional view showing a conventional CMOS transistor.

[Explanation of symbols]

 1 semiconductor substrate 3 field oxide film 4 PMOS source 5 PMOS drain 6 NMOS source 7 NMOS drain 8 gate insulating film 9 gate electrode 10 protective insulating film 11 power supply 11 'drain power supply 12 sidewall 13 P conductive type diffusion region 14 Diffusion region of N conductivity type 15-18 Parasitic transistor 19, 20 Spreading resistance 21 Titanium silicide layer 22 Titanium

Claims (3)

[Claims] 1. A semiconductor substrate of the first conductivity type, a first semiconductor region of the second conductivity type provided on the semiconductor substrate of the first conductivity type, and a first semiconductor region of the second conductivity type in the semiconductor substrate. The second semiconductor region of the first conductivity type provided and the first semiconductor region on the semiconductor substrate.
A third semiconductor region of the second conductivity type provided outside the semiconductor region of the second conductivity type, and a second conductivity type of the second conductivity type provided outside the source region in the second semiconductor region. A first semiconductor provided on the outside of the source region in the fourth semiconductor region or the third semiconductor region.
A refractory metal that is connected to the conductive fifth semiconductor region and at least the second and fourth semiconductor regions or the third and fifth semiconductor regions while forming a Schottky diode. Or a first layer formed of a refractory metal silicide, and a CMOS semiconductor device. 2. A gate electrode, and a second layer made of refractory metal or refractory metal silicide on the gate electrode,
The CMOS semiconductor device according to claim 1, further comprising: 3. A method for manufacturing a CMOS type semiconductor device, comprising: forming a second conductive type first semiconductor region on a first conductive type semiconductor substrate; and forming a gate electrode after forming an element isolation region. A step of forming a second semiconductor region of the first conductivity type in the first semiconductor region of the second conductivity type, and a third conductivity type of the second semiconductor type outside the first semiconductor region on the semiconductor substrate.
Forming a semiconductor region of the second semiconductor region, and
A step of forming a fourth semiconductor region of conductivity type, and a step of forming a first semiconductor on the outer side of the third semiconductor region close to the source region.
Forming a conductive type fifth semiconductor region; and having a high melting point on the gate electrode, the second semiconductor region, the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region. A method of manufacturing a CMOS semiconductor device, comprising: a step of forming a layer made of metal or a refractory metal silicide; and a step of forming a wiring pattern after forming an interlayer insulating film.