JPH06224194A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To embody a wiring structure, wherein the lateral etching of an intermediate metallic layer is suppressed, and uncontaminated copper is exposed to the bottom part of a via hole, and further, both the execution of an optimum pretreatment for burying copper in the via hole by a selective chemical gas phase reaction and the process of the pretreatment are made possible. CONSTITUTION:A via hole 208 to whose bottom surface a first copper layer 204 of a first wiring layer is exposed is formed. The copper on the bottom surface of the via hole 208 is reduced by its heating in a hydrogen atmosphere, and subsequently, a third copper layer 211 of a second wiring layer is formed by a chemical vapor growth. Thereby, the burying of the via hole 208 is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device such as a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In silicon semiconductor integrated circuits, copper, which has a low electric resistance and migration resistance, has been attracting attention as a wiring material replacing aluminum.

The present inventors have already filed Japanese Patent Application No. 63-12400.
No. 6, Japanese Patent Application No. 63-326063, and Japanese Patent Application Laid-Open No. 2-256238 based on which they claim domestic priority, copper is selectively vaporized only on the metal using a silicon oxide film as a mask. We propose a technology to fill the contact holes and through holes by phase growth. The main point of this selective growth is to heat and evaporate a raw material made of an organic complex of copper or an organic metal, and send it to a reaction chamber together with hydrogen, and a first material made of metal or metal silicide and a second material made of oxide or nitride. The substrate having the above material on its surface is heated above the decomposition temperature of the raw material gas, and the evaporated raw material gas is supplied together with the reducing gas onto the heated substrate while keeping the temperature lower than the decomposition temperature. Are selectively grown only on the surface of the first material. In the base substrate having the metal film on the entire surface of the substrate, the copper film naturally grows on the entire surface of the substrate by the above-described chemical vapor deposition.

Further, Japanese Patent Application No. 2-56586 proposes a technique for increasing the deposition rate by adding steam or the like to a raw material, and Japanese Patent Application Laid-Open No. 4-67655 discloses a metal intermediate layer on the bottom surface of a via hole. By removing and exposing copper, and utilizing the fact that the natural oxide film on the copper surface is easily reduced by hydrogen in the reaction atmosphere, by filling the via hole by the selective growth method described above, low resistance can be obtained. A method for implementing via embedding is disclosed.

JP-A-4-242937 discloses that after an insulating film is opened, sputter etching is performed, and then an intermediate metal having a diffusion barrier property and adhesion to the insulating film and copper are continuously sputter deposited, and the sputter deposition is performed. Discloses a method of growing a copper film on the formed copper film by chemical vapor deposition and filling the opened holes in the insulating film.

In the method described above, when the copper is exposed at the bottom of the via, the intermediate metal layer above the copper is removed by wet etching with an aqueous solution containing potassium ferricyanide.

However, if an attempt is made to remove the intermediate metal layer at the bottom of the via by wet etching, lateral etching of the intermediate metal layer may occur, which may deteriorate the adhesion between the interlayer insulating film and copper.

On the other hand, by dry processing, it is possible to expose copper, but the surface of the copper is fluorinated by the fluorine gas contained in the etching gas, which makes it difficult to perform good copper CVD on the surface.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in view of these problems, and suppresses the lateral etching of the intermediate metal layer and exposes the contamination-free copper at the bottom of the via, thereby selectively etching copper. It is an object of the present invention to perform an optimum pretreatment for filling a via hole by a vapor phase reaction and to realize a wiring structure that enables the pretreatment process.

[0010]

In order to achieve the above object, the invention according to claim 1 uses copper as a main material of a wiring formed on a substrate and improves adhesion between an interlayer insulating film and copper. In the method of manufacturing a semiconductor device having a multilayer wiring structure including an intermediate metal layer, a first wiring layer having a laminated structure of a first intermediate metal layer, a first copper layer and a second intermediate metal layer, Forming an interlayer insulating film on the first wiring layer and a first metal layer on the interlayer insulating film, the first metal layer being made of the same element as the first and second intermediate metal layers;
Forming a via hole in the first metal layer, the interlayer insulating film, and the second intermediate metal layer to expose the surface of the first copper layer; and exposing the exposed surface of the first copper layer. On the other hand, a step of performing a plasma treatment containing chlorine at a temperature of 200 ° C. or higher to remove contamination on the surface, and the first metal layer and the first wall on the inner wall surface and the bottom surface of the via hole.
Depositing a second metal layer made of the same element as the metal layer by sputtering, and reducing the surface of the first copper layer exposed at the bottom surface of the via hole by heating in a hydrogen atmosphere, Successively to the copper reduction step, a step of growing a second copper layer on the exposed surface of the first copper layer by chemical vapor deposition to fill the via hole, and a step of sputtering the second copper layer Depositing a third copper layer on the layer, and successively depositing a third metal layer made of the same element as the first and second metal layers to form a second wiring layer. It is characterized by including.

According to a second aspect of the present invention, copper is used as a main material of wiring formed on a substrate, and a semiconductor having a multilayer wiring structure including an intermediate metal layer for improving adhesion between an interlayer insulating film and copper. A method for manufacturing a device, comprising: a first wiring layer having a laminated structure of a first intermediate metal layer, a first copper layer and a second intermediate metal layer; an interlayer insulating film on the first wiring layer; Forming a first metal layer on the insulating film, the first metal layer comprising the same element as the first and second intermediate metal layers, and the first metal layer, the interlayer insulating film, and the second intermediate layer. Forming a via hole in the metal layer to expose the surface of the first copper layer, and the same element as the first metal layer on the inner wall surface and the bottom surface of the first metal layer and the via hole Process for depositing the second metal layer by sputtering And a step of exposing the surface of the first copper layer on the bottom surface of the via hole, leaving only the inner wall surface of the via hole by anisotropic processing of the second metal layer by dry etching, and heating in a hydrogen atmosphere. The step of reducing the surface of the first copper layer exposed at the bottom surface of the via hole, and a second step on the exposed surface of the first copper layer by chemical vapor deposition subsequent to the step of reducing the copper. Growing a copper layer to fill the via hole, and depositing a third copper layer on the second copper layer by sputtering and successively forming the first and second copper layers.
And a step of forming a second wiring layer by depositing a third metal layer made of the same element as the first metal layer.

The invention according to claim 3 is the invention according to claim 1 or 2.
The method for manufacturing a semiconductor device as described above, further comprising a step of smoothing the surface of the second copper layer by bias sputtering in which copper sputter deposition and sputter etching compete with each other after the via hole filling step.

The invention according to claim 4 is the invention according to claims 1 to 3.
The method of manufacturing a semiconductor device according to any one of 1 to 3, wherein the main materials of the first, second and third metal layers are selected from the group consisting of tantalum, niobium and vanadium. .

[0014]

By using the present invention, it is possible to embed a via hole exhibiting electrically good characteristics and to process a copper wiring with good controllability.

[0015]

EXAMPLES The present invention will be described below with reference to examples.

As the deposition apparatus, a copper CVD apparatus similar to that shown in Japanese Patent Application No. 2-56586 was used.
FIG. 1 shows an outline of the device. The reaction chamber 101 has an exhaust hole 102.
Can be exhausted through an exhaust system (not shown). Substrate holder 10 for holding sample substrate 104 with leaf spring 105
3 is provided in the reaction chamber 101. The heater 106 is built in the substrate holder 103 and can heat the substrate 104 to a predetermined temperature. A raw material container 107 containing a raw material 108 made of an organic complex of copper or an organometallic compound is provided in the reaction chamber 10.
It is installed outside 1. In the reaction chamber 101, the gas injection plate 109 facing the substrate holder 103 is the pipe 1
It is connected to the raw material container 107 via 10 and the valve 111. The gas injection plate 109 is provided with a number of fine gas injection holes 112. The raw material container 107, the pipe 110 and the valve 111 can be heated to a predetermined temperature by the heater 113, while the gas injection plate 109 can be heated to a predetermined temperature by the built-in heater 114. Hydrogen as a reducing carrier gas is controlled by the mass flow controller 117, and water vapor is controlled by the mass flow controller 118 as necessary,
It is introduced into the raw material container 107 through the pipe 115 by the valves 119 and 111. Reference numeral 116 in the figure denotes an O-ring. The deposition reaction is performed by introducing the gas that has passed through the pipe 110 and the raw material gas heated and evaporated in the raw material container into the reaction chamber. That is, the raw material gas heated and vaporized in the raw material container 107 is injected from the gas injection port 112 together with hydrogen or with hydrogen and water vapor, and the substrate holder 103
It is supplied on the surface of the sample substrate 104 fixed on the substrate. The source gas decomposes on a specific material, such as aluminum, titanium, chromium, zirconium, tungsten, molybdenum, tantalum, vanadium, or their silicide, to grow copper, depending on the material of the surface of the sample substrate 104. Specific material, metal oxide such as silicon oxide,
It does not decompose on nitrides such as silicon nitride and titanium nitride, and therefore copper does not grow. This is due to the difference in the catalytic action of various materials for the reaction in which the raw material gas is reduced by the reducing gas and decomposed. Therefore, by selecting the material of the sample substrate surface, it is possible to grow copper on the entire surface of the sample, and by changing the material at a specific position on the sample surface to the material at another position, Copper can also be selectively grown. At that time, it is important to correctly determine the temperature of the gas injection port 112, that is, the temperature of the gas injection plate 109 and the temperature of the sample substrate 104. When the temperature of the gas injection port 112 is equal to or lower than the solidification precipitation temperature of the raw material, the evaporated raw material gas is solidified on the injection plate 109 and is not injected in a gaseous state. Therefore, at this temperature, copper growth does not occur regardless of the temperature of the sample substrate. When the temperature of the gas injection port 112 is equal to or higher than the decomposition temperature of the raw material gas, the raw material gas is decomposed and copper reaches the surface of the sample substrate in an atomic or molecular state. Therefore, regardless of the material of the surface of the sample substrate, Grows all over. The temperature of the gas injection port 112 is
Therefore, it must be higher than the solidification precipitation temperature of the raw material gas and lower than the decomposition temperature of the evaporated raw material gas. On the other hand, if the temperature of the sample substrate is lower than the decomposition temperature of the source gas on the specific material on which copper is to be selectively grown, the source gas supplied to the surface of the sample substrate will not be decomposed and therefore copper will not grow. . Decomposition of the source gas on the material on which the temperature of the gas injection port 112 is higher than the solidification precipitation temperature of the organic complex or the organic metal as the raw material and lower than the decomposition temperature, and the temperature of the sample substrate is on which copper should be selectively grown. Only when the temperature is equal to or higher than the temperature, copper can be selectively grown on a specific portion of the surface of the sample substrate. If the temperature of the sample substrate is too high, the crystal grains of the selectively grown copper become coarse and the surface thereof becomes rough, which is not preferable. As a starting material, for example, copper divalent β-, such as bishexafluoroacetylacetonato copper
A diketonato compound or a compound obtained by adding an electron-donating ligand such as trimethylvinylsilyl to copper monovalent hexafluoroacetylacetonate can be used.

[Embodiment 1] FIG. 2 shows an example in which the present invention is applied to embedding a multilayer wiring via. This example exemplifies multilayer wiring on a semiconductor substrate that has undergone a transistor manufacturing process.

First, as shown in FIG. 2A, an insulating film such as silicon oxide 202 is formed on a semiconductor substrate 201, and a first intermediate metal layer such as tantalum 203 and a first intermediate metal layer is formed on the insulating film 202. A first copper layer 204 and a second intermediate metal layer, for example, a first wiring layer made of tantalum 205 are continuously formed by sputtering and processed by reactive ion etching. Next, a silicon nitride film or a silicon oxide film is formed on the interlayer insulating film 2 by plasma CVD, for example.
Then, a first metal layer made of the same element as the first and second intermediate metal layers 203 and 205, here, tantalum 207 is deposited by sputtering on the interlayer insulating film 206.

Next, as shown in FIG. 2B, a fluorine-containing gas, for example, a mixed gas of CHF ₃ and oxygen is added to the first metal layer 207, the interlayer insulating film 206 and the second intermediate metal layer 205. The via hole 208 is opened by performing reactive ion etching using, and the first copper layer 204 is exposed. 200 for this exposed first copper layer 204
A plasma treatment containing chlorine is performed at a temperature of 0 ° C. or higher to remove contamination on the surface of the first copper layer 204.

Next, as shown in FIG. 2C, a second metal layer 209 and a second copper layer 210 made of the same element as the first metal layer 207 are formed on the first metal layer 207. Then, the side surface and the bottom surface of the via hole 208 are deposited by sputtering.

Next, as shown in FIG. 2 (d), in a chemical vapor deposition apparatus in a hydrogen atmosphere of 1000 Pa or more, 20
By heating at 0 ° C. or higher to reduce the copper on the bottom surface of the via hole and continuously form a third copper layer 211 by chemical vapor deposition,
The via hole 208 is embedded. Here, as standard processing conditions for embedding a via hole, when bishexafluoroacetylacetonato copper was used as a raw material, the raw material temperature was set to 90 ° C., and hydrogen was 100 cc / min.
Then, the raw material is introduced into the reaction chamber 101 together with 10 cc / min of water vapor, the pressure in the reaction chamber 101 is set to 2000 Pa, and copper is deposited at a substrate temperature of 390 ° C. When using trimethylvinylsilylhexafluoroacetylacetonato copper, the raw material temperature is set to 65 ° C., the raw material is introduced into the reaction chamber 101 together with 100 cc / min of hydrogen, the pressure of the reaction chamber 101 is 1000 Pa, and the substrate temperature is 250 ° C. accumulate. CV
The third copper film 211 formed by D has the advantage that it has good coverage in fine via holes, but on the other hand, since the deposition rate is slow, after filling the via holes, the fourth copper film 211 is further sputtered.
A third metal layer 213 made of the same element as the copper layer 212 and the first metal layer 207 is continuously deposited. afterwards,
As shown in FIG. 2E, an upper wiring layer having a predetermined pattern is formed by dry etching using a gas containing chlorine.

The adhesion of the formed multi-layer wiring was good, and the via filling had a low resistance.

[Embodiment 2] This embodiment is also an example applied to embedding vias in a multi-layer wiring as in Embodiment 1, and will be described with reference to FIG.

Among the steps shown in FIGS. 3A to 3B, the steps up to the step of opening the via hole to expose the copper are the same as those in the first embodiment, and therefore the description thereof will be omitted. The characteristic part of this embodiment lies in the steps after the above-mentioned via hole opening step.

That is, after depositing a second metal layer 301 made of the same element as the first metal layer 207 by sputtering, of the second metal layer 301,
Via hole 2 by anisotropic processing by dry etching
As shown in FIG. 3C, only the side wall portion of 08 is left, and the surface of the first copper layer 204 as the lower wiring is exposed again on the bottom surface of the via hole 208. Example 1
Similarly to the above, the exposed surface of the first copper layer 204 is 200 ° C.
By performing a plasma treatment containing chlorine at the above temperature, the contamination on the copper surface is removed.

Next, as shown in FIG. 3D, the via hole 20 is heated in a chemical vapor deposition apparatus in a hydrogen atmosphere.
Copper on the surface of the first copper layer 204 exposed from the bottom surface of the second copper layer 204 is continuously reduced by the chemical vapor deposition method.
By forming 02, the via hole 208 is embedded.

Then, as shown in FIG.
A third copper layer 3 by sputtering on the copper layer 302 of
03 is formed, and a third metal layer 304 made of the same element as the first metal layer 207 is continuously deposited. Then, a wiring pattern, which is an upper layer of a predetermined pattern, is formed by dry etching using a gas containing chlorine.

The adhesion of the formed multi-layer wiring was good, and the via filling had low resistance.

[Embodiment 3] This embodiment is also an example applied to embedding multi-layer wiring vias in the same manner as Embodiment 1, and will be described with reference to FIG.

In this embodiment, a substrate which has been processed up to the step shown in FIG. 2D in Embodiment 1 is used. As shown in FIG. 4A, the third copper layer 211 formed by chemical vapor deposition is applied to the third copper layer 211 of this substrate by bias sputtering in which copper sputter deposition and sputter etching compete with each other. The surface of 211 is smoothed. Then, as shown in FIG. 4B, the first metal layer 207 is formed.
After depositing a third metal layer 401 composed of the same element by sputtering as described above, an upper wiring layer having a predetermined pattern is formed by dry etching using a gas containing chlorine.

The adhesion of the formed multilayer wiring was good, and the via filling had a low resistance.

[Embodiment 4] In the present embodiment, in the step of forming the lower and upper wiring layers in the first or third embodiment, the anisotropic processing technique is used to form the sidewall of each wiring layer as shown in FIG. Also the intermediate metal layer or the silicon nitride film 5
01 is further included.

The adhesion of the formed multi-layer wiring was good, and the via filling was low in resistance.

In the above-mentioned Examples 1 to 4, the plasma treatment containing chlorine is used to remove the contamination on the copper surface of the wiring layer. The chlorine plasma treatment temperature is set with reference to FIG. be able to. FIG. 6 is a graph showing the equilibrium constants of solid phase and vapor phase of copper chloride based on JANAF data. From FIG. 6 it can be seen that it evaporates in the form of a trimer. Although there are some differences in the equipment shape and reaction conditions,
The surface can be cleaned at 200 ° C. or higher without depositing copper chloride on the surface. In fact, good results have been obtained with chlorine plasma treatment at 200 ° C.

In the present invention, chlorine plasma treatment can be performed with a mixed gas of silicon tetrachloride and nitrogen under a pressure of 3 to 5 Pa, a substrate temperature of 200 to 250 ° C., and an electric power of 100 to 200 W.

[0036]

As described above, according to the present invention,
It is possible to reliably form a copper multilayer wiring having a low resistance via-filled portion, and it is possible to bring about a significant technological and economical advance in an LSI production line.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view of a semiconductor device manufacturing apparatus used in the present invention.

FIG. 2 is a diagram for explaining embedding of multilayer wiring vias to which the present invention is applied.

FIG. 3 is a diagram illustrating embedding of a multilayer wiring via to which the present invention is applied.

FIG. 4 is a diagram for explaining embedding of multilayer wiring vias to which the present invention is applied.

FIG. 5 is a diagram for explaining embedding of multilayer wiring vias to which the present invention is applied.

FIG. 6 is a graph showing equilibrium constants of solid phase and vapor phase of copper chloride.

[Explanation of symbols]

 101 Reaction Chamber 102 Exhaust Hole 103 Substrate Holder 104 Substrate 105 Leaf Spring 106 Heater 107 Raw Material Container 108 Raw Material 109 Gas Injection Plate 110 Pipe 111 Valve 112 Gas Injection Port 113 Heater 114 Heater 115 Pipe 116 O-ring 117 Mass Flow Controller 118 Mass Flow Controller 119 Valve 201 semiconductor substrate 202 insulating film 203 first intermediate metal layer 204 first copper layer 205 second intermediate metal layer 206 interlayer insulating film 207 first metal layer 208 via hole 209 second metal layer 210 second copper layer 211 Third Copper Layer 212 Fourth Copper Layer 213 Third Metal Layer 301 Second Metal Layer 302 Second Copper Layer 303 Third Copper Layer 304 Third Metal Layer 401 Third Metal Layer 501 Nitriding Silicon film

Claims (4)

[Claims] 1. A method of manufacturing a semiconductor device having a multi-layer wiring structure, which uses copper as a main material of wiring formed on a substrate and includes an intermediate metal layer for improving adhesion between an interlayer insulating film and copper, A first wiring layer having a laminated structure of a first intermediate metal layer, a first copper layer, and a second intermediate metal layer; an interlayer insulating film on the first wiring layer; and an interlayer insulating film on the interlayer insulating film. Forming a first metal layer made of the same element as the first and second intermediate metal layers, and forming a via hole in the first metal layer, the interlayer insulating film, and the second intermediate metal layer. And exposing the surface of the first copper layer, and performing plasma treatment containing chlorine at a temperature of 200 ° C. or higher on the exposed surface of the first copper layer to remove contamination on the surface. And the first metal layer and the inner wall of the via hole And a second consisting of the same elements as the first metal layer on the bottom surface
The step of depositing the metal layer by sputtering, the step of reducing the surface of the first copper layer exposed at the bottom surface of the via hole by heating in a hydrogen atmosphere, and the step of reducing the chemical vapor in succession by the chemical reduction step. Growing a second copper layer on the exposed surface of the first copper layer by a phase growth method to fill the via hole; and depositing a third copper layer on the second copper layer by sputtering. And then continuously depositing a third metal layer made of the same element as the first and second metal layers to form a second wiring layer, thereby manufacturing a semiconductor device. Method. 2. A method of manufacturing a semiconductor device having a multi-layer wiring structure, which uses copper as a main material of wiring formed on a substrate and includes an intermediate metal layer for improving adhesion between an interlayer insulating film and copper, A first wiring layer having a laminated structure of a first intermediate metal layer, a first copper layer, and a second intermediate metal layer; an interlayer insulating film on the first wiring layer; and an interlayer insulating film on the interlayer insulating film. Forming a first metal layer made of the same element as the first and second intermediate metal layers, and forming a via hole in the first metal layer, the interlayer insulating film, and the second intermediate metal layer. And exposing the surface of the first copper layer, and a second metal layer that is the same element as the first metal layer on the inner wall surface and the bottom surface of the via hole.
And depositing the metal layer by sputtering, and anisotropically processing the second metal layer by dry etching to leave only the inner wall surface of the via hole and expose the surface of the first copper layer at the bottom surface of the via hole. A step of reducing the surface of the first copper layer exposed on the bottom surface of the via hole by heating in a hydrogen atmosphere, and a step of reducing the first copper layer by a chemical vapor deposition method following the copper reduction step. Growing a second copper layer on the exposed surface of the copper layer and filling the via hole; and depositing a third copper layer on the second copper layer by sputtering and successively forming the first copper layer on the second copper layer. And a step of forming a second wiring layer by depositing a third metal layer made of the same element as that of the second metal layer. 3. The method for manufacturing a semiconductor device according to claim 1, wherein after the via hole filling step, the surface of the second copper layer is smoothed by bias sputtering in which copper sputter deposition and sputter etching compete with each other. A method of manufacturing a semiconductor device, which further comprises a step. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the main materials of the first, second and third metal layers are selected from the group consisting of tantalum, niobium and vanadium. A method of manufacturing a semiconductor device, characterized in that