JPH06223571A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Abstract] [PROBLEMS] To provide a semiconductor integrated circuit device including a highly sensitive sense amplifier that compensates an input offset due to a process variation of an amplification MOSFET, and a memory circuit that achieves high integration using the sense amplifier. [Structure] One conductivity type amplification MOSFET and the other conductivity type amplification MOSFET which constitute a CMOS sense amplifier
Amplification M that gives a time difference to the operation of T and starts the operation first
The variation in the threshold voltage of the OSFET and the input offset of the sense amplifier are reflected, and then the amplification MOSFET
In the form of a diode to precharge the bit line from the source side or disconnect the bit line from the sense amplifier during the initial amplification operation by capacitive coupling of the amplification MOSFET. [Effect] A highly sensitive sense amplifier can be obtained by an amplification operation that compensates for an input offset of an amplification MOSFET that dominantly performs an initial amplification operation for amplifying a minute input signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, for example, a dynamic RAM (random access memory) having a sense amplifier as a minute voltage amplifier circuit.
Memory) is related to effective technology.

[0002]

2. Description of the Related Art MOSF in a dynamic RAM
Regarding the sense amplifier that compensates for the variation in the ET threshold voltage, Japanese Utility Model Publication No. 56-21897 and Showa 5
There are two conferences of IEICE National Conference 2-288. In the former sense amplifier, an amplification MOSFET is connected to form a diode during a precharge period to precharge the bit line from the source side. The latter sense amplifier separates the source of the amplification MOSFET and performs the initial amplification operation by capacitive coupling.

[0003]

Dynamic type RAM
In that case, the sense amplifier is also C for low power consumption.
It is composed of a MOS circuit. With the CMOS circuit of such a sense amplifier, the precharge potential of the bit line is also set to an intermediate level of half the operating voltage. Therefore, the one that precharges the bit line with the power supply voltage as in the sense amplifier of Japanese Utility Model Laid-Open No. 56-21897 cannot be applied as it is. Also, amplification MO
Since the SFET is composed of a P-channel MOSFET and an N-channel MOSFET, there is a one-to-one correspondence between the offset voltage of the sense amplifier and the variation of the threshold voltage of the N-channel MOSFET and the P-channel MOSFET. Not only can I not do it, N
There is a problem that the precharge operation becomes difficult due to competition between the channel type side and the P channel type side.

Further, as in the sense amplifier described in National Conference of the Institute of Electronics, Communication and Communication, Japan, 1982, 2-288, it is necessary to make an extremely large capacitance value in the sense amplifier when operating the sense amplifier by capacitive coupling. Not relevant. That is, in the dynamic RAM, many memory cells are connected to one bit line in order to increase the storage capacity. Therefore, the parasitic capacitance value of the bit line becomes relatively large, and in order to increase the bit line potential to some extent by capacitive coupling, a considerably large capacitor is required. It is difficult to form such a capacitor in the sense amplifier. It is not feasible from the viewpoint of the degree of integration.

An object of the present invention is to provide a semiconductor integrated circuit device equipped with a high-sensitivity sense amplifier which compensates for an input offset due to a process variation of an amplification MOSFET. Another object of the present invention is to provide a semiconductor integrated circuit device provided with a memory circuit realizing high integration. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0006]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, the first and second switch MOSFETs are provided between the gate and the input terminal of the one conductivity type amplification MOSFET that constitutes the CMOS sense amplifier,
Third and fourth switch MOSFETs are provided between the gate and the common source side of the amplification MOSFET, the first and second switch MOSFETs are turned off, and the third and fourth switch MOSFETs are turned off.
Of the above-mentioned amplification MO by turning on the switch MOSFET of
The precharge of the bit line is performed by applying a precharge voltage obtained by adding a voltage corresponding to the threshold voltage of the first and second amplification MOSFETs to 1/2 of the operating voltage to the common source side of the SFET to precharge the bit line. Third and fourth switch MOSF
ET is turned off and the first and second switch MOSFE
After turning on T and applying a minute potential to one of the input terminals based on the precharge voltage to activate the amplifying MOSFET to perform an amplifying operation, C
Amplification MO of the other conductivity type that constitutes the MOS sense amplifier
Activate the SFET.

For the sense amplifier in which the initial amplification operation is performed by capacitive coupling, a switch MO is provided between the sense amplifier and the bit line.
An SFET is provided to disconnect the bit line from the sense amplifier during the initial amplification operation by capacitive coupling, and to reconnect the bit line to the sense amplifier when the amplified signal of the sense amplifier is increased.

[0008]

According to the above-mentioned means, the amplification MOSFET for starting the precharge and the amplification operation is limited according to the operation sequence, or the bit line having a large parasitic capacitance is disconnected, so that the initial amplification for amplifying a minute input signal is performed. A highly sensitive sense amplifier can be obtained by an amplification operation that compensates the input offset of the amplification MOSFET that performs the operation dominantly.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a circuit diagram of a main part of an embodiment of a dynamic RAM to which the present invention is applied. Each of the circuit elements shown in FIG. 1 is made of single crystal silicon by a known CMOS (complementary MOS) integrated circuit manufacturing technique.
It is formed on each semiconductor substrate.

In the same figure, a sense amplifier according to the present invention is mainly shown and a circuit related thereto is shown. That is, two sense amplifiers, two pairs of bit lines (sometimes referred to as data lines or digit lines) connected thereto, their pre-precharge circuits and eight word lines, and these bit lines and word lines. The control circuit of the sense amplifier and the memory cell and the precharge circuit provided at the intersection of and are illustrated as a representative. Of these, the sense amplifier and the preliminary precharge circuit related to one of the complementary bit lines B1T and B1B will be described below as an example.

In this embodiment, the sense amplifier basically has a CMOS structure. A P-channel type amplification MOSFET which constitutes a CMOS sense amplifier in order to compensate an input offset in the sense amplifier having the CMOS configuration.
Q10, Q11 and N-channel type amplification MOSFET Q
N-channel type amplification MOSFET Q
Mainly composed of 4 and Q5, P-channel type amplification MOSFET
Q10 and Q11 are used supplementarily. That is, when the sense amplifier starts operating, an N channel type amplification MOS
The FETs Q4 and Q5 are activated first to perform the amplification operation,
After the amplified signal becomes large to some extent, the P-channel type amplification MOSFETs Q10 and Q11 are activated to obtain a full swing high level / low level output signal corresponding to a minute input signal.

With such a configuration, the CMO
While using the S sense amplifier, the substantial input offset of the sense amplifier and the N channel type amplification MOSFET
It is possible to make one-to-one correspondence with variations (differences) in the threshold voltage of Q4 and Q5. In order to compensate for variations in the threshold voltage of the amplification MOSFETs Q4 and Q5 that perform amplification operation predominantly after the operation of the amplification MOSFETs of the sense amplifier is separated, Switch MOSFETs Q6 and Q8 are provided between and the bit lines B1B and B1T. Amplification MOSFET Q
Switch MOSFETs Q7 and Q9 are provided between the gates of 4 and Q5 and the common source line NS. These switch MOSFETs Q6 to Q9 are not particularly limited,
It is composed of an N-channel MOSFET.

The common source line NS is provided with a power switch MOSFET Q13 for activating the amplification MOSFETs Q4 and Q5. This power switch MOSFET Q13 supplies an operating voltage such as the ground potential of the circuit to the common source line NS to amplify the amplification MO.
SFETs Q4 and Q5 are activated.

The common source line NS is used for precharging the bit lines B1T, B1B in addition to activating the amplification MOSFETs Q4, Q5 as described above. That is, the common source line NS is connected to the precharge voltage VP.
A precharge MOSFET Q12 for supplying This precharge voltage VP is 1 of the operating voltage VCC.
It is set to a voltage (VCC / 2) + VTH obtained by adding the threshold voltage VTH of the MOSFETs Q4 and Q5 to the voltage VCC / 2 of / 2.

The switch MOSFETs Q6 and Q8,
Q7 and Q9 are complementarily switch-controlled by the control signal COM. That is, the switch MOSFETs Q6 and Q
The control signal COM is supplied to the gate of 8 and the control signal COM is supplied to the gates of the switch MOSFETs Q7 and Q9.
Are inverted and supplied through the inverter circuit N2. Similarly, the power switch MOSFET Q13 and the precharge MOSFET Q12 are complementarily switch-controlled by the control signal PN. In other words, the precharge MOSFET Q12 is controlled by the inverter circuit N1 which receives the control signal PN.

On the other hand, the P-channel type amplification MOSFETs Q10 and Q11 which are preliminarily made to function are latched as in the conventional case. The common source line PS is provided with a P-channel type power switch MOSFET Q14 that supplies an operating voltage such as the power supply voltage VCC.
The control signal PP for controlling the power switch MOSFET Q14 is delayed with respect to the control signal PN supplied to the gate of the N-channel type power switch MOSFET Q13, as described later in detail. As a result, the P-channel amplifier MOSFET Q as described above is
4, Q5 and N-channel type amplification MOSFET Q10, Q
Separation in the amplification operation of 11 is performed.

Between the complementary bit lines B1T and B1B, a preliminary precharge circuit including a short-circuit MOSFET Q1 and MOSFETs Q2 and Q3 for supplying a preliminary precharge voltage VCC / 3 is provided. The operation of the preliminary precharge circuit is basically the same as the operation of the conventional half precharge circuit, but the voltage level thereof changes from the half precharge voltage VCC / 2 by the short-circuit MOSFET Q1 to the ON state of the MOSFETs Q2 and Q3. Is different from the operation of the conventional circuit in that it is lowered to a potential such as VCC / 3.

The memory cell is provided between the word line and one bit line B1T or B1B. In the MOSFET QM for address selection, the gate is connected to the word line and one of the source and drain is the bit line B1T or B0.
Connected to T. A capacitor C for storing information is provided between the other source and drain and the plate voltage VPL.
S is provided. The arrangement of such memory cells is similar to that of the conventional dynamic RAM, and therefore detailed description thereof will be omitted. As for the word line, one word line selected by the word line selection circuit is brought into a selected state.

The complementary bit lines B0T and B0B and the related pre-precharge circuit, sense amplifier and sense amplifier control circuit, and precharge circuit shown as other representatives are the same as the above circuits, and the description thereof will be omitted. It is omitted. Correspondingly, circuit symbols for elements are omitted in the drawings.

FIG. 3 is a timing chart for explaining the operation of the sense amplifier shown in FIG. Signal P
The preliminary precharge operation is performed while C is at the high level. That is, when the control signal PC is high level, the MOS
The FETs Q1, Q2 and Q3 are turned on, and the complementary bit line BL is set to the pre-precharge voltage such as VCC / 3.

The signal PC is set to the low level to make the MOSF.
ETQ1 to Q3 are turned off, and the complementary bit line BL is set to a high impedance state. As a result, the complementary bit lines BL (B1T, B1B) hold the voltage VCC / 3 in the high impedance state.

When the control signal COM is set to low level, the switch MOSFETs Q6 and Q8 are turned off and the switch MOSFETs Q7 and Q9 are turned on. As a result, N-channel type amplification MOSFETs Q4 and Q5
Since the gate and common source side of
SFETs Q4 and Q5 are in diode form. As a result, the precharge voltage VP supplied from the common source line NS becomes the diode-type amplification MOSF.
It is transmitted to bit lines B1T and B1B through ETQ4 and Q5. At this time, if the threshold voltage of the amplification MOSFET Q5 is larger than that of the amplification MOSFET Q4, a level difference occurs between the bit lines B1T and B1B by the threshold voltage difference ΔVTH.

Since the bit lines B1T and B1B are precharged to VCC / 3 as described above, the level difference is small even if the bit lines B1T and B1B have a relatively large parasitic capacitance CB. The amplification MOSFE
Through TQ4 and Q5, the precharge level corresponding to approximately VCC / 2 can be changed at high speed. As described above, in order to set the precharge voltage of the bit lines B1T and B1B to approximately the half precharge voltage VCC / 2, the precharge voltage VP of the common source line NS is set to VCC / 2, M
In order to compensate for the level drop due to the threshold voltage VTH of the OSFETs Q4 and Q5, the corresponding voltage is raised to the added voltage.

The control signal COM is returned to the high level, the MOSFETs Q7 and Q9 are turned off, and the MOSFETs are turned off.
Amplification MOSFETs Q4 and Q with Q6 and Q8 turned on
When the word line WL is set to a selected state by setting 5 as a latch mode, the bit line to which the memory cell is connected has the accumulated charge of the capacitor CS of the memory cell and the precharge charge of the parasitic capacitance CB of the bit line. A minute potential change appears due to charge dispersion. This is the amplification MOSFET Q4 of the sense amplifier as the minute read signal VSIG from the memory cell.
Is transmitted to the gate of Q5 as a potential difference.

In this embodiment, since the offset voltage ΔVTH corresponding to the threshold voltages of the amplification MOSFETs Q4 and Q5 is applied to the bit line in advance by the precharge operation as described above, the read signal VSIG is directly amplified. It is given as a gate voltage difference to MOSFETs Q4 and Q5. In this state, the control signal PN is set to the high level and the amplification MOSFETs Q4 and Q5 are activated. This enables N-channel amplification MOSFET
Only Q4 and Q5 start the amplifying operation of the minute signal VSIG.

The N-channel type amplification MOSFET Q4
By the amplification operation of Q5 and Q5, the control signal PP is delayed to a low level when the amplified signal becomes large to some extent. As a result, the P-channel amplification MOSFET Q
10 and Q11 are activated, N channel type amplification MO
An amplification operation is performed together with the SFETs Q4 and Q5 to fully swing the potential of the bit line between a high level such as VCC and a low level such as 0V.

The P-channel type amplification MOSFET Q1
0 and Q11 also have offset voltages corresponding to the threshold voltage. However, at the time when it starts the amplifying operation, the input voltage difference becomes so large that such offset voltage can be ignored, so that it can be substantially not affected by the offset. That is, the P-channel type amplification MOSFETs Q10 and Q11 prevent the drop of the potential of the bit line that should be set to the high level by the amplification operation by the N-channel type amplification MOSFETs Q4 and Q5, and pull up it to the power supply voltage VCC, so to speak. It is responsible for the general amplification operation.

After the memory access is completed, the word line WL
Is reset and the control signals PN and PP for activating the sense amplifier are also reset, and then the control signal PC is set to a high level, the MOSFETs Q1 to Q3 are turned on, and the complementary bit line is turned on by turning on the MOSFET Q1. The high level and the low level of B1T and B1B are short-circuited, and it is about to become VCC / 2.
And the ON state of Q3 changes the pre-precharge voltage VCC / 3 which is slightly lower than that.

FIG. 2 shows a circuit diagram of a main part of another embodiment of the dynamic RAM to which the present invention is applied. In this embodiment, of the CMOS sense amplifiers, P
The channel type amplification MOSFET is dominantly used, and the N channel type amplification MOSFET is auxiliary used. That is, a P-channel type MOSFET and an N-channel type MOS which constitute the sense amplifier of the circuit of FIG.
It has a configuration in which the FET is replaced. Therefore, among the circuit elements constituting the sense amplifier, the circuit symbol is the same and the N-channel MOSFET is the P-channel MOS.
The FET is replaced by the FET, and the P-channel MOSFET is replaced by the N-channel MOSFET.

As described above, the P channel type amplification MOSF
When ETQ4 and Q5 are predominantly used, the precharge voltage VP is lowered to VCC / 2-VTH.
On the other hand, the spare precharge voltage of the bit line is
Raised as high as 2VCC / 3. This is because when the P-channel type amplifying MOSFET is dominantly used, the operating voltage is on the 0 V side, and the respective levels must be reversed correspondingly.

In the circuit diagrams of FIGS. 1 and 2,
Although it is shown that the P-channel type power switch MOSFET and the N-channel power switch MOSFET are provided on one side of the sense amplifier row, these MO
Since it is necessary to form the SFET relatively large, it is laid out above and below the sense amplifier row on the semiconductor substrate.

FIG. 4 is a timing chart for explaining the operation of the sense amplifier shown in FIG. Although it is basically the same as that in FIG. 3, the precharge voltage and the like are set so as to be different in accordance with the above-mentioned operating voltage.

Further, the read signal VS from the memory cell
When IG is at a level opposite to the offset voltage ΔVTH, it is apparently not present on the bit lines B1T and B1B, but the read voltage VSIG shown by the dotted line in the figure is present between the gate voltages of the amplification MOSFETs Q4 and Q5. It is applied, and accordingly, the bit lines B1T and B1B are amplified to a high level and a low level.

FIG. 5 shows a circuit diagram of a main part of another embodiment of the dynamic RAM to which the present invention is applied. Although the circuit symbols of the circuit elements in the figure are the same as those in FIG. 1 and FIG. 2, it should be understood that each basically has a separate circuit function. This also applies to other circuit diagrams.

In this embodiment, of the CMOS sense amplifiers, the N-channel type amplification MOSFET is predominantly used,
The P-channel type amplification MOSFET is used auxiliary. As a result, the threshold voltage difference between the N-channel type amplification MOSFETs Q4 and Q5 which operates dominantly corresponds to the substantial input offset of the sense amplifier, and the capacitive coupling is used as the compensation method.

The capacitors shown in the form of MOS capacitors are provided at the sources of the amplification MOSFETs Q4 and Q5 whose gates and drains are cross-connected. That is, MO
The drains and sources of the SFETs Q6 and Q7 are connected to each other and connected to the sources of the amplification MOSFETs Q4 and Q5 as one electrode. MOS that acts as a capacitor
The gates of the FETs Q6 and Q7 serve as the other electrode of the capacitor and are supplied with the control signal COM.

The sources of the amplification MOSFETs Q4 and Q5 are provided with MOSFETs Q8 and Q9 which operate as power switches. These MOSFETs Q8 and Q9
Also acts to isolate the sources of the amplification MOSFETs Q4 and Q5.

The P-channel amplifier MOSFETs Q10 and Q11, which are preliminarily operated, are latched. Preliminarily functioning P-channel amplification MOS
FET Q10 and Q11 are N-channel type amplification MOSF
Unlike ETQ4 and Q5, the source is common source line PS
Connected to. The common source line PS is provided with a P-channel type power switch MOSFET Q12 that supplies an operating voltage such as the power supply voltage VCC. Control signal P for controlling this power switch MOSFET Q12
As will be described in detail later, P is delayed with respect to the control signal PN supplied to the N-channel type power switch MOSFETs Q8 and Q9. As a result, the P-channel amplification MOSFETs Q4 and Q5 and the N-channel amplification MOSFETs Q10 and Q11 are separated in amplification operation as described above.

The input / output node of the above sense amplifier is connected to complementary bit lines B1T and B1B via switch MOSFETs Q13 and Q14. These switches MO
The control signal BS is supplied to the gates of the SFETs Q13 and Q14.

The complementary bit lines B1T and B1B have MOSs
A precharge circuit including FETs Q1 to Q3 is provided. This precharge circuit has the same circuit configuration as the preliminary precharge circuit shown in FIGS. 1 and 2, but is different in that a half precharge voltage such as VCC / 2 is used. Other configurations such as memory cells, word lines and word line selection circuits
Since it is the same as FIG. 1 and FIG. 2, description thereof will be omitted.

FIG. 7 is a timing chart for explaining the operation of the sense amplifier shown in FIG. Signal P
The precharge operation is performed while C is at the high level.
That is, the high level of the control signal PC causes the MOSFE
TQ1, Q2, and Q3 are turned on, and the complementary bit line BL is set to a precharge voltage such as VCC / 2. This voltage VCC / 2 is used for amplifying MOSFETs Q4 and Q4.
Since they are supplied to the gate and drain of No. 5, the source potential of each of them is lowered by the threshold voltage VTH. This potential acts as a capacitor M
It is stored in the MOS capacitors of the OSFETs Q6 and Q7.

The signal PC is set to the low level to set the MOSF.
ETQ1 to Q3 are turned off, and the complementary bit line BL is set to a high impedance state. As a result, the complementary bit lines BL (B1T, B1B) hold the voltage VCC / 2 in the high impedance state. Also, amplification MO
Voltages corresponding to the respective threshold voltages VTH are held between the gates and sources of the SFETs Q4 and Q5.

When the word line WL is selected, a minute potential change is caused in the bit line connected to the memory cell due to charge dispersion between the accumulated charge of the capacitor CS of the memory cell and the precharge charge of the parasitic capacitance CB of the bit line. Appears. This is transmitted as a minute read signal VSIG from the memory cell to the gates of the amplification MOSFETs Q4 and Q5 of the sense amplifier as a potential difference.

That is, as described above, the amplification MOSFET
A bias voltage corresponding to each threshold voltage is applied between the gate and the source of the MOSFET by the bit line potential and the holding voltages of the MOSFETs Q6 and Q7 acting as capacitors. Therefore, the potential difference between the bit lines B1T and B0B is supplied as a difference voltage between the gates of the amplification MOSFETs Q4 and Q5 regardless of the difference in threshold voltage as described above.

When the differential voltage according to the read signal as described above is applied to the gates of the amplification MOSFETs Q4 and Q5, the control signal BS is set to the low level and the switch MOSFET Q is turned on.
13 and Q14 are turned off. As a result, the bit lines B1T and B1 having a sense amplifier and a large parasitic capacitance CB are provided.
1B is cut off.

When the control signal COM is set to the low level, the source potentials of the amplifying MOSFETs Q4 and Q5 are lowered and activated with a voltage difference corresponding to the threshold voltage difference due to capacitive coupling by the gate capacitances of the capacitors Q6 and Q7. Turn into At this time, the sense amplifier operates as the bit line B1.
Since it is separated from T and B0B, the parasitic capacitance on the input side can be reduced to a level almost equal to the gate capacitance values of the MOSFETs Q6 and Q7, etc. Therefore, the amplification MOSFETs Q4 and Q5 form a pair of input terminals by the capacitive coupling as described above. Increase the potential difference of.

After this, the signal PN is set to the high level and N
Channel side power switch MOSFETs Q8 and Q9
Turn on to start full-scale amplification operation. At the same time, the signal PP is set to low level (not shown),
The power switch MOSFET Q12 on the P-channel side is turned on, and the amplification MOSFET Q on the P-channel side is turned on.
Activates 10 and Q11.

The P-channel type amplification MOSFET Q1
0 and Q11 also have offset voltages corresponding to the threshold voltage. However, at the time when it starts the amplifying operation, the input voltage difference becomes so large that such offset voltage can be ignored, so that it can be substantially not affected by the offset. That is, the P-channel type amplification MOSFETs Q10 and Q11 prevent the potential of the bit line from dropping to a high level due to the amplification operation by the capacitive coupling of the N-channel type amplification MOSFETs Q4 and Q5 and prevent it from dropping to the power supply voltage VC.
It is so-called a complementary amplifying operation of pulling up to C.

Power switch MOSFET as described above
After turning on, the signal BS is set to the high level to turn on the switch MOSFETs Q13 and Q14. As a result, the bit line B1 having a large parasitic capacitance
Since T and B1B are connected to the sense amplifier, the signal becomes small, but the potential of the bit line is expanded to a high level such as the power supply voltage VCC and a low level such as the ground potential of the circuit by the amplifying operation. .

After the memory access is completed, the word line WL
Is reset and the control signals PN and PP for activating the sense amplifier are also reset, and then the control signal PC is set to a high level, the MOSFETs Q1 to Q3 are turned on, and the complementary bit line is turned on by turning on the MOSFET Q1. The high level and low level of B1T and B1B are short-circuited, and a precharge voltage such as VCC / 2 is obtained.

FIG. 6 shows a circuit diagram of a main part of still another embodiment of the dynamic RAM to which the present invention is applied. In this embodiment, of the CMOS sense amplifiers, the P-channel type amplification MOSFET is predominantly used,
The N-channel type amplification MOSFET is used auxiliary. That is, a P-channel type MOSFET and an N-channel type M which constitute the sense amplifier of the circuit of FIG.
It has a configuration in which the OSFET is replaced. Therefore,
Of the circuit elements forming the sense amplifier, the N-channel MOSFET is a P-channel M without changing the circuit symbol.
Replaced by OSFET, P-channel type MOSFE
T has been replaced by an N-channel MOSFET.

FIG. 8 is a timing chart for explaining the operation of the sense amplifier shown in FIG. Basically the same as in FIG. 7, but with P-channel amplification MOSF
In response to the operating voltage VCC of ET, the signal COM is changed to the high level contrary to FIG. The other basic structure is the same as that of the above-mentioned embodiment, and therefore its explanation is omitted.

FIG. 14 shows a sectional view of the element structure of one embodiment of the dynamic memory cell. Reference numeral 46 is a word line, which is composed of a polysilicon layer. 48
Is a storage electrode constituting the capacitor CS, is an insulating film of 54, and acts as a dielectric of the capacitor CS.
A plate electrode 49 is supplied with the plate voltage VPL as described above. Reference numeral 50 is a bit line, which is made of polycide. Reference numeral 52 is an aluminum layer for the word line shunt.

The structure of the memory cell is a laminated type. 54
Usually Although SiO ₂ or Si ₃ N ₄ or the like is used, the bit line capacitance CB by connecting a large number of memory cells to reduce the size of the capacitor CS or, or one of the bit lines for high integration In order to increase the read voltage, which decreases relatively due to the increase,
A high dielectric film such as Ta ₂ O ₃ may be used so as to increase the capacitance value of. When such a high dielectric film is used, the structure of the memory cell can be simple.

Although not particularly limited, the amplifying MOS shown in FIG.
The capacitor that causes the FETs Q4 and Q5 to perform an initial operation by capacitive coupling is a capacitor CS that constitutes a memory cell.
Use the same structure as. In this case, the amplification MOSFETs Q4 and Q5 can have the same structure as the address selection MOSFET QM that constitutes the memory cell. However, the size may be larger than that of the memory cell in order to increase the amplification gain.

As described above, M having the same structure as the memory cell
Amplification MOS using OSFET QM and capacitor CS
A MOSFET for power switch or separation by configuring a FET Q4 and a capacitor provided at the source
By adding a MOSFET corresponding to Q8, the sense amplifier can be built relatively easily according to the bit line pitch. In this case, when a high dielectric film is used for the capacitor, a large capacitance value can be obtained, so that a large amplified signal can be obtained by capacitive coupling of the sense amplifier.

9 to 11 are circuit diagrams showing one embodiment of the dynamic RAM to which the present invention is applied. FIG. 9 shows a circuit diagram of the memory array and row system selection circuit, FIG. 10 shows a circuit diagram of the sense amplifier and column system selection circuit, and FIG. 11 shows a block diagram of the control system and the power supply system. It is shown. In FIGS. 9 and 10, the MO with an arrow added to the channel portion (back gate)
The SFET is a P-channel type. This point is different from the notation method in which the gate of the P-channel MOSFET is circled as in FIGS. 1 and 2. M in this invention
The OSFET is an insulated gate field effect transistor (IG
FET) is used in the sense.

In FIG. 9, the memory array MARY shown as an example is of a two-intersection (folded bit line) system, although not particularly limited thereto. In the figure, the pair of rows is exemplarily shown as a representative. A pair of complementary bit lines (data line or digit line) B0 arranged in parallel
Input / output nodes of a plurality of memory cells each composed of an address selection MOSFET Qm and an information storage capacitor Cs are distributed and coupled to T and B0B with a predetermined regularity as shown in FIG.

In FIG. 10, the precharge circuit PC
Is a switch MO provided between complementary bit lines B0T and B0B, like a MOSFET Q5 shown as a representative.
It is composed of SFET. The MOSFET Q5 is turned on in the chip non-selected state or before the memory cell is selected by supplying the gate with the precharge signal PC generated in the chip non-selected state. As a result, in the previous operation cycle, the complementary bit line B by the amplification operation of the sense amplifier SA described later is performed.
The high level and the low level of 0T and B0B are short-circuited to set the complementary bit lines B0T and B0B to a precharge voltage of about VCL / 2 (HVC).

Although not particularly limited, when the chip is left in a non-selected state for a relatively long time, the precharge level is lowered due to a leak current or the like. Therefore, in this embodiment, the switch MOSFETs Q45 and Q46 are provided to supply the half precharge voltage HVC. The voltage generating circuit for forming the half precharge voltage HVC has a relatively small current supply capability so as to compensate for the leak current and the like, although its specific circuit is not shown. This suppresses an increase in power consumption.

The sense amplifier SA is deactivated before the precharge MOSFET Q5 etc. is turned on by the chip non-selection state of the DRAM or the like. At this time, the complementary bit lines B0T and B0B hold a high level and a low level in a high impedance state. When the RAM is put into operation, the precharge MOSFETs Q5, Q45, Q46 and the like are turned off before the sense amplifier SA is put into operation. In such a half precharge system,
Since the complementary bit lines B0T and B0B are formed by simply short-circuiting the high level and the low level, power consumption can be reduced.

Under the half precharge system as described above, in the amplification operation of the sense amplifier SA, the complementary bit lines B0T and B0 are centered around the precharge level.
Since 0B changes in the common mode like the high level and the low level, the noise level generated by the capacitive coupling can be reduced.

The sense amplifier SA is a circuit for offset compensation by the capacitive coupling method as shown in FIG. However, as in the circuit of FIG.
ET and the power switch MOSFET are not integrated, but the source of the MOSFET for isolation is connected to the source line N.
Connected to S, a power switch MOSFET is provided as in the P channel side.

In this embodiment, although not particularly limited, the power supply voltage VCL is supplied through the P-channel MOSFETs Q12 and Q13 in parallel, and the ground voltage VSS of the circuit is supplied through the N-channel MOSFETs Q10 and Q11 in parallel. These power switch MOSF
ETQ10, Q11 and MOSFETs Q12, Q13
Are commonly used for the unit sense amplifier USA provided in another similar row in the same memory array. In other words, the sense amplifier S in the same memory array
P-channel MOSFET and N-channel M in A
The source lines PS and SN are commonly connected to the OSFET.

Complementary timing pulses PN1 and PP1 for activating the sense amplifier SA in the operation cycle are applied to the gates of the MOSFETs Q10 and Q12, and M
Complementary timing pulses PN2, PP2 delayed from the timing pulses PN1, PP1 are applied to the gates of the OSFETs Q11, Q13. As a result, the operation of the sense amplifier SA is divided into two stages.

When the timing pulses PN1 and PP1 are generated, that is, in the first stage, MOSFETs Q10 and Q12 having a relatively small conductance are used.
Due to the current limiting action of the above, the minute read voltage applied between the pair of data lines from the memory cell is amplified by the capacitive junction as described above without being subjected to an undesired level fluctuation. Above sense amplifier SA
When the timing pulses PN2 and PP2 are generated after the difference between the complementary data line potentials is increased by the amplifying operation in step 1, that is, when the second stage is entered, the MOSFETs Q11 and Q13 having a relatively large conductance are turned on. It

The amplification operation of the sense amplifier SA is the MOSF.
It is speeded up by turning on ETQ11 and Q13. In this way, the sense amplifier S is divided into two stages.
By performing the amplification operation A, it is possible to perform high-speed reading of data while preventing undesired level changes in the complementary data lines. Although not particularly limited, in the second step, the bit line B0T, which has been separated,
B0B is recombined by a switch MOSFET (not shown) to rewrite the memory cell.

In FIG. 9, the X (row) address decoder is not particularly limited, but the first address decoder circuit including the gate circuits G1 to G4 and the unit circuit UXDC.
It is configured by being divided into two so as to include a second address decoder circuit such as R. In the figure, one circuit (unit circuit) UXDCR forming the second address decoder circuit is shown.
And a NOR (NO) forming the first address decoder circuit.
R) Gate circuits G1-G4 are shown. The circuit symbols of the gate circuits G2 and G3 are omitted. The unit circuit UXDCR forms a decode signal for four word lines.

The four gate circuits G1 to G4 forming the first X-decoder circuit have four word combinations by combining the word line selection signals X0B, X0T and X1B, X1T corresponding to the address signal of the lower 2 bits. Line selection timing signal φx0
To φx3 are formed. These word line selection timing signals φx0 to φx3 are transmitted to the transmission gate above MOSFETQ.
20 to Q23 through the unit word line driver UWD0
~ Input to UWD3.

The word line driver WD is a unit circuit UWD.
0 is representatively shown as a typical example, and P-channel MOSFET Q26 and N-channel MOSFET Q
CMOS drive circuit composed of 27 and P-channel MOSFE provided between its input and operating voltage terminal VCH
It is composed of TQ24 and Q25. P channel MOS
The gate of the FET Q24 is supplied with the precharge signal wph level-converted by the level conversion circuit as described above. The drive output of the word line W0 is supplied to the gate of the P-channel MOSFET Q25.

The MOSFET Q25 has an internal step-down voltage VC.
Word line selection timing signal φx0 formed according to L
Is set to a high level and the word line W0 is set to a non-selection level such as the ground potential, it receives the low level and C
The input level of the MOS circuit is pulled up to the high voltage VCH to surely turn off the P-channel MOSFET Q26. As a result, the CM corresponding to the unselected word line is
P-channel MOSFET Q2 forming the OS drive circuit
It is intended to prevent the direct current from being consumed between 6 and Q27.

By dividing the X address decoder into two as described above, the pitch of the unit circuits UXDCR forming the second X address decoder circuit and the pitch of the word lines can be matched. As a result, useless space can be prevented from being generated on the semiconductor substrate.

Switch MOSFETs Q1 to Q4 and the like are provided between the far end side of the word line and the ground potential of the circuit.
Signals WC0 to WC3 having a phase opposite to the selection signal supplied to the corresponding word lines W0 to W3 are supplied to the gates of these switch MOSFETs Q1 to Q4. Thereby, the switch MO corresponding to the selected word line
Only SFET turned off, other switch MOSFET
Is turned on. As a result, it is possible to prevent the unselected word line from being undesirably raised to the intermediate potential due to capacitive coupling due to the rising of the selected word line.

In FIG. 10, a row (X) address buffer R-ADB has a timing signal (not shown) formed by a control circuit CONT described later based on a row address strobe signal RASB supplied from an external terminal.
The address signal AX supplied from the external terminal is fetched in synchronization with the row address strobe signal RASB in the operating state, and is held, and the level corresponding to the step-down voltage VCL is generated. The converted internal complementary address signal ax is formed and transmitted to the first and second row address decoders. The internal complementary address signal ax is composed of a pair of in-phase signal and anti-phase signal with respect to the address signal AX supplied from the external terminal.

Column (Y) address buffer C-ADB
Is activated by a timing signal (not shown) formed by the control circuit CONT described later based on the column address strobe signal CASB supplied from the external terminal, and in the operating state, is synchronized with the column address strobe signal CASB. Then, the address signal AY supplied from the external terminal is taken in, held, and the level-converted internal complementary address signal ay corresponding to the step-down voltage VCL is formed and transmitted to the column decoder CD. The internal complementary address signal ay and a pair of an in-phase signal and an anti-phase signal with respect to the address signal AY supplied from the external terminal. In the figure, the row address buffer R-ADB and the column address buffer C-ADB are combined to form address buffers R and C.
-It is expressed like ADB.

The column decoder CD basically has the above X
It is composed of an address decoder circuit similar to the address decoder and decodes the complementary address signal ay supplied from the column address buffer C-ADB to generate a selection signal to be supplied to the column switch CW in synchronization with the data line selection timing signal φy. Form.

The column switch CW selectively couples the complementary bit lines B0T and B0B and the complementary common input / output lines CDT and CDB like the representatively shown N channel MOSFETs Q42 and Q43. These MOS
A selection signal from the column decoder CD is supplied to the gates of the FETs Q42 and Q43.

Between the common input / output lines CDT and CDB,
An N-channel type precharge MOSFET Q44 forming a precharge circuit similar to the above is provided.
The MOSFET Q44 is controlled by the precharge signal PCC. A pair of input / output nodes of a main amplifier MA having a circuit configuration similar to that of the sense amplifier USA of the above unit is coupled to the common input / output lines CDT and CDB.

The amplified output signal of the main amplifier MA is sent to the outside from the external terminal Dout via the data output buffer DOB. In the read operation mode, the data output buffer DOB is activated by the timing signal r, and the output signal of the main amplifier MA activated at this time is amplified and level-converted to a level corresponding to the external power supply voltage VCC. Send to external terminal Dout. In the write operation mode, the output signal Dout of the data output buffer DOB is brought into a high impedance state by the timing signal r.

The output terminals of the data input buffer DIB are coupled to the common input / output lines CDT and CDB. In the write operation mode, the data input buffer DIB is activated by the timing signal w, and the external terminal D
By converting the level of the complementary write signal according to the write signal supplied from in to a level corresponding to the internal step-down voltage VCL and transmitting the level to the common input / output lines CDT, CDB,
Writing to the selected memory cell is performed. In the read operation mode, the timing signal w causes the output of the data input buffer DIB to be in a high impedance state.

In FIG. 11, the various timing signals described above are formed by the control circuit CONT. The control circuit CONT forms various timing signals necessary for the operation of the RAM, such as the main timing signals shown as the representative above. That is, the control circuit CONT is configured to control the address strobe signal RASB supplied from the external terminal.
, And CAS and the write enable signal WEB, the series of various timing pulses are formed.

The circuit symbol REFC is an automatic refresh circuit, which includes a refresh address counter and the like. This automatic refresh circuit REF
C is not particularly limited, but is not limited to address address strobe signal R
When the column address strobe signal CAS is set to the low level before the row address strobe signal RASB is set to the low level by the logic circuit receiving ASB and CASB, it is determined as the refresh mode, and the row address strobe signal RASB is used as a clock. A refresh address signal ax 'generated by the address counter circuit is transmitted.

This refresh address signal ax 'is
The row address buffer R having a multiplexer function
-Transmitted to the row address decoder circuit via ADB. Therefore, in the refresh mode, the refresh control circuit REFC causes the address buffer R-AD to
A control signal for switching B is generated (not shown). As a result, the refresh address signal ax '
The refresh operation is performed by selecting one word line corresponding to (CAS before RAS refresh).

The internal voltage down converter VCLG receives a power supply voltage VCC of about 5V supplied from an external terminal and generates a stabilized internal voltage downvoltage VCL of about 3.3V. The internal booster circuit VCHG receives a pulse signal formed based on the stabilized internal step-down voltage VCL and forms a boosted voltage required for the word line selecting operation. The substrate voltage generation circuit VBG is not particularly limited,
Receiving a pulse signal formed based on the stabilized internal step-down voltage VCL, a negative bias voltage -Vbb applied to the substrate is generated.

FIG. 12 shows a chip layout diagram of an embodiment of a dynamic RAM using the sense amplifier according to the present invention. In this embodiment, it has a storage capacity of about 16 Mbits.

The memory array is divided into 8 blocks each having about 2 Mbits. Sense amplifier SA is 2
It is arranged in the middle part of one block and consists of 8192 pieces in total. Row decoder RD and word driver WD
Are arranged in a direction perpendicular to the sense amplifier row so as to be sandwiched between two pairs of blocks. A column decoder CD or a column decoder CD is provided at the center of the chip in the vertical direction.
And two data registers DR are arranged.

In one block, the sense amplifier S
The number NSA of memory cells connected to A is set to 1024 per bit line. The number of memory cells connected to one word line is NWD2048.

When as many as 1024 memory cells are connected to one bit line as described above, the bit line capacitance CB increases. On the other hand, since the size of the memory cell cannot be increased in terms of the degree of integration, the amount of signals read to the bit line can be reduced.

The threshold voltage variation of the MOSFET is generally about 50 mV. Therefore, it is necessary to secure about 100 mV as the signal voltage read to the bit line. Therefore, when the conventional sense amplifier is used, as shown in FIG. 13, one bit line is connected to 256 memory cells. Similarly, 1
The number of memory cells connected to one word line is also about 1024. As a result, the ratio of the sense amplifier SA occupying the semiconductor chip is increased as indicated by hatching in the figure, which is a cause of hindering the downsizing of the chip size or the high integration degree.

On the other hand, as in the present invention, the MOSF
In the sense amplifier that compensates for the variation in the ET threshold voltage, in other words, in the sense amplifier that compensates for the input offset, the signal amount of the bit line may be about 50 mV if the same operation margin as in the conventional case is obtained. Therefore, it is necessary to set the ratio of the capacitance value CS of the memory cell to the parasitic capacitance value CB of the bit line, CB / CS, to about 10 in the past, but by using the sense amplifier of the present application, It can be increased to about 20.

When CB / CS = 20, the read signal amount when the bit line potential is 3 V is as shown in the following equation (1). 3V × 1 / (20 + 1) × 1/2 = 71 mV (1) Similarly, about 2.5 mV is about 60 mV, and 2 V is 48 m.
A signal amount of 36 mV is obtained at V and 1.5 V,
It can be seen that up to 2.5 V can be read without sacrificing the operating speed compared with the conventional circuit.

By the input offset compensation of the sense amplifier as described above, the number of memory cells connected to one bit line is increased to 1024 and the number of memory cells connected to the word line is also increased. As a result, the semiconductor chip of FIG. 12 has about the same memory capacity and about the same performance as the semiconductor chip of FIG.
It can be reduced to about 0%. That is, FIG.
In the dynamic RAM of, the occupancy of the memory cell is 8
This is because it can be increased to 0% or more, whereas in the dynamic RAM of FIG. 13, the memory cell occupancy rate is only about 50%.

The operational effects obtained from the above embodiment are as follows. That is, (1) One conductivity type amplification MOSFET and the other conductivity type amplification MOSFET that constitute the CMOS sense amplifier.
Amplification MO that gives a time lag to the operation of and starts the operation first
The variation of the threshold voltage of the SFET and the input offset of the sense amplifier are reflected, and the first and second switch MOSFETs are provided between the gate and the input terminal, and the amplification M
The third and fourth switch MOSFETs are provided between the gate of the OSFET and the common source side, the first and second switch MOSFETs are turned off, and the third and fourth switch MOSFETs are turned on. The first and second half of the operating voltage is applied to the common source side of the MOSFET.
The precharge voltage added with the voltage corresponding to the threshold voltage of the amplifying MOSFET is applied to precharge the bit line, the third and fourth switch MOSFETs are turned off, and the first and second switches are turned on. The MOSFET is turned on, and a minute potential is applied to one of the input terminals with the precharge voltage as a reference to amplify the amplification MOSFET.
After T is activated to perform the amplification operation, the other conductivity type amplification MOSFET that constitutes the CMOS sense amplifier is activated, so that the offset of the sense amplifier can be compensated. The effect that it can be obtained is obtained.

(2) Variations in the threshold voltage of the amplification MOSFET that starts the operation first by giving a time difference to the operation of the amplification MOSFET of one conductivity type and the amplification MOSFET of the other conductivity type that form the CMOS sense amplifier. And the input offset of the sense amplifier, and a switch MOSFET is provided between the bit line and the bit line to disconnect the bit line from the sense amplifier during the initial amplification operation by capacitive coupling of the amplification MOSFET that starts the operation above. As a result, the amplifying operation by the capacitive coupling can be realized with a small capacitance, and the offset of the sense amplifier can be compensated, so that the highly sensitive sense amplifier can be obtained.

(3) Since the number of memory cells connected to the bit line is increased by using the sense amplifier in which the input offset is compensated as described above, the memory occupation rate of the semiconductor chip can be increased. The effect that the chip size can be reduced can be obtained.

(4) Since the amount of signal read to the bit line can be substantially increased by using the above-described sense amplifier in which the input offset is compensated, there is an effect that high-speed reading of the dynamic RAM can be realized. can get.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say. For example, RA
The layout of the entire M is based on the configuration shown in FIG. 12, and the peripheral circuits can be arranged in various embodiments. The input circuit, the output circuit, etc. are arranged in the central portion of the chip. Connection with the input circuit and output circuit,
It is performed using LOC technology.

In addition to the DRAM having a large storage capacity as in this embodiment, the present invention can be applied to various semiconductor integrated circuit devices including a combination with a large-scale logic gate circuit and a memory circuit. In the above description, the case where the invention made by the inventor of the present application is mainly applied to a large-scale DRAM which is the technical field of the background has been described, but the present invention is not limited to this, and a high-sensitivity sense amplifier is used. It can also be used for various memory circuits such as required ROM.

[0099]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, there is a time difference between the operation of the one conductivity type amplification MOSFET and the other conductivity type amplification MOSFET that form the CMOS sense amplifier, and the variation in the threshold voltage of the amplification MOSFET that starts the operation first and the sense amplifier It is reflected in the input offset, and the first and second switch MOSFs are provided between the gate and the input terminal.
ET and the third and fourth switch MOSFETs are provided between the gate and the common source side of the amplification MOSFET,
The first and second switch MOSFETs are turned off, the third and fourth switch MOSFETs are turned on, and half the operating voltage is applied to the common source side of the amplification MOSFET.
Is applied to the bit line to precharge the bit line to turn off the third and fourth switch MOSFETs. , The first and second switches M
After turning on the OSFET and applying a minute potential to one of the input terminals with the precharge voltage as a reference to activate the amplifying MOSFET to perform an amplifying operation, the other conductivity forming the CMOS sense amplifier Since the offset of the sense amplifier can be compensated by activating the type amplifying MOSFET, a highly sensitive sense amplifier can be obtained.

One conductivity type amplification MOSFET and the other conductivity type amplification MOSF constituting the CMOS sense amplifier.
A time difference is given to the operation of ET so that the variation in the threshold voltage of the amplification MOSFET that starts the operation first and the input offset of the sense amplifier are reflected, and a switch MOSFET is provided between the bit line and By separating the bit line from the sense amplifier during the initial amplification operation by the capacitive coupling of the amplification MOSFET that starts the operation, the amplification operation by the capacitive coupling can be realized with a small capacitance, and the offset of the sense amplifier can be compensated. Can obtain a highly sensitive sense amplifier.

[Brief description of drawings]

FIG. 1 is a main part circuit diagram showing an embodiment of a dynamic RAM to which the present invention is applied.

FIG. 2 is a main part circuit diagram showing another embodiment of a dynamic RAM to which the present invention is applied.

FIG. 3 is a timing diagram illustrating an operation of the sense amplifier of FIG.

FIG. 4 is a timing diagram illustrating an operation of the sense amplifier of FIG.

FIG. 5 is a main part circuit diagram showing another embodiment of a dynamic RAM to which the present invention is applied.

FIG. 6 is a main part circuit diagram showing still another embodiment of a dynamic RAM to which the present invention is applied.

7 is a timing diagram for explaining the operation of the sense amplifier of FIG.

8 is a timing diagram for explaining the operation of the sense amplifier of FIG.

FIG. 9 is a circuit diagram showing an embodiment of a memory array and row system selection circuit in a dynamic RAM to which the present invention is applied.

FIG. 10 is a dynamic RAM to which the present invention is applied.
3 is a circuit diagram showing an example of a sense amplifier and a column system selection circuit.

FIG. 11 is a dynamic RAM to which the present invention is applied.
FIG. 3 is a block diagram showing an example of a control system and a power supply system circuit among them.

FIG. 12 is a dynamic RAM to which the present invention is applied.
It is a chip layout diagram showing an example of.

FIG. 13 is a chip layout diagram showing an example of a conventional dynamic RAM.

FIG. 14 is a dynamic RAM to which the present invention is applied.
3 is a cross-sectional view of an element structure showing an example of the memory cell of FIG.

[Explanation of symbols]

MA ... Memory array, RD ... Row decoder, CD ... Column decoder, WD ... Word line driver, PC ... Precharge circuit, USA ... Sense amplifier unit circuit, SA ... Sense amplifier, MA ... Main amplifier, CW ... Column switch, R , C-ADB ... Address buffer, CONT ... Control circuit, REFC ... Automatic refresh circuit, DOB ... Data output buffer, DIB ... Data input buffer, VB
G ... Substrate bias generation circuit, G1-G8 ... Gate circuit,
UWD0 to UWD3 ... Word line driver unit circuit, VC
LG ... Internal voltage down converter, VCHG ... Internal voltage booster. 44 ...
Source / drain diffusion layer, 46 ... Word line, 48 ... Storage electrode, 49 ... Plate electrode, 50 ... Bit line, 52 ... Word line shunt aluminum layer, 53 ... Gate insulating film, 54 ... Insulating film (dielectric).

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Internal reference number FI Technical indication 7210-4M H01L 27/10 325 C (72) Inventor Kazuyoshi Oshima 2326 Imai, Ome, Tokyo Hitachi Device Development Center

Claims (8)

[Claims] 1. A first conductivity type first amplification MOSFET in which one source and drain are connected to a first input terminal.
A first conductivity type second amplification MOSFET whose one source and drain are connected to the second input terminal, a first input terminal and a gate of the second amplification MOSFET, and a second input terminal First and second switch MOSFETs connecting the gates of the first amplifying MOSFETs, and third and fourth switch MOSFETs connecting the gates of the first and second amplifying MOSFETs to the other source and drain, respectively. And a gate and one source and drain of the gate are cross-connected to the first and second input terminals to form a latch form, and third and fourth amplification MOSs of the second conductivity type are provided.
An FET, a first conductivity type power switch MOSFET that supplies one operating voltage to the other source and drain of the first and second amplification MOSFETs, and the third and fourth amplification MOSFETs in common. Second-conductivity-type power switch MOSFET for applying the other operating voltage to the other source and drain, and the above-mentioned first and second amplification M
1 / s of the operating voltage to the other source and drain of the OSFET
And a precharge MOSFET that gives a precharge voltage obtained by adding a voltage corresponding to the threshold voltage of the first and second amplification MOSFETs to the second voltage, and turns on the third and fourth switch MOSFETs. Charge MOSF
A first period in which a precharge voltage is supplied from ET to precharge the first and second input terminals through the first and second amplification MOSFETs, and the third and fourth switch MOSFETs are turned off. To turn on the first and second switch MOSFETs, and to apply a minute potential to one of the input terminals based on the precharge voltage, and a power switch MOSF of the first conductivity type.
ET is turned on to activate the first and second amplification MOSFETs, and then the second conductivity type power switch MO is activated.
Turn on the SFET and turn on the third and fourth amplification MOSFETs.
A semiconductor integrated circuit device comprising a minute voltage amplifying circuit for performing an amplifying operation according to a third period for activating T. 2. The first and second input terminals are pre-charged to the same voltage lower than the pre-charge voltage prior to the first period. Semiconductor integrated circuit device. 3. The first and second input terminals are connected to complementary bit lines of a dynamic RAM, and the minute voltage is a read voltage from a dynamic memory cell. The semiconductor integrated circuit device according to claim 2. 4. The semiconductor integrated circuit according to claim 3, wherein the ratio of the parasitic capacitance value CB of the bit line to the capacitance value of the capacitance CS of the memory cell is set to be larger than about 20. apparatus. 5. A fifth and a sixth switch MOSFET provided between a pair of capacitive signal lines and a pair of input terminals, and one source and drain of the first and second input terminals. And fifth and sixth amplification MOSFETs whose gates are cross-connected, and the fifth and sixth amplification MOSFETs described above.
A first and second capacitance means in which one electrode is connected to the source of T and the other electrode is made common; and a power switch MOSFET for applying an activation voltage to the sources of the fifth and sixth amplification MOSFETs. A predetermined potential is applied to the other common electrode of the first and second capacitance means, the fifth and sixth switch MOSFETs are turned on, and the same precharge voltage is applied to the signal line and the input terminal. The first period of application, the second period of applying a minute voltage to one of the pair of capacitive signal lines, and the fifth and sixth switch MOSFETs in the OFF state to set the first and second The potential of the other common electrode of the capacitance means is set to 1 and the second amplification MOS.
A third period in which the level is changed to activate the FET, and the power switch MOSFET is turned on in the first period.
And activating the second amplification MOSFET and then turning on the fifth and sixth switch MOSFETs again.
2. A semiconductor integrated circuit device comprising a minute voltage amplifier circuit for performing an amplifying operation according to the period. 6. The amplifier M is provided at the first and second input terminals.
Third and fourth amplification MOSFETs of opposite conductivity type to the latch type are provided, and the fifth and fifth amplification MOSFETs are provided in the fourth period.
6. The semiconductor integrated circuit device according to claim 5, wherein the semiconductor integrated circuit device is activated at a timing delayed from the amplification operation of the sixth amplification MOSFET. 7. The capacitive signal line is a complementary bit line of a dynamic RAM, and the first and second capacitance means have the same structure as a storage capacitor of a dynamic memory cell. 7. The semiconductor integrated circuit device according to claim 6, wherein. 8. The ratio of the parasitic capacitance value CB of the bit line which is the capacitive signal line to the capacitance value of the capacitance CS of the memory cell is set to be larger than about 20. The semiconductor integrated circuit device according to claim 7.