JPH06223570A - Dynamic ram and information processing system using it - Google Patents

Abstract

(57) [Summary] (Modified) [Objective] To provide a dynamic RAM that achieves high integration and low power consumption while achieving large storage capacity, and an information processing system that achieves small size and high performance. A ratio of a parasitic capacitance value on a bit line to a capacitance value of a memory cell is increased to about 20 times or more by using a sense amplifier whose characteristic variation of paired MOSFETs is compensated. A switch MOSFET that disconnects the bit line at the center is provided, and disconnects when necessary. A plurality of memory arrays are set as one set, and switch MOSFETs that connect the common source lines to which the sense amplifiers are connected to each other are provided to mutually reuse the charges of the common source lines.

Description

Detailed Description of the Invention

[0001]

This invention relates to a dynamic RA
The present invention relates to M (random access memory) and an information processing system using the same, for example, a dynamic RAM having a large storage capacity and a technique effectively applied to an information processing system using the same.

[0002]

2. Description of the Related Art MOSF in a dynamic RAM
Regarding the sense amplifier that compensates for the variation in the ET threshold voltage, Japanese Utility Model Publication No. 56-21897 and Showa 5
There are two conferences of IEICE National Conference 2-288. In the former sense amplifier, an amplification MOSFET is connected to form a diode during a precharge period to precharge the bit line from the source side. The latter sense amplifier separates the source of the amplification MOSFET and performs the initial amplification operation by capacitive coupling.

[0003]

Dynamic type RAM
In that case, the sense amplifier is also C for low power consumption.
It is composed of a MOS circuit. With the CMOS circuit of such a sense amplifier, the precharge potential of the bit line is also set to an intermediate level of half the operating voltage. Therefore, the one that precharges the bit line with the power supply voltage as in the sense amplifier of Japanese Utility Model Laid-Open No. 56-21897 cannot be applied as it is. Also, amplification MO
Since the SFET is composed of a P-channel MOSFET and an N-channel MOSFET, there is a one-to-one correspondence between the offset voltage of the sense amplifier and the variation of the threshold voltage of the N-channel MOSFET and the P-channel MOSFET. Not only can I not do it, N
There is a problem that the precharge operation becomes difficult due to competition between the channel type side and the P channel type side.

Further, as in the sense amplifier described in National Conference of the Institute of Electronics, Communication and Communication, Japan, 1982, 2-288, it is necessary to make an extremely large capacitance value in the sense amplifier when operating the sense amplifier by capacitive coupling. Not relevant. That is, in the dynamic RAM, many memory cells are connected to one bit line in order to increase the storage capacity. Therefore, the parasitic capacitance value of the bit line becomes relatively large, and in order to increase the bit line potential to some extent by capacitive coupling, a considerably large capacitor is required. It is difficult to form such a capacitor in the sense amplifier. It is not feasible from the viewpoint of the degree of integration.

Therefore, in the present inventors, the pair M
We have developed a sense amplifier that compensates for variations in the threshold voltage of the OSFET and enables the sensing operation of a memory cell with a large storage capacity as in reality. By using such a sense amplifier, it was considered to achieve high integration and low power consumption of the dynamic RAM.

In a large-capacity dynamic RAM, power consumption is not controlled by a memory access such as read / write, but always by a short time interval so that stored information in a memory cell is not lost. The refresh operation is performed, and the operation is serial access, not random access such as read / write, and it is considered to reduce power consumption.

An object of the present invention is to provide a dynamic RAM which realizes high integration while achieving large storage capacity. Another object of the present invention is to provide a dynamic RAM which realizes a large storage capacity and low power consumption. Still another object of the present invention is to provide an information processing system that realizes a small size and high performance. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, the ratio of the parasitic capacitance value in the bit line to the capacitance value of the memory cell is increased to about 20 times or more by using the sense amplifier in which the characteristic variation of the pair MOSFET is compensated.

A switch MOSFET for disconnecting the bit line connected to the sense amplifier at the center is provided, and one of the two memory arrays forms a word line which intersects the bit line outside the sense amplifier with the switch MOSFET as the center. When selected, on the other hand, the word line that intersects the bit line on the sense amplifier side is set to the selected state.

By using a sense amplifier in which characteristic variations of paired MOSFETs are compensated, the ratio of the parasitic capacitance on the bit line to the memory cell capacitance value is increased from about 20 times to the operable range of the sense amplifier, and a plurality of memories are used. A set of arrays is provided, and switch MOSFETs that connect the common source lines to which the sense amplifiers are connected to each other are provided, and word lines are sequentially selected one by one in a plurality of memory arrays that make up one set in the refresh mode. At the same time, the switch MOSFET connecting the common source lines to each other is turned on to start the amplifying operation of the sense amplifier, and the switch MOSFET is turned off and then the amplifying operation is performed.
Turn ET on.

An information processing system is constructed using the dynamic RAM as described above as a memory device.

[0012]

According to the above means, the number of memory cells connected to the bit line can be increased and the number of sense amplifiers can be reduced, so that high integration can be achieved. The bit line capacitance is reduced by disconnecting the bit line of the non-selected word line, and the power consumption is reduced by using the charge of the common source line capacitance corresponding to the non-selected sense amplifier for the initial amplification of the sense amplifier. To be By using the highly integrated and low power consumption dynamic RAM as a memory device, it is possible to realize a small size and high performance of the information processing system.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 shows a dynamic type R according to the present invention.
A schematic circuit diagram of an essential part of one embodiment of an AM is shown. Each circuit element in the figure is formed on one semiconductor substrate such as single crystal silicon by a known CMOS (complementary MOS) integrated circuit manufacturing technique.

In the same figure, a sense amplifier according to the present invention is mainly shown and a circuit related thereto is shown. That is, two sense amplifiers, two pairs of bit lines (sometimes referred to as data lines or digit lines) connected thereto, their pre-precharge circuits and eight word lines, and these bit lines and word lines. The control circuit of the sense amplifier and the memory cell and the precharge circuit provided at the intersection of and are illustrated as a representative. Of these, the sense amplifier and the preliminary precharge circuit related to one of the complementary bit lines B1T and B1B will be described below as an example.

In this embodiment, the sense amplifier is basically of CMOS construction. A P-channel type amplification MOSFET which constitutes a CMOS sense amplifier in order to compensate an input offset in the sense amplifier having the CMOS configuration.
Q10, Q11 and N-channel type amplification MOSFET Q
N-channel type amplification MOSFET Q
Mainly composed of 4 and Q5, P-channel type amplification MOSFET
Q10 and Q11 are used supplementarily. That is, when the sense amplifier starts operating, an N channel type amplification MOS
The FETs Q4 and Q5 are activated first to perform the amplification operation,
After the amplified signal becomes large to some extent, the P-channel type amplification MOSFETs Q10 and Q11 are activated to obtain a full swing high level / low level output signal corresponding to a minute input signal.

With such a configuration, the CMO
While using the S sense amplifier, the substantial input offset of the sense amplifier and the N channel type amplification MOSFET
It is possible to make one-to-one correspondence with variations (differences) in the threshold voltage of Q4 and Q5. In order to compensate for variations in the threshold voltage of the amplification MOSFETs Q4 and Q5 that perform amplification operation predominantly after the operation of the amplification MOSFETs of the sense amplifier is separated, Switch MOSFETs Q6 and Q8 are provided between and the bit lines B1B and B1T. Amplification MOSFET Q
Switch MOSFETs Q7 and Q9 are provided between the gates of 4 and Q5 and the common source line NS. These switch MOSFETs Q6 to Q9 are not particularly limited,
It is composed of an N-channel MOSFET.

The common source line NS is provided with a power switch MOSFET Q13 for activating the amplification MOSFETs Q4 and Q5. This power switch MOSFET Q13 supplies an operating voltage such as the ground potential of the circuit to the common source line NS to amplify the amplification MO.
SFETs Q4 and Q5 are activated.

The common source line NS is used for precharging the bit lines B1T, B1B in addition to activating the amplification MOSFETs Q4, Q5 as described above. That is, the common source line NS is connected to the precharge voltage VP.
A precharge MOSFET Q12 for supplying This precharge voltage VP is 1 of the operating voltage VCC.
It is set to a voltage (VCC / 2) + VTH obtained by adding the threshold voltage VTH of the MOSFETs Q4 and Q5 to the voltage VCC / 2 of / 2.

The switch MOSFETs Q6 and Q8,
Q7 and Q9 are complementarily switch-controlled by the control signal COM. That is, the switch MOSFETs Q6 and Q
The control signal COM is supplied to the gate of 8 and the control signal COM is supplied to the gates of the switch MOSFETs Q7 and Q9.
Are inverted and supplied through the inverter circuit N2. Similarly, the power switch MOSFET Q13 and the precharge MOSFET Q12 are complementarily switch-controlled by the control signal PN. In other words, the precharge MOSFET Q12 is controlled by the inverter circuit N1 which receives the control signal PN.

On the other hand, the P-channel type amplification MOSFETs Q10 and Q11 which are preliminarily made to function are latched as in the conventional case. The common source line PS is provided with a P-channel type power switch MOSFET Q14 that supplies an operating voltage such as the power supply voltage VCC.
The control signal PP for controlling the power switch MOSFET Q14 is delayed with respect to the control signal PN supplied to the gate of the N-channel type power switch MOSFET Q13, as described later in detail. As a result, the P-channel amplifier MOSFET Q as described above is
4, Q5 and N-channel type amplification MOSFET Q10, Q
Separation in the amplification operation of 11 is performed.

Between the complementary bit lines B1T and B1B, a preliminary precharge circuit including a short-circuit MOSFET Q1 and MOSFETs Q2 and Q3 for supplying a preliminary precharge voltage VCC / 3 is provided. The operation of the preliminary precharge circuit is basically the same as the operation of the conventional half precharge circuit, but the voltage level thereof changes from the half precharge voltage VCC / 2 by the short-circuit MOSFET Q1 to the ON state of the MOSFETs Q2 and Q3. Is different from the operation of the conventional circuit in that it is lowered to a potential such as VCC / 3.

The memory cell is provided between the word line and one bit line B1T or B1B. In the MOSFET QM for address selection, the gate is connected to the word line and one of the source and drain is the bit line B1T or B0.
Connected to T. A capacitor C for storing information is provided between the other source and drain and the plate voltage VPL.
S is provided. The arrangement of such memory cells is similar to that of the conventional dynamic RAM, and therefore detailed description thereof will be omitted. As for the word line, one word line selected by the word line selection circuit is brought into a selected state.

The complementary bit lines B0T and B0B and the related pre-precharge circuit, sense amplifier and sense amplifier control circuit and precharge circuit which are shown as other representatives are the same as the circuits described above. It is omitted. Correspondingly, circuit symbols for elements are omitted in the drawings.

FIG. 4 is a timing chart for explaining the operation of the sense amplifier shown in FIG. Signal P
The preliminary precharge operation is performed while C is at the high level. That is, when the control signal PC is high level, the MOS
The FETs Q1, Q2 and Q3 are turned on, and the complementary bit line BL is set to the pre-precharge voltage such as VCC / 3.

The signal PC is set to the low level to set the MOSF.
ETQ1 to Q3 are turned off, and the complementary bit line BL is set to a high impedance state. As a result, the complementary bit lines BL (B1T, B1B) hold the voltage VCC / 3 in the high impedance state.

When the control signal COM is set to the low level, the switch MOSFETs Q6 and Q8 are turned off and the switch MOSFETs Q7 and Q9 are turned on. As a result, N-channel type amplification MOSFETs Q4 and Q5
Since the gate and common source side of
SFETs Q4 and Q5 are in diode form. As a result, the precharge voltage VP supplied from the common source line NS becomes the diode-type amplification MOSF.
It is transmitted to bit lines B1T and B1B through ETQ4 and Q5. At this time, if the threshold voltage of the amplification MOSFET Q5 is larger than that of the amplification MOSFET Q4, a level difference occurs between the bit lines B1T and B1B by the threshold voltage difference ΔVTH.

Since the bit lines B1T and B1B are pre-charged to VCC / 3 as described above, the level difference is small even if the bit lines B1T and B1B have a relatively large parasitic capacitance CB. The amplification MOSFE
Through TQ4 and Q5, the precharge level corresponding to approximately VCC / 2 can be changed at high speed. As described above, in order to set the precharge voltage of the bit lines B1T and B1B to approximately the half precharge voltage VCC / 2, the precharge voltage VP of the common source line NS is set to VCC / 2, M
In order to compensate for the level drop due to the threshold voltage VTH of the OSFETs Q4 and Q5, the corresponding voltage is raised to the added voltage.

The control signal COM is returned to the high level, the MOSFETs Q7 and Q9 are turned off, and the MOSFETs are turned off.
Amplification MOSFETs Q4 and Q with Q6 and Q8 turned on
When the word line WL is set to a selected state by setting 5 as a latch mode, the bit line to which the memory cell is connected has the accumulated charge of the capacitor CS of the memory cell and the precharge charge of the parasitic capacitance CB of the bit line. A minute potential change appears due to charge dispersion. This is the amplification MOSFET Q4 of the sense amplifier as the minute read signal VSIG from the memory cell.
Is transmitted to the gate of Q5 as a potential difference.

In this embodiment, since the offset voltage ΔVTH corresponding to the threshold voltages of the amplification MOSFETs Q4 and Q5 is applied to the bit line in advance by the precharge operation as described above, the read signal VSIG is directly amplified. It is given as a gate voltage difference to MOSFETs Q4 and Q5. In this state, the control signal PN is set to the high level and the amplification MOSFETs Q4 and Q5 are activated. This enables N-channel amplification MOSFET
Only Q4 and Q5 start the amplifying operation of the minute signal VSIG.

The N-channel type amplification MOSFET Q4
By the amplification operation of Q5 and Q5, the control signal PP is delayed to a low level when the amplified signal becomes large to some extent. As a result, the P-channel amplification MOSFET Q
10 and Q11 are activated, N channel type amplification MO
An amplification operation is performed together with the SFETs Q4 and Q5 to fully swing the potential of the bit line between a high level such as VCC and a low level such as 0V.

The P-channel type amplification MOSFET Q1
0 and Q11 also have offset voltages corresponding to the threshold voltage. However, at the time when it starts the amplifying operation, the input voltage difference becomes so large that such offset voltage can be ignored, so that it can be substantially not affected by the offset. That is, the P-channel type amplification MOSFETs Q10 and Q11 prevent the drop of the potential of the bit line that should be set to the high level by the amplification operation by the N-channel type amplification MOSFETs Q4 and Q5, and pull up it to the power supply voltage VCC, so to speak. It is responsible for the general amplification operation.

After the memory access is completed, the word line WL
Is reset and the control signals PN and PP for activating the sense amplifier are also reset, and then the control signal PC is set to a high level, the MOSFETs Q1 to Q3 are turned on, and the complementary bit line is turned on by turning on the MOSFET Q1. The high level and the low level of B1T and B1B are short-circuited, and it is about to become VCC / 2.
And the ON state of Q3 changes the pre-precharge voltage VCC / 3 which is slightly lower than that.

FIG. 3 shows a circuit diagram of a main part of another embodiment of the dynamic RAM to which the present invention is applied. In this embodiment, of the CMOS sense amplifiers, P
The channel type amplification MOSFET is dominantly used, and the N channel type amplification MOSFET is auxiliary used. That is, a P-channel type MOSFET and an N-channel type MOS constituting the sense amplifier of the circuit of FIG.
It has a configuration in which the FET is replaced. Therefore, among the circuit elements constituting the sense amplifier, the circuit symbol is the same and the N-channel MOSFET is the P-channel MOS.
The FET is replaced by the FET, and the P-channel MOSFET is replaced by the N-channel MOSFET.

As described above, the P-channel type amplification MOSF
When ETQ4 and Q5 are predominantly used, the precharge voltage VP is lowered to VCC / 2-VTH.
On the other hand, the spare precharge voltage of the bit line is
Raised as high as 2VCC / 3. This is because when the P-channel type amplifying MOSFET is dominantly used, the operating voltage is on the 0 V side, and the respective levels must be reversed correspondingly.

In the circuit diagrams of FIGS. 2 and 3,
Although it is shown that the P-channel type power switch MOSFET and the N-channel power switch MOSFET are provided on one side of the sense amplifier row, these MO
Since it is necessary to form the SFET relatively large, it is laid out above and below the sense amplifier row on the semiconductor substrate.

FIG. 5 is a timing chart for explaining the operation of the sense amplifier shown in FIG. Although it is basically the same as that in FIG. 4, the precharge voltage and the like are set to be different corresponding to the above-mentioned operating voltage.

In addition, the read signal VS from the memory cell
When IG is at a level opposite to the offset voltage ΔVTH, it is apparently not present on the bit lines B1T and B1B, but the read voltage VSIG shown by the dotted line in the figure is present between the gate voltages of the amplification MOSFETs Q4 and Q5. It is applied, and accordingly, the bit lines B1T and B1B are amplified to a high level and a low level.

FIG. 6 shows a circuit diagram of a main part of another embodiment of the dynamic RAM to which the present invention is applied. The circuit symbols of the circuit elements in the figure are the same as those in FIG. 2 and FIG. 3, but it should be understood that each basically has a separate circuit function. This also applies to other circuit diagrams.

In this embodiment, of the CMOS sense amplifiers, the N-channel type amplification MOSFET is predominantly used,
The P-channel type amplification MOSFET is used auxiliary. As a result, the threshold voltage difference between the N-channel type amplification MOSFETs Q4 and Q5 which operates dominantly corresponds to the substantial input offset of the sense amplifier, and the capacitive coupling is used as the compensation method.

At the sources of the amplification MOSFETs Q4 and Q5 whose gates and drains are cross-connected, capacitors shown in the form of MOS capacitors are provided. That is, MO
The drains and sources of the SFETs Q6 and Q7 are connected to each other and connected to the sources of the amplification MOSFETs Q4 and Q5 as one electrode. MOS that acts as a capacitor
The gates of the FETs Q6 and Q7 serve as the other electrode of the capacitor and are supplied with the control signal COM.

The sources of the amplification MOSFETs Q4 and Q5 are provided with MOSFETs Q8 and Q9 which operate as power switches. These MOSFETs Q8 and Q9
Also acts to isolate the sources of the amplification MOSFETs Q4 and Q5.

P-channel amplifier MOSFETs Q10 and Q11, which are preliminarily operated, are latched. Preliminarily functioning P-channel amplification MOS
FET Q10 and Q11 are N-channel type amplification MOSF
Unlike ETQ4 and Q5, the source is common source line PS
Connected to. The common source line PS is provided with a P-channel type power switch MOSFET Q12 that supplies an operating voltage such as the power supply voltage VCC. Control signal P for controlling this power switch MOSFET Q12
As will be described in detail later, P is delayed with respect to the control signal PN supplied to the N-channel type power switch MOSFETs Q8 and Q9. As a result, the P-channel amplification MOSFETs Q4 and Q5 and the N-channel amplification MOSFETs Q10 and Q11 are separated in amplification operation as described above.

The input / output node of the above sense amplifier is connected to complementary bit lines B1T and B1B via switch MOSFETs Q13 and Q14. These switches MO
The control signal BS is supplied to the gates of the SFETs Q13 and Q14.

The complementary bit lines B1T and B1B have MOSs
A precharge circuit including FETs Q1 to Q3 is provided. This precharge circuit has the same circuit configuration as the preliminary precharge circuit of FIGS. 2 and 3, but is different in that a half precharge voltage such as VCC / 2 is used. Other configurations such as memory cells, word lines and word line selection circuits
Since it is the same as FIG. 2 and FIG. 3, the description thereof will be omitted.

FIG. 8 is a timing chart for explaining the operation of the sense amplifier shown in FIG. Signal P
The precharge operation is performed while C is at the high level.
That is, the high level of the control signal PC causes the MOSFE
TQ1, Q2, and Q3 are turned on, and the complementary bit line BL is set to a precharge voltage such as VCC / 2. This voltage VCC / 2 is used for amplifying MOSFETs Q4 and Q4.
Since they are supplied to the gate and drain of No. 5, the source potential of each of them is lowered by the threshold voltage VTH. This potential acts as a capacitor M
It is stored in the MOS capacitors of the OSFETs Q6 and Q7.

The signal PC is set to the low level to set the MOSF.
ETQ1 to Q3 are turned off, and the complementary bit line BL is set to a high impedance state. As a result, the complementary bit lines BL (B1T, B1B) hold the voltage VCC / 2 in the high impedance state. Also, amplification MO
Voltages corresponding to the respective threshold voltages VTH are held between the gates and sources of the SFETs Q4 and Q5.

When the word line WL is selected, a minute potential change is caused in the bit line connected to the memory cell due to charge dispersion between the accumulated charge of the capacitor CS of the memory cell and the precharge charge of the parasitic capacitance CB of the bit line. Appears. This is transmitted as a minute read signal VSIG from the memory cell to the gates of the amplification MOSFETs Q4 and Q5 of the sense amplifier as a potential difference.

That is, as described above, the amplification MOSFET
A bias voltage corresponding to each threshold voltage is applied between the gate and the source of the MOSFET by the bit line potential and the holding voltages of the MOSFETs Q6 and Q7 acting as capacitors. Therefore, the potential difference between the bit lines B1T and B0B is supplied as a difference voltage between the gates of the amplification MOSFETs Q4 and Q5 regardless of the difference in threshold voltage as described above.

When the difference voltage according to the read signal as described above is applied to the gates of the amplification MOSFETs Q4 and Q5, the control signal BS is set to the low level and the switch MOSFET Q is turned on.
13 and Q14 are turned off. As a result, the bit lines B1T and B1 having a sense amplifier and a large parasitic capacitance CB are provided.
1B is cut off.

When the control signal COM is set to a low level, the source potentials of the amplifying MOSFETs Q4 and Q5 are lowered and activated with a voltage difference corresponding to the threshold voltage difference due to capacitive coupling by the gate capacitances of the capacitors Q6 and Q7. Turn into At this time, the sense amplifier operates as the bit line B1.
Since it is separated from T and B0B, the parasitic capacitance on the input side can be reduced to a level almost equal to the gate capacitance values of the MOSFETs Q6 and Q7, etc. Therefore, the amplification MOSFETs Q4 and Q5 form a pair of input terminals by the capacitive coupling as described above. Increase the potential difference of.

After this, the signal PN is set to the high level and N
Channel side power switch MOSFETs Q8 and Q9
Turn on to start full-scale amplification operation. At the same time, the signal PP is set to low level (not shown),
The power switch MOSFET Q12 on the P-channel side is turned on, and the amplification MOSFET Q on the P-channel side is turned on.
Activates 10 and Q11.

The P-channel type amplification MOSFET Q1
0 and Q11 also have offset voltages corresponding to the threshold voltage. However, at the time when it starts the amplifying operation, the input voltage difference becomes so large that such offset voltage can be ignored, so that it can be substantially not affected by the offset. That is, the P-channel type amplification MOSFETs Q10 and Q11 prevent the potential of the bit line from dropping to a high level due to the amplification operation by the capacitive coupling of the N-channel type amplification MOSFETs Q4 and Q5 and prevent it from dropping to the power supply voltage VC.
It is so-called a complementary amplifying operation of pulling up to C.

Power switch MOSFET as described above
After turning on, the signal BS is set to the high level to turn on the switch MOSFETs Q13 and Q14. As a result, the bit line B1 having a large parasitic capacitance
Since T and B1B are connected to the sense amplifier, the signal becomes small, but the potential of the bit line is expanded to a high level such as the power supply voltage VCC and a low level such as the ground potential of the circuit by the amplifying operation. .

After the memory access is completed, the word line WL
Is reset and the control signals PN and PP for activating the sense amplifier are also reset, and then the control signal PC is set to a high level, the MOSFETs Q1 to Q3 are turned on, and the complementary bit line is turned on by turning on the MOSFET Q1. The high level and low level of B1T and B1B are short-circuited, and a precharge voltage such as VCC / 2 is obtained.

FIG. 7 shows a circuit diagram of a main part of still another embodiment of the dynamic RAM to which the present invention is applied. In this embodiment, of the CMOS sense amplifiers, the P-channel type amplification MOSFET is predominantly used,
The N-channel type amplification MOSFET is used auxiliary. That is, the P-channel type MOSFET and the N-channel type M which constitute the sense amplifier of the circuit of FIG.
It has a configuration in which the OSFET is replaced. Therefore,
Of the circuit elements forming the sense amplifier, the N-channel MOSFET is a P-channel M without changing the circuit symbol.
Replaced by OSFET, P-channel type MOSFE
T has been replaced by an N-channel MOSFET.

FIG. 9 is a timing chart for explaining the operation of the sense amplifier shown in FIG. Basically the same as in FIG. 8, but with P-channel amplification MOSF
In response to the operating voltage VCC of ET, the signal COM is changed to the high level contrary to FIG. The other basic structure is the same as that of the above-mentioned embodiment, and therefore its explanation is omitted.

FIG. 25 is a sectional view showing the element structure of one embodiment of the dynamic memory cell. Reference numeral 46 is a word line, which is composed of a polysilicon layer. 48
Is a storage electrode forming the capacitor CS, 54 is an insulating film, and acts as a dielectric of the capacitor CS.
A plate electrode 49 is supplied with the plate voltage VPL as described above. Reference numeral 50 is a bit line, which is made of polycide. Reference numeral 52 is an aluminum layer for the word line shunt.

The structure of the memory cell is a laminated type. 54
Usually Although SiO ₂ or Si ₃ N ₄ or the like is used, the bit line capacitance CB by connecting a large number of memory cells to reduce the size of the capacitor CS or, or one of the bit lines for high integration In order to increase the read voltage, which decreases relatively due to the increase,
A high dielectric film such as Ta ₂ O ₃ may be used so as to increase the capacitance value of. When such a high dielectric film is used, the structure of the memory cell can be simple.

Although not particularly limited, the amplifying MOS shown in FIG.
The capacitor that causes the FETs Q4 and Q5 to perform an initial operation by capacitive coupling is a capacitor CS that constitutes a memory cell.
Use the same structure as. In this case, the amplification MOSFETs Q4 and Q5 can have the same structure as the address selection MOSFET QM that constitutes the memory cell. However, the size may be larger than that of the memory cell in order to increase the amplification gain.

As described above, M having the same structure as the memory cell
Amplification MOS using OSFET QM and capacitor CS
A MOSFET for power switch or separation by configuring a FET Q4 and a capacitor provided at the source
By adding a MOSFET corresponding to Q8, the sense amplifier can be built relatively easily according to the bit line pitch. In this case, when a high dielectric film is used for the capacitor, a large capacitance value can be obtained, so that a large amplified signal can be obtained by capacitive coupling of the sense amplifier.

FIG. 1 shows a chip layout diagram of an embodiment of a dynamic RAM using a sense amplifier according to the present invention. In this embodiment, it has a storage capacity of about 16 Mbits.

The memory array is divided into 8 blocks of about 2 Mbits each. Sense amplifier SA is 2
It is arranged in the middle part of one block and consists of 8192 pieces in total. Row decoder RD and word driver WD
Are arranged in a direction perpendicular to the sense amplifier row so as to be sandwiched between two pairs of blocks. A column decoder CD or a column decoder CD is provided at the center of the chip in the vertical direction.
And two data registers DR are arranged.

In one block, the sense amplifier S
The number NSA of memory cells connected to A is set to 1024 per bit line. The number NWD of memory cells connected to the word line is set to 2048 per one.

When as many as 1024 memory cells are connected to one bit line as described above, the bit line capacitance CB increases. On the other hand, since the size of the memory cell cannot be increased in terms of the degree of integration, the amount of signals read to the bit line can be reduced.

Paired MOSFETs forming a sense amplifier
The variation of the threshold voltage is generally about 50 mV. Therefore, it is necessary to secure at least about 100 mV as the signal voltage read to the bit line. For this reason, when the conventional sense amplifier is used, as shown in FIG.
As described above, the number of memory cells connected to one bit line is 256 at most. Similarly, the number of memory cells connected to one word line is about 1024. As a result, the ratio of the sense amplifier SA occupying the semiconductor chip is increased as indicated by hatching in the figure, which is a cause of hindering the downsizing of the chip size or the high integration degree.

On the other hand, as in the present invention, the MOSF
In the sense amplifier that compensates for the variation in the ET threshold voltage, in other words, in the sense amplifier that compensates for the input offset, the signal amount of the bit line may be about 50 mV if the same operation margin as in the conventional case is obtained. Therefore, CB / CS, which is the ratio of the capacitance value CS of the memory cell to the parasitic capacitance value CB of the bit line, must be set to about 10 in the past, but by using a sense amplifier like the present application, it is 20 or more. It can be greatly increased.

When CB / CS = 20, the read signal amount when the bit line potential is 3V is as shown in the following equation (1). 3V × 1 / (20 + 1) × 1/2 = 71 mV (1) Similarly, about 2.5 mV is about 60 mV, and 2 V is 48 m.
A signal amount of 36 mV is obtained at V and 1.5 V,
It can be seen that up to 2.5 V can be read without sacrificing the operating speed compared with the conventional circuit.

By the input offset compensation of the sense amplifier as described above, the number of memory cells connected to one bit line is increased like 1024 and the number of memory cells connected to the word line is also increased. As a result, the semiconductor chip of FIG. 1 has about the same storage capacity and about the same performance as the semiconductor chip of FIG.
It can be reduced to about%. That is, in the dynamic RAM of about 16 Mbits as shown in FIG. 1, the memory cell occupation rate can be increased to 80% or more, whereas in the dynamic RAM of FIG. 10, the memory cell occupation rate is only about 50%. It will not happen.

Further, the layout of FIG.
Bit dynamic RAM can also be made. In this case, the NSA may be left unchanged and the number of NWD may be increased to 4096. At this time, if the occupation rate of the memory cell is 80%, the dynamic type R of about 16 Mbits of the configuration of FIG.
A dynamic RAM having a double storage capacity can be obtained only by increasing the chip area by about 25% with respect to AM.

In the dynamic type RAM having a large storage capacity of about 64 Mbits or more, when the conventional technique is used, the memory cell occupation rate tends to be further reduced. At this time,
A dynamic RAM of about 64 Mbits having a memory cell occupation rate of 45% and a memory cell occupation rate of 9 using the present invention.
Approximately 128 Mbit dynamic RA that achieved 0%
M can have the same design rule and the same chip area.

FIG. 11 is a circuit diagram of a main part of another embodiment of the dynamic RAM according to the present invention.
In this embodiment, a sense amplifier that compensates for variations in the threshold voltage of the paired MOSFETs as in the embodiment of FIG. 2 or 3 is used to increase the speed and stabilize the operation.

In the figure, one sense amplifier, a pair of complementary bit lines connected to it, and one memory cell connected to each bit line are shown as a representative example. In this embodiment, switch MOSFETs Q3 and Q4 are provided between the input / output nodes BST and BSB of the sense amplifier and the complementary bit lines BT and BB. A control signal SC is supplied to the gates of these switch MOSFETs Q3 and Q4. The sense amplifier starts its amplifying operation by the P-channel type power switch MOSFET Q1 and the N-channel type power switch MOSFET Q2. These power switch MOSFETQ
Control signals PP and PN are supplied to the gates of 1 and Q2.

Paired MOS as in the embodiment of FIG. 2 or FIG.
It is to be understood that the precharge circuit and the spare precharge circuit for compensating the variation in the threshold voltage of the FET and the control signals and timing signals necessary for the operation thereof are included in the sense amplifier.

FIG. 12 is a timing chart for explaining the operation of the sense amplifier shown in FIG. In the state where the control signal PC is at the high level, in other words, in the state where the sense amplifier and the complementary bits BT and BB are connected, the precharge operation is performed by a spare precharge circuit or the like not shown. .

The word line is set to the high level selected state, and the switch M of the memory cell connected to the selected word line is selected.
Since the OSFET QM is turned on, a minute voltage corresponding to the charge coupling between the charge accumulated in the memory cell capacitor CS and the precharge charge of the bit line appears on the selected bit line.

When such a minute read signal is taken into the set at the input / output nodes BST and BSB of the sense amplifier, the control signal SC is set to low level and the switch MO is switched.
SFETs Q3 and Q4 are turned off. In this state, the control signal PP of the sense amplifier is set to the low level and PN is set to the high level to start the amplification operation. At this time, the parasitic capacitance of the input / output nodes BST and BSB of the sense amplifier is
Since it is made small, the minute signal is rapidly expanded to the high level and the low level.

After the input / output nodes BST and BSB are expanded to the high level and the low level, the control signal SC is set to the high level and is coupled to the bit lines BT and BB again. Bit lines BT and B having such a large parasitic capacitance
When B is connected to the sense amplifier again, its input / output nodes BST and BSB try to return to the original state again, but due to the amplification operation of the sense amplifier, the bit lines BT and B
Expanded to high level / low level with B.

By performing such an amplifying operation, when the sense amplifier amplifies a minute read signal, the influence of noise generated on the bit lines BT and BB and the parasitic between the bit lines BT and BB are provided. The input / output nodes BST and BSB having only a small parasitic capacitance can be amplified at high speed without being affected by the capacitance imbalance.

As a result, by compensating for the variations in the threshold voltage of the pair elements as described above, it is possible to compensate for the decrease in the signal amount when the number of memory cells connected to the bit line is increased. , While ensuring operating margin 1
The number of memory cells connected to one bit line can be further increased.

FIG. 13 shows a schematic chip layout diagram of another embodiment of the dynamic RAM according to the present invention. In this example, the memory array is divided into four blocks. The sense amplifier is arranged in the vertical center of each memory array. Although not particularly limited, complementary bit lines are arranged on the left and right with the sense amplifier as the center.
That is, the folded bit line system in which the complementary bit lines are arranged in a folded manner with respect to the sense amplifier is not adopted. The bit line is a cut MOS that enables cutting at the center
An FET is provided.

Although not particularly limited, the word line is selected by the row decoder RD provided in the center of the chip.
A word line is formed long by connecting a large number of memory cells such as 2048 to one word line.
In addition, since the pitch between the word lines is short, the parasitic capacitance between the word line lines is increased. This prevents the unselected word lines from floating due to the coupling with the selected word line arranged adjacent to each other.
A word clear circuit for speeding up the floating and resetting the word line as described above is provided at three locations where the same is done.

Further, regions for word line shunts for reducing the resistance of the word lines are provided at a total of 7 places including the word clear circuit, which divides the word line into eight equal parts. That is, the dedicated area of the word line shunt is shown by four lines extending in the horizontal direction per one memory array.

In this embodiment, in order to reduce the power consumption,
When only one memory array is selected in normal memory access, when the word line is selected outside the cut MOSFET with reference to the sense amplifier, the cut MOSFET is turned on and When the word line of is selected, cut M
Turn off the OSFET. As a result, the parasitic capacitance value of the bit line can be reduced to about half, so that the charge-up current and the discharge current when the sense amplifier performs the amplifying operation can be reduced.

In the refresh mode, in order to shorten the number of refresh cycles, in other words, it is necessary to bring a plurality of word lines into a selected state. In this case, the number of operating sense amplifiers increases.
Therefore, the current consumption of the dynamic RAM depends on the current consumption in the refresh mode. Therefore, in the dynamic RAM provided with the cut MOSFET as described above, when the word lines of two memory arrays are simultaneously selected in the refresh mode, the following address allocation is performed.

In FIG. 13, when the two memory arrays on the left half of the semiconductor chip are simultaneously refreshed, the upper memory array of FIG.
Cut MO based on the sense amplifier as shown in 4 (A)
When the word line outside the SFET is set to the selected state, the word line inside the cut MOSFET is set to the selected state based on the sense amplifier in the lower memory array as shown in FIG. 14B. . On the contrary, when the word line inside the cut MOSFET is selected in the upper memory array, the word line outside the cut MOSFET is selected in the lower memory array. This is the same when the refresh operation is performed in the two memory arrays on the right half.

Then, as shown in FIGS. 14A and 14B, the word line outside the cut MOSFET is selected in the upper memory array, and the word line inside the cut MOSFET is selected in the lower memory array. When the state is set, the cut MOSFET of the upper memory array is kept in the on state, and the cut MOSFET of the lower memory array is turned off. As a result, in the lower memory array, the current consumption of the sense amplifier can be reduced to almost half. As a result, the operating current during refresh can be reduced to 3/4. The cut MOSFET is
Besides dividing the bit line in half, the bit line may be divided into a large number such as by dividing the bit line into four equal parts. As a result, the power consumption can be further reduced by disconnecting the bit line outside the selected word line.

FIG. 14C shows a timing chart in the refresh mode. When the RASB is changed to the low level, the refresh address stepping operation is performed (CAS follower RAS refresh). Then, as shown in FIGS. 9A and 9B, the control signal CU of the upper memory array is maintained at the high level, and the control signal CL of the lower memory array is set to the low level, and then the word line WL. Selection operation is performed. As a result, the sense amplifier starts an amplifying operation by an activation signal of a sense amplifier (not shown), a read operation of the selected memory cell, and a refresh operation of rewriting the original memory cell by amplifying the read signal. The action is taken.

FIG. 15 is a schematic circuit diagram of another embodiment of the dynamic RAM according to the present invention.
In this embodiment, in the refresh mode of the dynamic RAM, it is noted that the memory cell selection operations are performed in a fixed order. In other words, read / write operations are performed.
Even though the write mode is random access, the refresh operation is performed as serial access to reduce the power consumption of the sense amplifier.

In this embodiment, two memory blocks (memory arrays) will be described to facilitate understanding of the invention. The common source lines PS1 and NS1 of the sense amplifier of the block 1 are provided with power switch MOSFETs including P-channel MOSFETs and N-channel MOSFETs controlled by the control signals PP1 and PN1. Similarly, the control signals PP2 and PN2 are applied to the common source lines PS2 and NS2 of the sense amplifier of the block 2.
Power switch MOSF consisting of P-channel type MOSFET and N-channel type MOSFET controlled by
ET is provided.

The sense amplifier is C for simplification of description.
Although shown by a MOS latch circuit, in the present invention,
When the number of memory cells connected to the bit line is increased, the amount of signal on the bit line is reduced, or the bit line high level voltage as described later, in other words, the operating voltage of the sense amplifier. Since the signal amount is reduced by decreasing the value of M, the pair M as in the above embodiment is
An OSFET provided with a function of compensating for variations in threshold voltage is used.

The common source lines PS1 and NS1 and PS2 and NS2 have complementary bits BL of the memory array.
A precharge circuit similar to the precharge circuit provided in T and BLB is provided. A half precharge voltage VCC / 2 is supplied to the precharge circuit.
Precharge signals PC1 and PC2 corresponding to the blocks 1 and 2 are supplied to these precharge circuits.

In this embodiment, the common source lines PS1 and PS2 and NS1 and NS2 of the above two memory blocks are used.
A switch MOSFET including a P-channel MOSFET QP and an N-channel MOSFET QN is provided between them. The gates of these switch MOSFETs QP and QN have control signals SCPB and SC formed based on the address signal formed by the refresh control circuit.
PT is supplied.

FIG. 16 is a timing chart for explaining the refresh operation of the dynamic RAM shown in FIG. Column address strobe signal CA
When the SB is set to the low level before the row address strobe signal RASB, the refresh mode (C
BR refresh mode).

The address stepping operation is performed by the low level of the RASB signal, and before the refresh operation is performed on the block 1, the precharge signal PC1 is set to the low level and the MOSFET of the precharge circuit is turned off. As a result, on the block 1 side, the complementary bit lines BLT and BLB of the memory array and the common source lines PS1 and PN1 of the sense amplifier are set to a high impedance state.

X decoder XDEC corresponding to block 1
When the word line driver DRIV selects one word line WL, the stored information from the selected memory cell is read to the bit lines BLT and BLB. Then, the sense amplifier corresponding to the block 1 is activated by the signals PP1 and PN1, and the complementary bit line BL is
The minute signal read between T and BLB is amplified and expanded to a high level / low level.

In the memory cell, the memory charges that are about to be lost by the above read operation are expanded by the amplifying operation of the sense amplifier, and the bit lines BLT and BLB are expanded.
Is rewritten to the high level or the low level, and the refresh operation is performed.

Even if the refresh operation is completed in the block 1 as described above, the precharge signal PC1 is kept at the low level. When the RASB signal is reset to the high level and then set to the low level again, the address advance operation is performed and the precharge signal PC2 on the block 2 side is set to the low level before the refresh operation is performed on the block 2 in place of the block 1. To be This allows
On the block 2 side, the complementary bit line BLT of the memory array
And BLB and common source lines PS2 and P of the sense amplifier
N2 is brought to a high impedance state.

X decoder XDEC corresponding to block 2
When the word line driver DRIV selects one word line WL, the stored information from the selected memory cell is read to the bit lines BLT and BLB. Then, before the sense amplifier corresponding to the block 1 is activated by the signals PP1 and PN1, the control signal SCPB is set to the low level, the SCPT is set to the high level, the switch MOSFETs QP and QN are turned on, and the common source line is turned on. PS1 and PS2 and NS1 and NS2 are short-circuited.

Since the common source lines PS1 and NS1 are in the high impedance state while holding the high level and the low level in the previous refresh operation, the operating current flows in the sense amplifier on the block 2 side due to the above short circuit. The initial amplification operation is performed. After that, the signal signal SCPB is returned to the high level and the SCPT is returned to the low level to turn off the switch MOSFETs QP and QN, and then the sense amplifier corresponding to the block 2 is activated by the signals PP2 and PN2, and the amplification is performed. The potential of the bit line intermediately expanded by the operation is finally set to the high level and the low level.

Similarly to the above, even if the refresh operation is completed in the block 2, the precharge signal PC2 is kept at the low level. When the RASB signal is reset to the high level and then set to the low level again, the address advance operation is performed and the precharge signal PC2 on the block 1 side is temporarily changed before the refresh operation is performed on the block 1 in place of the block 2. The common source lines PS1 and NS1 complementary to the complementary bit lines BLB and BLT are half-precharged. After completion of this precharge, the signal PC1 is set to the low level. As a result, on the block 1 side, the complementary bit line B of the memory array is
Common source line PS2 for LT and BLB and sense amplifier
And NS2 maintain the precharge potential in the high impedance state. In this precharge operation, the intermediate high level and the low level formed by the connection with the common source lines PS2 and NS2 as described above are short-circuited, so that a half precharge like VCC / 2 is made. It

X decoder XDEC corresponding to block 1
When the word line driver DRIV selects one word line WL, the stored information from the selected memory cell is read to the bit lines BLT and BLB. Then, before the sense amplifier corresponding to the block 1 is activated by the signals PP1 and PN1, the control signal SCP is again generated.
B is set to the low level, SCPT is set to the high level, the switch MOSFETs QP and QN are turned on, and the common source lines PS1 and PS2 and NS1 and NS2 are short-circuited.

Since the common source lines PS2 and NS2 are brought to the high impedance state while holding the high level and the low level in the refresh operation before the block 2, the operating current is supplied to the sense amplifier on the block 1 side by the above short circuit. And the initial amplification operation is performed. After that, the signal signal SCPB is returned to the high level and the SCPT is returned to the low level to turn off the switch MOSFETs QP and QN, and then the sense amplifier corresponding to the block 2 is activated by the signals PP1 and PN1 and the amplification is performed. The potential of the bit line intermediately expanded by the operation is finally set to the high level and the low level.

Similarly, by alternately refreshing the block 1 and the block 2, the sense amplifier corresponding to the refresh address immediately before is added to a part of the amplified current of the sense amplifier except the start address of the refresh cycle. By using the charge accumulated in the common source line of, the current consumption of the sense amplifier can be reduced to about half.

In this embodiment, the refresh operation is alternately performed by using the two memory blocks, but the present invention is not limited to this. For example, when the memory array is divided into four as shown in FIG. The refresh addresses may be sequentially rotated among the four memory arrays, and the common source lines may be connected to each other. In this case, the charge amount (current amount) that can be used for the initial amplification operation of the refreshed sense amplifier can be increased, so that the sense amplifier current can be further reduced.

The embodiments of FIGS. 13 and 15 may be carried out simultaneously. That is, in FIG.
13 is applied to two memory arrays which are vertically divided among the memory arrays which are divided into four in FIG.
The example of is applied. That is, when refreshing the two memory arrays in the left half at the same time, the refresh current is reduced by controlling the cut MOSFET of the bit line, and when refreshing the two memory arrays in the right half at the same time, the common source line The operating current of the sense amplifier on the right side, which attempts to start the amplification operation due to a short circuit, uses the charge on the common source line of the sense amplifier on the left side. At this time, in the right half memory array, one of the upper and lower memory arrays is a cut MOS
The FET reduces the bit line capacitance by half.

Then, again in the two memory arrays on the left half, the bit line capacitance by the cut MOSFET is halved,
The charge of the common source line of the right-side sense amplifier is used as the operating current of the left-side sense amplifier for starting the amplification operation due to the short-circuit of the common source line. Less than,
By repeating similar operations, the refresh current can be greatly reduced.

FIG. 17 is a schematic block diagram showing another embodiment of the dynamic RAM according to the present invention. In this embodiment, as the sense amplifier included in the memory array, one that compensates for the characteristic variation of the threshold voltage of the pair MOSFET as shown in FIG. Focusing on the fact that the signal amount may be small in the sense amplifier with such high sensitivity, in this embodiment,
As described above, it is used for increasing the storage capacity and reducing the power consumption.

As described above, when the high level supplied to the bit potential decreases to 2.5 V, the amount of charge stored in the capacitor decreases accordingly, and the amount of read signal also decreases. However, from the viewpoint of power consumption, the charge-up current and the discharge current are reduced as the signal amplitude of the bit potential is reduced, so that the power consumption can be reduced.

Therefore, in this embodiment, the dynamic RAM is divided into a memory array and a peripheral circuit such as an address selection circuit, and the power supply voltage VCC supplied from the outside is directly supplied to the peripheral circuit, and the memory array is supplied to the memory array. The power supply voltage VDL is reduced by the power supply voltage down circuit.
For example, the power supply voltage VC supplied from the external terminal VCCE
When C is a voltage such as 5V, a reduced voltage VDL of about 3V to 2.5V is used for the memory array. In addition, the power supply voltage V supplied from the external terminal VCCE
When CC is a low voltage such as 3V, a reduced voltage VDL of about 2V to 1.5V is used for the memory array.

FIG. 18 shows a characteristic diagram of the power supply voltage down circuit. The power supply step-down circuit is set to a constant voltage when the power supply voltage VCCE supplied from the outside changes, and is set to a constant voltage when the power supply voltage VCCE is higher than the constant voltage. A normal operation area is set in the constant voltage area.

The reason why the characteristic is such that the step-down voltage VDL also rises with the rise of the power supply voltage VCCE as described above is that stress is applied to the memory array portion to perform an aging or burn-in test for removing an initial defect. It corresponds.

FIG. 19 shows a circuit diagram of an embodiment of the power supply voltage down circuit. The voltage VREF is a reference voltage and is output as the difference between the threshold voltages VTH of the two P-channel MOSFETs a and b. Reference voltage VREF
Is set to a substantially constant constant voltage regardless of the power supply voltage VCCE.

The voltage VL is a reference voltage obtained by amplifying the reference voltage VREF by an amplification circuit by a constant factor to obtain a voltage value corresponding to a desired array voltage. Even if the reference voltage VREF fluctuates due to process variations, fuse means F1 to F4 are provided in order to set the reference voltage VL to a desired voltage value. By appropriately cutting the fuse means F1 to F4, a trimming circuit for controlling the amplification factor is provided. Is equipped with.

When the power supply voltage VCCE is set to a certain voltage or higher, in other words, the reference voltage VRFBI for obtaining the stress voltage such as burn-in is the power supply voltage VCCE.
Is output as a voltage lower than the threshold voltage VTH of the P-channel MOSFET by four steps. This voltage VR
When the FBI becomes higher due to the voltage VL multiplied by the amplification circuit, the voltage VL is automatically switched to the stress voltage that follows the voltage VRFBI.

The voltage VDL is output through an impedance conversion buffer which refers to the voltage VL and makes a low impedance power source equal to the voltage VL. This impedance conversion buffer uses a signal LD to reduce power consumption.
The impedance conversion buffer dedicated to the operation controlled by 1) and the impedance conversion buffer for standby controlled by the signal LS.

The signal LD is a signal for activating the impedance conversion buffer for operation. When the signal RASB is set to low level, the signal LD receives the high level of the signal R3 and becomes high level. Activate. At the standby time when the RASB signal is set to the high level, the operation of the impedance conversion buffer during the operation is stopped at the low level of the signals R3 and R3D and the high level of the signal SA to reduce the power consumption.

The signal LS is a signal dedicated to the test mode, and is always set to the high level in the normal mode in which the signal VE is at the low level, and maintains the impedance conversion buffer for standby in the operating state. In the test mode in which the signal VE is set to the high level, the signal VE is set to the low level, the operation of the impedance conversion buffer for standby is stopped, and the signal VEH is set to the high level.
The P-channel MOSFET shown by is turned on to directly connect the internal step-down voltage VDL to the power supply voltage VCCE. In this test mode, the memory array power supply voltage V
This is a mode in which DL is made equal to the power supply voltage VCCE of its peripheral circuits.

The signals SA and SB are formed by a signal INT which detects the level of the power supply voltage VCCE and becomes high level for a certain period after power-on, and a signal WKB which detects the substrate potential and becomes high level. The signal is an initial setting signal for forcibly operating the voltage VDL buffer (impedance conversion buffer) when the power is turned on and charging the potential required for the operation of the memory array.

FIG. 20 shows an overall block diagram of an embodiment of the dynamic RAM according to the present invention.
In this embodiment, the number of memory cells connected to a bit line or a word line is increased for higher integration and lower power consumption. In addition, the operating voltage of the memory array is lowered as described above. Therefore, it takes time to select the memory cell and read the bit line, and the access time is lengthened.

Therefore, an in-page serial access mode is provided to substantially speed up the access time. A row address buffer control signal XL and a column address buffer control signal Y are supplied from a clock generation circuit CLG which receives the control signals RASB, CASB and WEB and OEB.
L, the sense amplifier drive signal SE, the read / write control signal RW, the data input buffer control signal DL, the data output buffer control signal DOE, etc. are output.

The in-page serial access mode is not particularly limited, but during the period when the signal RASB is low level,
The serial clock CK is generated according to the toggle of the CASB signal, and the serial counter SC initially set by the output of the column address buffer CADB is incremented. In such an operation mode, it is not necessary to externally input an address at the time of serial access, and high-speed access is possible.

In the figure, RADB is a row address buffer, CADB is a column address buffer, MA is a memory array, SA is a sense amplifier, CD is a column decoder, RD is a row decoder, WD is a word driver, and MA is a memory array.
Is a main amplifier, DOB is a data output buffer, DIB
Is a data input buffer, and WA is a write amplifier.

FIG. 21 is an overall block diagram of another embodiment of the dynamic RAM according to the present invention. In this embodiment, a data register DR that holds and transfers one page (one word line) of data amplified by the sense amplifier SA between the column decoder CD and the memory array MA in the dynamic RAM of FIG. Are placed.

The serial counter SC is deleted corresponding to the provision of the data register DR as described above. When the data transfer signal DT is generated following the amplification operation of the sense amplifier SA by the signal SE, the data for one page is transferred to the data register RD. Subsequent in-page access can be performed at high speed by using the data register DR as a cache. In particular, if the data register DR has the function of a shift register, the signal CAS
The serial clock CK output according to the toggle of B enables high-speed serial access.

FIG. 22 is a schematic block diagram of an embodiment of a memory device using the dynamic RAM according to the present invention. According to the same design rule as that of the dynamic RAM of about 16 Mbits as in the above-mentioned embodiment, the dynamic RAM to which the present invention is applied has almost 2
Since the degree of integration is doubled (the increase of the chip area is about 25%), a dynamic RAM of about 32 Mbits can be formed.

In this embodiment, ECC (error detection and correction)
Twenty chips can be mounted on a memory card equipped with chips, and a storage capacity twice as large as that of a memory card of the same size and using a dynamic RAM of about 16 Mbits can be realized.

By using the ECC chip, a chip including a defective bit can also be used, and further cost reduction can be achieved. Further, it is possible to obtain sufficient resistance to a soft error caused by α rays.

FIG. 23 shows a sectional structural view of one embodiment of the memory card of FIG. The dynamic RAM of about 32 Mbits is sealed in a TSOP package and mounted on both surfaces of the substrate, so that high density mounting, in other words, high integration can be achieved.

FIG. 24 shows a sectional view of an embodiment of the dynamic RAM according to the present invention. In this embodiment, two semiconductor chips constituting the above-mentioned dynamic RAM of about 32 Mbits are mounted face to face in an SOJ package by using LOC technology. With this configuration, a dynamic type R of about 64 Mbits apparently with a design rule of about 16 Mbits.
AM can be obtained.

The operational effects obtained from the above embodiments are as follows. (1) Higher integration is achieved by increasing the ratio of the parasitic capacitance value in the bit line to the capacitance value of the memory cell by about 20 times or more by using the sense amplifier in which the characteristic variation of the pair MOSFET is compensated. The effect of being able to be obtained is obtained.

(2) By providing a switch MOSFET for disconnecting the bit line connected to the sense amplifier at the center, 2
When one of the memory arrays between the two memory arrays selects the word line that intersects the bit line outside the sense amplifier centering on the switch MOSFET, the other selects the word line that intersects the bit line on the sense amplifier side. By doing so, it is possible to obtain the effect of reducing power consumption.

(3) A plurality of memory arrays are set as one set,
Switch MOSFETs are provided for connecting common source lines to which sense amplifiers are connected to each other, and word lines are sequentially selected one by one in a plurality of memory arrays forming one set in the refresh mode. A power switch MOSF of a sense amplifier that performs an amplifying operation after turning on a switch MOSFET that connects lines to each other to start an amplifying operation of the sense amplifier and turning off the switch MOSFET.
By turning on ET, an effect that power consumption can be reduced can be obtained.

(4) According to the above (1), it is possible to obtain the dynamic RAM of about 32 Mbits by using the design rule of the dynamic RAM of about 16 Mbits as it is.

FIG. 26 is a schematic view of a main part of a memory board which is a memory storage section in a computer system to which the DRAM of the present invention is applied. This memory board is a memory board composed of a plurality of memory modules. A plurality of packaged DRAMs of the present invention are mounted on the memory module, and the DR of the present invention is mounted.
The AM and the wiring on the memory module are connected.

The address bus or data bus in the computer system is connected to the DRAM of the present invention by the connector on the memory module. this is,
This is done by inserting the connector into the memory board slot of the memory section in the memory storage section in the computer system. In this way, the information storage capacity of a storage device such as a computer system is determined by the number of DRAMs of the present invention that can be mounted on a memory board, that is, a memory module.

FIG. 27 shows a DRA using the DRAM of the present invention.
1 shows a schematic diagram of the M system. This system is a DRAM
IC ARRAY and central processing unit CPU and the above DR
It is composed of an interface circuit I / F for interfacing the AM with the central processing unit CPU. The DRAM IC ARRAY is composed of the mounted DRAM of the present invention.

This DRAM system and central processing unit CP
Input / output signals to and from U will be described. Address signals A0-Ak generated by the central processing unit CPU select the addresses of the DRAM of the present invention. The refresh instruction signal REFGRNT is a control signal for refreshing the memory information of the DRAM of the present invention. The write enable signal WEB is a data read / write control signal in the DRAM of the present invention. The memory activation signal MS is a control signal for starting the memory operation of the DRAM of the present invention. Input / output data D1 to DB on the data bus are transmitted between the central processing unit CPU and the DRAM. The refresh request signal REFREQ is a control signal for requesting refresh of the memory information of the DRAM of the present invention.

In the interface circuit I / F, the row address receiver RAR has one of the address signals A0 to Ak sent from the central processing unit CPU.
The address signals A0 to Ai are received and converted into address signals at timings suitable for the operation of the DRAM of the present invention. The column address receiver CAR uses the above address signal A0.
-Ak of address signals Ai + 1 to AJ are received. The column address receiver CAR is the DRA of the present invention.
The address signal is converted into a timing signal suitable for the operation of M. The address receiver ADR receives the address signals Aj + 1 to Ak among the address signals A0 to Ak. Address receiver ADR DRAM of the present invention
The address signal is converted to the timing signal suitable for the operation.

The decoder DCR enables the DRAM of the present invention.
Chip control signal (hereinafter C
S1 to CSm). The RAS control circuit RAS-CONT sends a chip select signal and a row address fetch signal at the timing suitable for the DRAM operation of the present invention. Address multiplexer AD
MPX is the address signals A0 to Ai and Ai + 1.
~ Aj are time-sequentially multiplexed and sent to the DRAM of the present invention. The data bus driver DBD is the central processing unit C described above.
Input / output of data between the PU and the DRAM of the present invention is switched by the WEB signal. Control circuit C
ONT is the address multiplexer ADMPX, RA
It sends out signals for controlling the S control circuit RAS-CONT, the data bus driver DBD, the DRAM of the present invention and the like.

The function of the address signal in this DRAM system will be described. The address signals A0 to Ak sent from the central processing unit CPU are the address signals A0 to Aj and the address signal Aj + 1 in this DRAM system.
~ Ak is separated into two functions. That is, the address signals A0 to Aj are used as the row and column address signals of the memory matrix in each chip of the DRAM of the present invention. The address signals A0 to Ai are the DRA of the present invention.
It is designed to assign Ai + 1 to Aj to the row selection of the M IC chip array and the column selection of the IC chip array.

The circuit operation in this DRAM system will be described. First, address signals A0 to Ai, Ai + 1
Aj to Aj are applied to the address multiplexer ADMPX via the row address receiver RAR and the column address receiver CAR, respectively. Then, in the address multiplexer ADMPX, when the RASbB signal reaches a certain level, row address signals A0 to Ai are transmitted and applied to the address terminals in the DRAM of the present invention. At this time, the column address signals Ai + 1 to Aj are not sent from the address multiplexer ADMPX.

Next, when the RASbB signal becomes the level opposite to the above, column address signals Ai + 1 to Aj are sent from the address multiplexer ADMPX and applied to the address terminals. At this time, the row address signals A0 to A0
Ai is not sent from the address multiplexer ADMPX.

In this way, the address signals A0 to A
i and Ai + 1 to Aj are applied to the address terminals of the DRAM of the present invention in time series according to the level of the RASbB signal. The chip selection signals Aj + 1 to Ak are decoders DCR.
Through, the chip in the DRAM of the present invention is mainly selected. Then, it is converted into chip select signals CS1 to CSm and used as a chip select signal and a row address fetch signal.

The address setting operation in the chip in each row of the DRAM of the present invention will be described. Row address signal A
0 to Ai are applied to the address terminals of all IC chips of the DRAM of the present invention. After that, RAS1B to RAS
It is assumed that when one signal of the mB signals, for example, the RAS1B signal reaches a certain level, the uppermost B ICs are selected. At this time, the ICs (IC11, IC12, ...
.., IC1B) The row address signals A0 to Ai are RA at the row address of the memory matrix array in the chip.
It is applied to the IC before the S1B signal. The reason is that if the RAS1B signal is applied before the row address signals A0 to Ai, signals other than the row address signal may be taken in.

Next, the column address signals Ai + 1 to Aj are applied to the address terminals of all IC chips of the DRAM of the present invention. After that, C delayed from the RAS1B signal
When the ASB signal reaches a certain level, the uppermost nM, B
The column address signals Ai + 1 to Aj are fetched at the column address of the memory matrix array in each IC chip. Here, the column address signals Ai + 1 to
The reason why Aj is applied to the IC before the CASB signal is similar to the above reason. The function of the CASB signal is to determine which of the row address signals A0 to Ai or the column address signals Ai + 1 to Aj is being sent.

With the above operation, the DRA according to the present invention
The uppermost nM of M bits and B in-chip addresses are set. Further, ICs other than the uppermost stage of the DRAM of the present invention are RA
Since the S2B to RASmB signals are opposite in level to the level of RAS1B, they are not selected.

A data write operation and a data read operation at the set address will be described. The data write operation and data read operation are designed to be determined by the high level or low level of the WEB signal. The data write operation is performed by the central processing unit C at the set address when the WEB signal is at a certain level.
This is performed by applying data DI1 to DIB from PU.

The read operation is performed by outputting the data Do1 to DoB of the respective addresses which have been written when the WEB signal is at a level opposite to the above level, by B bits. The control circuit CONT receives the command signal from the central processing unit CPU, that is, REF.
Receiving GRNT signal, WEB signal, MS signal, CASB
Signal, RASaB signal, RASbB signal, WEB signal, respectively. The function of these transmitted control signals will be described. The CASB signal is a row address signal A0 to Ai or a column address signal Ai + 1 to Ai.
A signal for distinguishing which one of j is being sent to each chip in the DRAM of the present invention and a signal for fetching the column address signal of the IC chip.

The RASaB signal is a signal for supplying the CS1 to CSm signals to the IC chip array in the DRAM of the present invention at the same timing. The WEB signal is a signal for determining reading of data from a memory cell in the IC chip in the DRAM of the present invention and writing of data to the memory cell. The RASbB signal is the row address signals A0 to Ai from the address multiplexer ADMPX.
And a switching timing signal for converting the column address signals Ai + 1 to Aj into time series multiplexed signals.
When one of the RASB (RASB1 to RASBm) signals is selected, the row address signals A0 to Ai and the column address signals Ai + 1 to Aj are switched so that the address multiplexer ADMPX outputs the row address signals A0 to Ai. The signal is delayed from the RASaB signal.

WEB signal and data bus driver DB
The relationship of D will be described. The WEB signal sent from the control circuit CONT is applied to the DRAM and the data bus driver DBD of the present invention. For example, when the WEB signal is at a high level, the read mode is set and the D
RAM data is output and data bus driver DBD
To the central processing unit CPU. At this time,
The input data is from the DBD to the DR of the present invention by the WEB signal.
It is controlled not to be taken into AM. Further, when the WEB signal is low level, the write mode is set, and the central processing unit CPU is connected to the data input terminal of the DRAM of the present invention.
Input data is applied via the data bus driver DBD, and the data is written at the set address. At this time, the data output of the DRAM of the present invention is the WE
It is controlled by the B signal so as not to be output from the data bus driver DBD.

FIG. 28 is a schematic view of the essential parts of a computer system to which the DRAM of the present invention is applied. Bus and central processing unit CPU, peripheral device control unit, DRAM of the present invention as main memory and its control unit, SRAM as backup memory and backup parity and its control unit, ROM storing program, display system, etc. This computer system is configured.

The peripheral device control section is connected to an external storage device, a keyboard KB and the like. Display system is video R
It is composed of an AM (hereinafter referred to as VRAM), etc., and V is connected to a display as an output device.
The stored information in the RAM is displayed. Further, a power supply unit for supplying power to the internal circuit of the computer system is provided. The central processing unit CPU controls the operation timing of each memory by forming a signal for controlling each memory. Here, an example in which the present invention is applied to a DRAM as a main memory has been described above, but when the VRAM of the display system is a multiport VRAM, it can be applied to a random access unit of the VRAM. is there.

FIG. 29 is a schematic view of the external appearance of a personal computer system when the DRAM of the present invention is applied as a main memory. This is a system in which a floppy disk drive FDD, a file memory fileM by the DRAM of the present invention as a main memory, and an SRAM as a battery backup are built in. And
The input / output device is the keyboard KB and the display DP, and the floppy disk FD is inserted into the floppy disk drive FDD. As a result, a desktop type personal computer capable of storing information in the floppy disk FD as software and the file memory fileM as hardware is obtained. Further, although an example in which the present invention is applied to a desktop type personal computer is described in the present embodiment, it is also applicable to a notebook type personal computer and the like, and a floppy disk is described as an auxiliary function as an example, but the present invention is not particularly limited.

FIG. 30 shows a functional block diagram of a personal computer system when the DRAM of the present invention is applied as a main memory. This personal computer includes a central processing unit CPU as the information device, an I / O bus built in the information processing system, and a BUS Uni.
t, a memory control unit for accessing a high-speed memory such as a main memory or an extended memory.
ll Unit, DRA of the present invention as main memory
M, ROM storing the basic control program, keyboard controller KBDC with a keyboard connected to the tip
Etc.

Display a as a display adapter
The adapter is connected to the I / O bus, and
A display is connected to the tip of the ay adaptor. The I / O bus includes a parallel port Parallel Port I / F, a serial port Serial Port I / F such as a mouse, a floppy disk drive FDD, and an HDD from the I / O bus.
Buffer controller HDD buf for converting to I / F
fer is connected.

The memory control unit Memory C
Connected to the bus from the control unit and expanded R
An AM and a DRAM as a main memory of the present invention are connected. Here, the operation of the personal computer system will be described. When the power is turned on and the operation is started, first, the central processing unit CPU causes the RO
M is accessed through the I / O bus to perform initial diagnosis and initialization. Then, the system program is loaded from the auxiliary storage device into the DRAM of the present invention as the main storage memory.

The central processing unit CPU operates to access the HDD to the HDD controller through the I / O bus. When the loading of the system program is completed, the processing proceeds according to the processing request from the user. The user can use the keyboard controller KBDC on the I / O bus or the display adapter Display adapt.
Work is performed while inputting / outputting processing by er.
Parallel port Parallel Por if required
t I / F, serial port Serial Port
Utilize the input / output device connected to the I / F. When the main memory capacity of the DRAM of the present invention as the main memory on the main body is insufficient, the main memory is supplemented by the expanded RAM. Further, although the hard disk drive HDD is shown in the same drawing, it can be replaced with a flash file using a flash memory. Needless to say, the dynamic RAM according to the present invention can be applied to not only the main memory but also the expansion RAM and the auxiliary memory.

When the dynamic RAM according to the present invention is mounted in the information processing system as in the above embodiment, the miniaturization and high performance are achieved by the high integration, large capacity or high speed or low power consumption. Can be expected.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in the layout of the dynamic RAM, the number of bit lines to be connected can be set variously in consideration of the performance of the sense amplifier and the capacitance value of the capacitor of the memory cell as described above. Various modifications can be made. The circuit for compensating for the variation in the threshold voltage of the pair MOSFET of the sense amplifier can adopt various embodiments. This invention is a dynamic RA
It can be widely used for M and an information processing system using the same.

[0160]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, high integration can be realized by increasing the ratio of the parasitic capacitance value on the bit line to the capacitance value of the memory cell by about 20 times or more by using the sense amplifier in which the characteristic variation of the pair MOSFET is compensated.

A switch MOSFET for disconnecting the bit line connected to the sense amplifier at the center is provided, and one of the two memory arrays has a word line which intersects the bit line outside the sense amplifier with the switch MOSFET as the center. On the other hand, when selected, the word line intersecting with the bit line on the sense amplifier side is brought into the selected state, so that the power consumption can be reduced.

A plurality of memory arrays are set as one set, switch MOSFETs for connecting common source lines to which sense amplifiers are connected to each other are provided, and one set is provided for each of the plurality of memory arrays forming one set in the refresh mode. A switch MOSF for sequentially selecting word lines and mutually connecting the common source lines
Turn on ET to start the amplification operation of the sense amplifier,
Low power consumption can be achieved by turning on the power switch MOSFET of the sense amplifier which performs the amplifying operation after turning off the switch MOSFET.

By using the dynamic RAM as a memory device as described above, the size and performance of the information processing system can be reduced.

[Brief description of drawings]

FIG. 1 is a chip layout diagram showing an embodiment of a dynamic RAM using a sense amplifier according to the present invention.

FIG. 2 is a main part circuit diagram showing an embodiment of a dynamic RAM to which the present invention is applied.

FIG. 3 is a main part circuit diagram showing another embodiment of a dynamic RAM to which the present invention is applied.

FIG. 4 is a timing diagram illustrating an operation of the sense amplifier of FIG.

5 is a timing diagram for explaining the operation of the sense amplifier of FIG.

FIG. 6 is a main part circuit diagram showing another embodiment of a dynamic RAM to which the present invention is applied.

FIG. 7 is a main part circuit diagram showing still another embodiment of a dynamic RAM to which the present invention is applied.

8 is a timing diagram for explaining the operation of the sense amplifier of FIG.

9 is a timing diagram for explaining the operation of the sense amplifier of FIG.

FIG. 10 is a chip layout diagram showing an example of a dynamic RAM using a conventional sense amplifier.

FIG. 11 is a main part circuit diagram showing another embodiment of the dynamic RAM according to the present invention.

12 is a timing chart for explaining the operation of the sense amplifier of FIG.

FIG. 13 is a schematic chip layout diagram showing another embodiment of the dynamic RAM according to the present invention.

14 is an explanatory diagram of an operation of the dynamic RAM of FIG.

FIG. 15 is a schematic circuit diagram showing another embodiment of the dynamic RAM according to the present invention.

16 is a timing chart for explaining the operation of the dynamic RAM of FIG.

FIG. 17 is a schematic block diagram showing another embodiment of the dynamic RAM according to the present invention.

18 is a characteristic diagram for explaining the operation of the power supply voltage down circuit of FIG.

19 is a circuit diagram showing an embodiment of the power supply voltage down circuit of FIG.

FIG. 20 is an overall block diagram showing another embodiment of the dynamic RAM according to the present invention.

FIG. 21 is an overall block diagram showing another embodiment of the dynamic RAM according to the present invention.

FIG. 22 is a schematic block diagram showing one embodiment of a memory device using a dynamic RAM according to the present invention.

FIG. 23 is a sectional view showing an embodiment of a dynamic RAM according to the present invention.

FIG. 24 is a sectional view showing an embodiment of a dynamic RAM according to the present invention.

FIG. 25 is a sectional view of an element structure showing an embodiment of the memory cell portion of the dynamic RAM according to the present invention.

FIG. 26 is a schematic view of a main part of a memory board to which the DRAM of the present invention is applied.

FIG. 27 is a schematic diagram of a main part of a DRAM system to which the DRAM of the present invention is applied.

FIG. 28 is a schematic diagram of a main part of a computer system to which the DRAM of the present invention is applied.

FIG. 29 is a functional external view of a personal computer system to which the DRAM of the present invention is applied.

FIG. 30 is a functional block diagram of a personal computer system to which the DRAM of the present invention is applied.

[Explanation of symbols]

MA ... Memory array, RD ... Row decoder, CD ... Column decoder, WD ... Word line driver, PC ... Precharge circuit, SA ... Sense amplifier, MA ... Main amplifier,
WA ... Write amplifier, RADB ... Row address buffer, CADB ... Column address buffer, SC ... Serial counter, DR ... Data register, DOB ... Data output buffer, DIB ... Data input buffer, CLG ... Clock generation circuit. CPU ... Central processing unit, I / F ... Interface circuit, RAR ... Row address receiver,
CAR ... Column address receiver, ADR ... Address receiver, DCR ... Decoder, RAS-CONT ... R
AS control circuit, CONT ... control circuit,
DBD ... Data bus driver, REFREQ ... Refresh request signal, MS ... Memory activation signal, REGRNT ...
Refresh instruction signal, ADMPX ... Address multiplexer, DP ... Display, FDD ... Floppy disk drive, FD ... Flappy disk, file
M ... File memory, KB ... Keyboard, KBDC ... Keyboard controller, HDD ... Hard disk drive. 44 ... Source / drain diffusion layer, 46 ... Word line,
48 ... Storage electrode, 49 ... Plate electrode, 50 ... Bit line, 52 ... Word line shunt aluminum layer, 53
... Gate insulating film, 54 ... Insulating film (dielectric).

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Masayuki Nakamura 2326 Imai, Ome City, Tokyo, Hitachi, Ltd. Device Development Center (72) Inventor Hiroshi Otori 2326 Imai, Ome City, Tokyo Hitachi, Ltd. Device Development Center (72) Inventor Tetsuro Matsumoto 2326 Imai, Ome-shi, Tokyo Inside Hitachi, Ltd. Device Development Center

Claims (12)

[Claims] 1. A sense amplifier in which characteristic variations of paired MOSFETs are compensated for, and a ratio of a parasitic capacitance value in a bit line to a memory cell capacitance value is increased from about 20 times to an operable range of the sense amplifier. Dynamic type RAM characterized by. 2. Each bit line has 1024 lines.
2. The dynamic RAM according to claim 1, wherein a plurality of or more memory cells are connected. 3. The sense amplifier has a first conductivity type first amplification MOSFET whose source and drain are connected to one of complementary bit lines, and one source and drain of which is connected to the other complementary bit line. Second amplification MO of the first conductivity type
SFET, one of complementary bit lines and second amplification MOSF
The other of the gate of ET and the complementary bit line and the first amplification MO
First and second connecting to the gate of the SFET, respectively
Switch MOSFET, and the first and second amplification MO
Third and fourth switch MOSFETs that connect the gate of the SFET to the other source and drain, respectively, and the gate and one source and drain of the complementary bit line are cross-connected to form a latch form. Type third and fourth amplification MOSFETs, and a first conductivity type power switch M for applying one operating voltage to the other common source and drain of the first and second amplification MOSFETs.
OSFET, a second conductivity type power switch MOSFET for applying the other operating voltage to the other common source and drain of the third and fourth amplification MOSFETs, and the other of the first and second amplification MOSFETs. The source and drain of the first and second amplification MO at a voltage half the operating voltage
A precharge MOSFET for applying a precharge voltage to which a voltage corresponding to the threshold voltage of the SFET is added, and turning on the third and fourth switch MOSFETs to supply the precharge voltage from the precharge MOSFET. A first period for precharging the first and second input terminals through the first and second amplification MOSFETs;
The third and fourth switch MOSFETs are turned off, the first and second switch MOSFETs are turned on, and the memory cell selected on the basis of the precharge voltage is read to the bit line coupled to the memory cell. A second period in which a minute potential is applied, and a first conductivity type power switch MOSFET is turned on to provide a first and a second amplification MOS.
The FET is activated, and then the power switch MOSFET of the second conductivity type is turned on so that the third and fourth amplification M
The dynamic RAM according to claim 1 or 2, wherein an amplification operation is performed by a third period in which the OSFET is activated. 4. The fifth and sixth switches M are provided between the pair of input / output terminals of the sense amplifier and the complementary bit lines.
5th and 6th switch MOSF provided with OSFET
After the ET is turned on and the read minute signal appearing on the complementary bit line is given to the input / output terminal of the sense amplifier, the fifth and sixth switch MOSFETs are turned off to start the amplification operation of the sense amplifier. 4. The fifth and sixth switch MOSFETs are turned on again after the amplified signal is increased.
Dynamic RAM. 5. The sense amplifier includes fifth and sixth switch MOSFETs provided with complementary bit lines, and a pair of first and second input terminals corresponding to the complementary bit lines, one source being one source. , Fifth and sixth amplification MOSFETs whose drains and gates are cross-connected, and the fifth and sixth amplification MOSFETs
One electrode is connected to the source of the amplification MOSFET of
First and second capacitance means including first and second capacitance means having the other electrode in common, and a power switch MOSFET for applying an activation voltage to the sources of the fifth and sixth amplification MOSFETs. A first period in which a predetermined potential is applied to the other common electrode of the above, the fifth and sixth switch MOSFETs are turned on and the same precharge voltage is applied to the signal line and the input terminal, and the complementary bit line In a second period in which a minute voltage for reading from the memory cell is applied to one side, the fifth and sixth switch MOSFETs are turned off, and the potential of the other electrode common to the first and second capacitance means is set. For a third period during which the power switch MOSFET is changed to a level that activates the first and second amplification MOSFETs, and a fifth period after activating the first and second amplification MOSFETs by turning on the power switch MOSFET. Dynamic RAM according to claim 1 or claim 2, characterized in that according to the fourth period to the sixth switches MOSFET turned on again is intended to perform an amplifying operation. 6. The operating voltage of the sense amplifier is set to be lower than the operating voltage of a peripheral circuit including an address selection circuit by a step-down circuit receiving a power supply voltage supplied from the outside. Claim 1, Claim 2,
Dynamic type RA according to claim 3, claim 4 or claim 5.
M. 7. A sense amplifier in which the first and second memory arrays each having a switch MOSFET for disconnecting a bit line connected to the sense amplifier at the center are provided as a set, and the switch MOSFET is centered in the first memory array. When a word line crossing the bit line on the outer side of is selected, the switch M in the second memory array is selected.
When the word line intersecting the bit line on the sense amplifier side with the OSFET as the center is selected and the word line intersecting with the bit line on the sense amplifier side with the switch MOSFET as the center is selected in the first memory array. , Switch MOSFE in the second memory array
Addressing is performed so that a word line intersecting with an outer bit line is selected with respect to the sense amplifier centering on T, and a word line intersecting with the bit line on the sense amplifier side is selected. A dynamic RAM in which a switch MOSFET is turned off in a memory array. 8. A plurality of memory arrays are set as one set, switch MOSFETs for connecting common source lines to which the sense amplifiers are connected to each other are provided, and one set in the plurality of memory arrays forming one set in the refresh mode. Switch MOSFETs for sequentially selecting the word lines one by one and connecting the common source lines to each other
The power switch MO of the sense amplifier is turned on to start the amplification operation of the sense amplifier, and turns off the switch MOSFET to perform the amplification operation.
The dynamic RAM according to claim 1, claim 2, claim 3, claim 4, claim 5, claim 6 or claim 7, wherein the SFET is turned on. 9. The dynamic RAM according to claim 8, wherein a switch MOSFET for short circuit is provided on the common source line of the sense amplifier, and the short circuit is provided when the switch MOSFET is in a non-operating state. 10. A sense amplifier in which characteristic variations of paired MOSFETs are compensated is used, and a ratio of a parasitic capacitance value on a bit line to a capacitance value of a memory cell is increased from about 20 times to an operable range of the sense amplifier. An information processing system using a dynamic RAM as a memory device. 11. A first switch provided with a switch MOSFET for disconnecting a bit line connected to a sense amplifier at a center thereof.
And a second memory array as one set, and when a word line that intersects with a bit line outside the sense amplifier centering on the switch MOSFET in the first memory array is selected, in the second memory array, A word line that intersects the bit line on the sense amplifier side with the switch MOSFET as the center is selected, and a word line that intersects with the bit line on the sense amplifier side with the switch MOSFET as the center is selected. Sometimes, in the second memory array, the switch MOSF
Address setting is performed so that the word line intersecting with the outer bit line is selected with respect to the sense amplifier centering on ET, and the word line intersecting with the bit line on the sense amplifier side is selected. An information processing system characterized in that a dynamic RAM in which a switch MOSFET is turned off is used as a memory device in a memory array. 12. A sense amplifier in which characteristic variations of paired MOSFETs are compensated is used, and a ratio of a parasitic capacitance on a bit line to a memory cell capacitance value is increased from about 20 times to an operable range of the sense amplifier, and a plurality of them are provided. Of memory arrays are set as one set, and switch MOSFETs for connecting the common source lines to which the above sense amplifiers are connected to each other are provided, and the plurality of memory arrays forming one set in the refresh mode are sequentially word line by line. Is selected, the switch MOSFETs that connect the common source lines to each other are turned on to start the amplification operation of the sense amplifier, and the switch MOSFE
An information processing system characterized by using as a memory device a dynamic RAM in which a power switch MOSFET of the sense amplifier is turned on after performing an amplification operation after turning off T.