JPH06222089A - Window comparator - Google Patents

Abstract

PURPOSE:To make circuit constitution capable of contriving free setting of an upper limit value or a lower limit value and precisely and simply agreeing with its set value in a window comparator. CONSTITUTION:An N-channel MOS transister 21 for constituting a second differential amplifier is connected between common connection terminals of the other N-channel MOS transisters 11, 12 for constituting a first differential amplifier and a constant current power source 15 together with another N-channel MOS transister 22 and these differential amplifiers are coupled in connection relation such as an analog multiplier. Input voltage Vin common to these differential amplifiers and respective different reference voltage E1, E2 are supplied to gates of the MOS transisters 11, 12, 21, 22 and output voltage of the window comparator indicates a value which is multiplied by a result in which voltages in the two differential amplifiers are compared with each other.

Description

Detailed Description of the Invention

[0001]

The present invention relates to MOS (metal-oxide-
(Silicon) structure window comparator.

[0002]

2. Description of the Related Art A window comparator is a comparator which changes its output depending on whether or not an input signal voltage is within a predetermined range. Such a window comparator is usually constructed by combining a pair of comparators, and as an example of a known window comparator, there is a circuit configuration described in Japanese Patent Laid-Open No. 52-99866.

FIG. 3 shows the circuit. As shown in FIG. 3, the pair of differential amplifiers are npns each forming a differential pair.
Type bipolar transistors 71, 72 and 61, 62, the common current mirror circuit of the differential amplifier is p
It is composed of np type bipolar transistors 85 and 86. The emitter of the npn bipolar transistor 71 is connected via the resistor 76 to the npn bipolar transistor 7
The emitter of 2 is directly connected to the constant current source 75, and the emitter of the npn bipolar transistor 62 is connected via the resistor 66 to the npn bipolar transistor 6
The emitters of No. 1 are directly connected to the constant current source 65, respectively. The reference voltage (or reference voltage) of the terminal 52 is n
The input voltage (or input signal voltage) is supplied from the terminal 51 to the bases of the pn-type bipolar transistors 62 and 72, and to the bases of the npn-type bipolar transistors 61 and 71. The output stage is composed of a pnp bipolar transistor 89.

In the window comparator shown in FIG. 3, the threshold voltage, that is, the upper limit value and the lower limit value of the comparator are the absolute values of the constant current sources 65 and 75, the absolute values of the resistors 66 and 76, and the pnp type transistors 85 and 86. It is determined by the ratio of currents.

[0005]

However, in the window comparator having the circuit configuration shown in FIG. 3, the upper limit value and the lower limit value are affected by electrical factors such as the absolute value of each element and the current capability. , It is difficult to freely set the upper and lower limits. Further, this window comparator is formed on one semiconductor chip as a part of a semiconductor integrated circuit. However, the size, conductivity, etc. of each element that determines the above-mentioned electrical factors vary due to variations in the manufacturing process. Therefore, it is not easy to form the element as designed, and it is difficult to accurately match the upper limit value and the lower limit value with the design value.

In view of the above technical problems, the present invention has an object to provide a window comparator which can freely set the upper limit value and the lower limit value thereof, and at the same time, can be accurately and easily adjusted.

[0007]

The window comparator of the present invention has a MOS structure and includes first and second differential amplifiers. One of the active elements of the second differential amplifier is connected between the common connection terminal of the active elements of the first differential amplifier and the constant current source, and the first differential amplifier and the second differential amplifier are connected. Is a connection relationship such as a so-called analog multiplier. 2 of these first and second differential amplifiers
A common input voltage and a different reference voltage are supplied to the pair of control terminals, and one of the different reference voltages is the upper limit reference voltage and the other is the lower limit reference voltage.

In this window comparator, the first
The differential amplifier may have a circuit configuration including a current mirror circuit, and the other active element of the second differential amplifier is preferably connected between the current mirror circuit and the constant current source. An n-channel MOS transistor may be used as the active element, and the current mirror circuit may be composed of a p-channel MOS transistor.

[0009]

A predetermined input voltage and a reference voltage are supplied to the control terminals of the active elements of each differential amplifier, and in the first differential amplifier, the input voltage and one of the upper limit reference voltage and the lower limit reference voltage are supplied. And the second differential amplifier compares the input voltage with the other one of the lower limit reference voltage and the upper limit reference voltage. In the window comparator of the present invention, one of the active elements of the second differential amplifier is connected between the common connection terminal of the active elements of the first differential amplifier and the constant current source, and the first difference The voltage at the common connection terminal of the dynamic amplifier reflects the result of comparison between the input voltage to the second differential amplifier and the reference voltage. At the same time, since the input voltage and the reference voltage are also compared in the first differential amplifier itself, the output voltage of the window comparator is eventually the product of the comparison results of the two differential amplifiers.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described with reference to FIGS.

FIG. 1 is a circuit diagram showing a window comparator of this embodiment. This window comparator is a CMO
It has an S configuration and has a pair of differential amplifiers.

As shown in FIG. 1, the n-channel MOS transistors 21 and 22 form a second differential amplifier for lower limit comparison, the sources thereof are commonly connected, and the constant current source 15 is provided.
Is connected to the ground voltage Vss on the negative side. The gate of the n-channel MOS transistor 21 is connected to the terminal 16 and is supplied with the input voltage Vin whose voltage is to be compared. The gate of the n-channel MOS transistor 22 is connected to the terminal 23 and is supplied with a lower limit reference voltage E ₁ as a lower limit value.

This n-channel MOS transistor 21
Is connected to the commonly connected sources of the n-channel MOS transistor 11 and the n-channel MOS transistor 12 of the first differential amplifier for upper limit comparison.
As a result, the n-channel MOS transistor 21 of the differential amplifier for lower limit comparison is connected between the commonly connected source of the differential amplifier for upper limit comparison and the constant current source 15. Due to the connection relationship such as the multiplier, the number of elements is small, and the operation is effectively performed by the upper limit value and the lower limit value freely determined. The gate of the n-channel MOS transistor 11 and the gate of the n-channel MOS transistor 21 are common to the terminal 16
And are supplied with the same input voltage Vin. The gate of the n-channel MOS transistor 12 is connected to the terminal 17, and the upper limit reference voltage E ₂ as the upper limit value is supplied through the terminal 17.

N-channel MOS transistors 11, 1
The drains of 2 and 22 are connected to the current mirror circuit of the differential amplifier. This current mirror circuit is a p-channel MO in which the positive side power supply voltage V _DD is supplied to each source.
It consists of S transistors 13 and 14. p channel MO
In order that the drain voltage of the S transistor 13 becomes the gate voltage of each gate, the p-channel MOS transistor 1
The gates of 3 and 14 are p-channel MOS transistors 1
The drain of the p-channel MOS transistor 13 is connected to the drains of the n-channel MOS transistors 11 and 22. The drain of the p-channel MOS transistor 14 which is current-mirror connected to the p-channel MOS transistor 13 is
It is connected to the drain of n-channel MOS transistor 12. The drain of the p-channel MOS transistor 14 is a p-channel MOS which further constitutes an output stage.
Connect to the gate of transistor 31.

P-channel M as output transistor
The power supply voltage V _DD is supplied to the source of the OS transistor 31, and the drain of the p-channel MOS transistor 31 is connected to the ground voltage Vss via the constant current source 32 as a load. The output terminal 33 is taken out from the drain of the MOS transistor 31, and the output terminal 33 is taken out.
Then, the output voltage V _OUT as a window comparator is obtained.

Next, the operation of the window comparator of this embodiment will be described. When the input voltage Vin of the terminal 16 is lower than the upper limit reference voltage E ₂ and the lower limit reference voltage E ₁ , the gate voltage of the n-channel MOS transistor 22 becomes higher than the gate voltage of the n-channel MOS transistor 21, and the constant current is constant. The current flowing through the source 15 will flow through the n-channel MOS transistor 22. Therefore, the current flowing from the power supply voltage V _DD through the p-channel MOS transistor 13 connected to the MOS diode flows through the n-channel MOS transistor 22 and the constant voltage source 15 to reach the ground voltage Vss.
At this time, a current does not flow through the n-channel MOS transistor 21, so that a current cannot necessarily flow through the n-channel MOS transistors 11 and 12 of the upper limit differential amplifier. p-channel MOS transistor 13
The p-channel MOS transistor 14 forming the current mirror circuit tries to pass a current equivalent to that of the p-channel MOS transistor 13, but the n-channel MOS transistor 12 connected to its drain cannot pass a current. In addition, the drain voltage of the p-channel MOS transistor 14 rises to near the power supply voltage V _DD . As a result, the p-channel MOS transistor 31 which is an output transistor is turned off, and the output voltage V _OUT of the output terminal 33 becomes the level of the ground voltage Vss conducted through the constant current source 32.

Next, when the input voltage Vin is the lower limit reference voltage E ₁
When the input voltage Vin is higher than the upper limit reference voltage E ₂ and the input voltage Vin is lower than the upper limit reference voltage E ₂ , first, the gate voltage of the n-channel MOS transistor 21 becomes higher than the gate voltage of the n-channel MOS transistor 22, and the constant current source 15 is turned on. The flowing current flows through the n-channel MOS transistor 21 and does not flow through the n-channel MOS transistor 22. Similarly, since the gate voltage of the n-channel MOS transistor 12 is higher than the gate voltage of the n-channel MOS transistor 11, the current flowing through the n-channel MOS transistor 21 flows through the n-channel MOS transistor 12 and the n-channel MOS transistor 1
It doesn't flow to 1. n-channel MOS transistor 2
Since 2 and 11 do not flow current, p-channel MOS
No current necessarily flows through the transistor 13. Therefore, the p-channel MOS transistor 1 forming a current mirror circuit with the p-channel MOS transistor 13
4 also operates so that no current flows, and eventually the drain voltage of the n-channel MOS transistor 12 is lowered to near the ground voltage Vss by the current flowing through the n-channel MOS transistors 12 and 21 and the constant current source 15. As a result, the p-channel MOS transistor 31 operates so as to allow the current of the constant current source 32 or more to flow, and the output voltage V _OUT becomes the level of the power supply voltage V _DD .

Next, when the input voltage Vin is the upper limit reference voltage E ₂
And both lower limit reference voltage E ₁ are higher than the lower limit reference voltage E ₁ , the gate voltage of the n-channel MOS transistor 21 is higher than the gate voltage of the n-channel MOS transistor 22, and the current flowing through the constant current source 15 is the n-channel MOS transistor.
It flows through the transistor 21 and does not flow into the n-channel MOS transistor 22. At the same time, the gate voltage of the n-channel MOS transistor 11 is higher than the gate voltage of the n-channel MOS transistor 12, and
The current flowing through the OS transistor 21 is an n-channel M
It flows through the OS transistor 11 and does not flow through the n-channel MOS transistor 12. The current flowing through the n-channel MOS transistor 11 flows through the p-channel MOS transistor 13 which is MOS diode-connected to the power supply voltage V _DD . Therefore, p-channel MOS
Transistor 14 is a p-channel MOS transistor 1
An n-channel MOS transistor 12 connected to the drain of the n-channel MOS transistor
Cannot pass current, so p-channel MOS
The drain voltage of the transistor 14 becomes the voltage level of the power supply voltage V _DD , and the p-channel M which is an output transistor.
The OS transistor 33 cannot pass a current. Therefore, the output voltage V _OUT of the output terminal 33 becomes the voltage level of the ground voltage Vss.

FIG. 2 is a diagram showing the relationship between the input voltage Vin and the output voltage V _OUT of the window comparator of this embodiment.
When the input voltage Vin is larger than the lower limit reference voltage E ₁ and smaller than the upper limit reference voltage E ₂ , the output voltage V _OUT becomes the voltage level of the power supply voltage V _DD , and in other cases, the output voltage V _OUT is grounded. It can be seen that the voltage level is the voltage Vss.

If the window comparator of this embodiment is composed of bipolar transistors, its operation is
Problems may occur. That is, n channel M
It is also possible to replace the OS transistor with an npn-type bipolar transistor and replace the p-channel MOS transistor with a pnp-type bipolar transistor. However, since the MOS transistor is a variable resistance element based on the gate voltage and the bipolar transistor is a current amplification element based on the base current, M
In the case of an OS transistor, the drain of the n-channel MOS transistor 21 and the source of the n-channel MOS transistor 11 are connected, and even if their gates are connected, they function as resistance elements, but in the case of a bipolar transistor, they are n-channel MOS transistors. 11,
When the collector and the emitter of two npn type bipolar transistors are connected to each other and the bases of the two bipolar transistors are connected to each other instead of 21, the emitter of the bipolar transistor of the lower limit differential amplifier is
The collector-to-collector voltage becomes equal to or lower than the saturation voltage, and the current of the constant current source flows to the input terminal 16 via the base of the bipolar transistor of the lower limit differential amplifier, so that normal operation cannot be expected. Therefore, in order to obtain a normal operation, the window comparator of this embodiment needs to have a MOS structure.

[0021]

As described above in detail, in the window comparator of the present invention, the first and second MOS structures are used.
In this configuration, the first differential amplifier and the second differential amplifier are coupled by a connection relationship such as what is called an analog multiplier. By supplying the input voltage, the upper limit reference voltage, and the lower limit reference voltage to each control terminal of these differential amplifiers, it is possible to freely set the threshold voltage independent of the circuit configuration, and to set the voltage accurately and easily. You can Also, the number of elements will be small, and MO
This structure is suitable for manufacturing an S-structure semiconductor integrated circuit device.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a window comparator according to an embodiment of the present invention.

FIG. 2 is an input / output characteristic diagram of the window comparator of FIG.

FIG. 3 is a circuit diagram of an example of a conventional window comparator.

[Explanation of symbols]

11, 12, 21, 22 n-channel MOS transistor 13, 14, 31 p-channel MOS transistor 15, 32 constant current source 16, 17, 23 terminal Vin input voltage V _OUT output voltage E ₁ lower limit reference voltage E ₂ upper limit reference voltage

Claims (2)

[Claims] 1. A first differential amplifier including first and second MOS transistors, a second differential amplifier including third and fourth MOS transistors, and fifth and sixth MOSs.
A current mirror circuit including a transistor, a common connection point of the first differential amplifier is connected to one terminal of the second differential amplifier, and a common connection point of the second differential amplifier is a constant current Connected to a second potential point via a voltage source, a common connection point of the current mirror circuit is a first potential point, and one terminal is one terminal of the first differential amplifier and the second difference. The other terminal of the dynamic amplifier is connected to the other terminal of the first differential amplifier, and the input voltage is commonly supplied to one of the control terminals of the first and second differential amplifiers. A window comparator, wherein different first and second reference voltages are supplied to the other control terminals of the first and second differential amplifiers, respectively. 2. The window comparator according to claim 1, wherein the first, second, third, and fourth MOS transistors are n-channel type, and the fifth and sixth MOS transistors are p-channel type. .