JPH0622040B2 - Electronic graphic system and graphic creation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION RELATED APPLICATION This application is a continuation-in-part of US patent application Ser. No. 06 / 664,980 to Nakamura et al., Filed October 26, 1984, assigned to the same assignee as this application.

BACKGROUND OF THE INVENTION Researchers have undertaken a wide variety of technical studies on the generation of paired coordinate signals from electronic graphics devices.
The industrial demand for such devices is increasing with the development of computer graphics, computer aided design (CAD) and computer aided manufacturing (CAM) systems. However, for such applications, digitizers or graphic tablets that make up such electronic graphics devices are required to be used in electrically noisy environments. It has been observed that such an environment results in interference frequencies, such as, for example, synchronization signals of the visual reading components and associated electronics that are necessarily located in the area of the tablet.

The operation of the digitizer or graphic tablet is
In general, it involves the same manual work as used in conventional graphic design, ie, drawing or selectively positioning a stylus or tracer for handwriting across the surface of the digitizer.
In addition, the electronic graphics device responds to the position of the stylus,
It produces a pair of analog coordinate signals that are digitized and sent to a host computer mechanism.

In most cases, the digitizer is constructed as a composite structure in which a grid of two separated rows of fine wires arranged at right angles to each other is embedded in an insulating carrier. One face of such a structure serves to result in receiving a stylus input that is converted into a coordinate signal. Various methods have been considered for producing the coordinate-defining signal as the interaction between the stylus and the lattice, for example, the magnetostriction effect between the stellais and the lattice can be ensured, or capacitive coupling between these elements can be ensured. It can also have an effect.

The use of such a grid structure, while yielding an accurate linear output coordinate signal, necessarily involves a precision structure that is expensive to manufacture and susceptible to breakage during normal use.
Furthermore, in many applications it is desirable to manufacture the digitizer as a highly transparent composite sheet.
However, the formation of gratings within the composite structure generally hinders such transparency properties.

Older researchers noted the advantage in developing a digitizer with a writing surface formed from a coating of continuous resistive material. A clear advantage over such digitizer attempts is the unique structural simplicity of providing a resistive surface on a supporting insulating substrate such as glass or plastic. Further, the substrate and associated resistive coating can be transparent to allow a wide range of industrial applications.

The enlightenment history of such resistant coating type devices shows that researchers have encountered various technical problems, one of which is the uneven reading of the coordinates obtained by the surface. Is to be. In general, an exact one-to-one correspondence or linearity between the actual stylus or tracer position and the resulting coordinate signal is required. Resistive coatings cannot actually be formed without causing local resistance changes, eg, about + 10% change, so that the otherwise non-linear characteristic of otherwise promising design attempts has recently become. Until now, it has been an obstacle to the development of practical devices.
However, some important work has been accomplished using resistive surfaces. For example, Turner was assigned to the same assignee as the present application.
In U.S. Pat. No. 3,699,439 issued October 17, 1972, "Apparatus and Method Responsive to Electrical Probe Position", a critical processing or switching technique is disclosed. This approach uses the input of a current form directly from a hand-held stylus to the resistive surface, with the stylus tip physically contacting the resistive surface. Schlosser et al. Describe yet another improvement in which an AC input signal is used in conjunction with each device, resulting in a significant improvement in paired coordinate output signal processing. See U.S. Pat. No. 4,456,787, "Electronic Graphic Systems and Methods," issued June 26, 1984, also assigned to the same assignee as the present application. The operation corresponding to the position of the resistive layer type device is further
This was also assigned to the same assignee as this application October 25, 1977
By Turner et al., U.S. Pat. Has been improved.

Since the construction of the digitizer in the plane of the resistive layer has reached the level of technological development which enables its practical construction today, the need for improved linearity, ie a further finishing with regard to its accuracy of performance, has been recognized. While such finishing is possible using computer programming or software attempts, computational techniques generally require software architectures that exhibit complexity such that digital processing is too slow, and microprocessors that are too expensive. It is known to require equipment.

An object of the present invention is to solve the above-mentioned problems of the conventional example, to provide an electronic figure system which is economical, has an improved signal-to-noise ratio, and can be operated at high speed, and an output correction method and a correction method for the system. It is to provide a method for creating a search table.

SUMMARY OF THE INVENTION The present invention features a control that implements the correction of graphical non-linearities using a procedure that is advantageously fast and can be performed using economically costly processing components. To an electronic graphics system and method resulting in. With this system, as a preliminary part of the correction, readings are made in the physical area along each of the resistive or graphic surfaces according to a predetermined geometry. Thus, the signal is adjusted with respect to its signal area so as to obtain the address of the memory as a regularly incremented sequence of numerical values of the calculated physical area coordinates and corresponding address values for the graphic read. In the operation of the system, this memory is accessed by producing the value of the address from a given or real-time read, and the calculated physics such that the interpolation correction procedure is weighted by the actual read. It is carried out using the coordinate values of the physical form. In particular, the interpolation method used is one of the parabolic mixing algorithms, which is one attempt for a two-dimensional interpolation method.

Another feature of the present invention is an electronic device including a structure defining a graphic surface and a moveable locator proximate to the surface for selecting interactions that directly affect the surface to cause deviations in position signals. The provision of a dynamic graphic system. The processing circuit is responsive to the position signal to obtain a position digital signal. A pre-reserved of the physical area obtained as a corresponding value with the position-selected digital signal of the signal area and adjusted to ensure a certain regular increment sequence of the values of the addresses in the signal area. A memory is provided for holding the calculated physical area coordinate values reserved for each position within a predetermined grid of positions. A controller is provided which responds to each received position digital signal to obtain a corresponding address value. The controller accesses the memory at the value of the address, retrieves the coordinate value of the calculated physical area corresponding to the address, and searches the coordinate value of the physical area corresponding thereto by the two-dimensional interpolation weighting method corresponding to the digital signal of the received position. Adjust the calculated physical area coordinates of.

Another feature of the invention is that certain surfaces are selectively accessed,
In an electronic graphics system that produces an electrical signal that is processed to produce an output corresponding to this accessed position, the coordinate value of the physical region obtained as a value corresponding to the selected output of a signal region. For each position within a predetermined grid row of pre-established positions of this physical region which is adjusted to establish the value of the address of some regularly incremented sequence in the signal region. Providing a memory for reserving, obtaining a value of an address from a given output, accessing the memory at the address value to obtain a coordinate value of a calculated physical area corresponding thereto, The calculated coordinate value of the accessed physical area of
Outputting a corrected output to produce a corrected output, adjusted by its two-dimensional interpolation weighting corresponding to the given output, to produce coordinate information representative of the position on the accessed surface. To provide a method of correcting one value with an output consisting of:

Another feature of the invention is that a graphical surface of a known geometrical shape is selectively accessed by the locator to produce an electrical signal that is processed to produce an output corresponding to the physical location of the locator. In an electronic graphic system, in a physical area, a grid row having a physically positionable position on the surface is determined, and in a signal area, electrical information relating to the position of each row of the physical area is determined. Generating a signal and a corresponding output in the signal area, obtaining a regularly incremented sequence of address values, determining the coordinate value of the physical area corresponding to each address value, and the corresponding address value The coordinate value of the physical area is recorded in relation to the physical area, a correction address value is obtained from the certain output, and the physical address corresponding to the correction address value is obtained in the correction address value. The memory is accessed for the coordinate values of the physical area, and the value of the coordinate value of the physical area is adjusted by a two-dimensional interpolation weighting method to obtain the corrected output. To provide a method for correcting the value of some of the outputs relating to changes in the surface, which comprises producing a pair of coordinated information representative of the physical position of the locator.

Yet another feature of the present invention is that a look-up table maintained by a memory used to correct the output of a position within a corresponding signal area by an interpolation technique to access a location within a physical area of a resistive surface. A method of generating collects a set of input data from a response surface that characterizes the physical and signal domain of the surface, the input data as a maximum and minimum signal domain value for the first and second coordinate directions. A set of boundaries, a first of which is an indexable value of regularly incremented addresses extending between values of the maximum and minimum signal regions corresponding to the first and second coordinate directions, respectively; Obtaining a second set, resulting in a first evaluation of the value of the coordinate position of the physical region on the surface corresponding to the addressable value of the address for each of the first and second coordinate directions; And the second coordinate direction The value of the coordinate position of the interpolated physical region for each of the above is obtained from the first evaluation value and the approximation of the set of said input data, and in combination with the discoverable value of the address of the corresponding signal region, in memory Of the interpolated physical area is provided.

Therefore, the present invention comprises an apparatus, a system, and a processing method for the structures, combinations of components, steps, and configurations of respective parts, which will be described by way of example in the following detailed description.

The nature and purpose of the present invention will be better understood with reference to the following detailed description in connection with the drawings.

The following disclosure describes an electronic graphics device in which the resistive surface of a digitizer or tablet is energized by an AC power source, as opposed to the use of a power source in a stylus or tracer, which illustrates a first embodiment of the present invention. However, it should be understood that, with the exception of the selection of the energizing frequency, the same structure and circuit as described herein can be used for its form. The above embodiments in which the resistive surface itself is energized by an AC power source provide enhanced capability for improved signal to noise ratio characteristics. When this signal-to-noise ratio is improved, the effects of otherwise detrimental noise can be avoided and the more desirable energizing frequency can be selected for system operation.

As a preliminary consideration of the present system and method, reference is made to FIGS. 1 through 3 where an idealized one-dimensional model of the digitizing technique of the first embodiment is shown. In FIG. 1, a graphic surface 10, such as a resistance sheet made of indium tin oxide, is designated by 10, and a dielectric material designated by 12 is arranged thereon. Electrode 14 is V _o from the line 16
The electrode 15 is connected to the AC power source shown by, but is grounded via the line 17. A locator, such as a stylus or tracer 20, is located adjacent the resistive layer 10 at any location and acts to pick up a voltage output on line 21 such as the voltage labeled "Vsense" by capacitive coupling. Although the circuit of equality for this idealized one-dimensional model is shown in Figure 2, in which is shown the resistance layer 10 as the resistance, the distance of the stylus 20 from the edge of the nearest resistor to a supply V _o is Represented as "X", electrodes 14 and 15
The distance between is represented as "D". The residual resistance component of layer 10 from the voltage energizing source to position X can be expressed as: In other words, the distance from the location of the stylus 20 to the opposite electrode 15 can be expressed as follows: XR / D That is, the corresponding idealized value for (1-X / D) R Vsense is shown in FIG. 3 as a straight line as shown by curve 24.

The corresponding one-dimensional model for the above embodiment of the invention in which the bias from the voltage source occurs through the stylus is described in detail in the aforementioned US Pat. No. 4,456,787.

In order to obtain a signal representative of a coordinate pair relating to the position of the stylus or tracer 20 on the resistance surface 10, a measurement of the voltage Vsense is made along the orthogonal axes indicated by x and y. Using the switching operation, the application of a voltage source, such as via line 16 as shown in FIG. 1 and grounding by line 17, is reversed for each point in the X, Y coordinates. In this way, the voltage ratio of the difference and the sum is determined by the value obtained for each x and y coordinate, and the signal of the coordinate position is obtained.

In FIG. 4, the digitizer device is indicated generally by 28. The device 28 incorporates a switching procedure for obtaining the coordinate position of the difference and sum ratio. In the same figure, a resistance sheet 30 is shown which is accessed by a locator which is present as a stylus or tracer 32 at the point (x, y) which is rectangular. The resistance sheet 30 is shown as having axes x ⁺ and x ⁻ , and axes y ⁺ and y ⁻ , with the point of intersection therebetween approximately at the center of the rectangular sheet 30.

This coordinate system is +1 to -1 in both x and y directions.
If it is shown in the range up to, some coordinates (x, y)
Under a procedure in which an alternating voltage source, i.e. a varying energizing source, is first applied in one coordinate direction to one edge of the resistance sheet while a ground reference voltage is applied to the opposite side, It can be determined by measuring the value of the voltage picked up by the stylus or tracer 32. The procedure is then reversed from the original coordinate direction and the combined reading is used to determine one coordinate. This procedure is then carried out in opposite coordinate directions. For example, opposite x simultaneously ^- current source that alternates between the ground voltage is applied to a time when applied along the coordinate side of x ⁺ sheet 30, optionally indicate that the output of the stylus 32 is represented by Xplus, alternating current source to the sheet 30 x ^- added along the side and the opposite side x ^- signal when obtaining the opposite condition to which the ground voltage is applied to the optionally XMINUS, and the signal source that alternates the resistive sheet 30 y ⁺ added to the side and opposite or y of the ^- signal at tracer i.e. stylus 32 when the ground voltage is applied to the YPLUS next, ground voltage along the side of the sheet 30 represented by the y ⁺ coordinate signal of the pair added While an alternating current source is applied to the y ^- side of resistor sheet 30 during
The signal indicated by MINUS is obtained. For example, these signal values can be used with ratios that define the difference and sum coordinates to obtain a position signal for any position of tracer 32 on surface 30 as follows: That is, position x = {(XPLUS)-(XMINUS) / (XP
LUS) + (XMINUS)} Position y = {(YPLUS)-(YMINUS) / (YP
LUS) + (YMINUS)} Allows one set of coordinate regions, ie, the resistance sheet 30 side, eg, y ⁺ and y edges, to be “floating” in an electrically isolated state during any data collection implementation Will be
Boundary regions on opposite sides, eg on the x ⁺ and x ⁻ sides, can be actuated by alternating ground voltage and alternating current sources. The application of an alternating signal and the addition of a ground connection are made by means of contacts, which are rather long but are provided as spaced pads placed along the boundary. FIG. 4 illustrates at 34 an array of four such pads or contacts along the x ⁺ boundary,
x ^- a is shown in the opposite side of the array of such pads 36 in the boundary region. Correspondingly, four remote pad or contact of the array along the boundary region indicated by y ⁺ is shown at 38, y ^- corresponding array of connections or pads along the border region indicated by the Indicated by 40.

Each contact or pad in the array 34 in the x ⁺ boundary region is coupled to one side of the array's single pole, single throw analog switch. Similarly, each pad or contact of array 36 in the x ^- boundary region is coupled to a corresponding single pole, single throw analog switch of that array, generally indicated at 44. Correspondingly, each pad or contact within array 38 at the y ⁺ boundary region is coupled to a single pole, single throw analog switch of that array, generally indicated at 46, but located on the opposite side. Array 40 y ⁻
Each boundary area contact or port is coupled to a corresponding single pole, single throw analog switch of its array 48.

An AC source for energizing the resistive surface 30 is shown at 50 having an output on line 52 extending through line 54 to the input side of two single pole, single throw analog switches 56,57. Switch
The output side of 56 is connected to the bus 58a, which is further connected to the array 4
Extend together for the input side of each analog switch in 6, 42. In contrast, the output of analog switch 57 extends through bus elements 60a and 60b to the common input side of the analog switches in arrays 44 and 48.

The ground voltage ensured to operate the resistance sheet 30 with a built-in digitizer is the line 62 which extends via the line 64 to the input side of the two single pole single throw analog switches 66, 67.
Obtained from The output of switch 66 is coupled to bus element 58b which extends through element 58a in common with the inputs of the analog switches in arrays 42,46. Similarly,
The output side of analog switch 67 is coupled to bus element 60b, which is further coupled with the cat power side of the analog switches in arrays 48,44.

All of the above analog switches are actually blocks.
It is energized by a logically compatible voltage signal appearing at the output of a central controller which includes a microprocessor shown at 70. Therefore, by operating an appropriate signal through the lines 72 and 73 indicated by "X CONTROL",
All switches along the x-axis, such as in arrays 42 and 44, can be opened and closed simultaneously. Similarly, the controller 70
Actuating signals from lines 74 and 75, labeled "Y CONTROL," can be activated to open and close all switches on the y-axis as shown in arrays 46 and 48. The control unit 70 also controls the switches 66, 67 with "PLUS CO
The signals on lines 76 and 77, labeled "NTROL", can be simultaneously forced into the de-energized state. By this operation, the AC source via the array 46 of switch of y ⁺ side may be added to the bus 58a, also the opposite side of the y ^- the array 48 of switch via the bus 60b to the ground at the same time Can also be combined. Similarly, the controller 70
Is the line 78 indicated by "MINUS CONTROL",
The actuating signal flowing to 79 causes actuation of the switch 57 and the passage of the signal of the AC source 50 to the array 44 of x ^- switches via the bus 60b, but at the same time via bus 58b to the array in the x ⁺ boundary region. Ground switch 42. Output from controller 70 "X CONTROL",
By alternating "Y CONTROL", the opposite mode of operation can be obtained. In this regard, reference is made to FIG. 5 where the mode of operation for carrying out one measurement cycle is shown in timing diagram form. According to this, the line XCONTROL has the corresponding ON signal PLUS CON on lines 76, 77 as indicated by 82 in the figure.
At the same time as TROL, an ON state, that is, an operation signal is generated, and 1
In the first quarter interval of one measurement cycle, it produces the signal X PLUS as represented by curve 84. Similarly, the ON state for signal X CONTROL as shown at 80 in the figure is generated in combination with the corresponding ON signal MINUS CONTROL on lines 78, 79 as shown at 86 in the figure. The signal X MINUS generated in this way
Is shown by curve 88 and represents the second quarter of the measurement cycle. The third quarter of the measurement cycle is the ON or operating state Y on lines 74, 75 as shown at 90 in the figure.
The CONTROL hypothesis is shown to produce the signal Y PLU92. Simultaneously with this ON state shown at 90 in the figure, the lines PLUS CONTROL 76, 77 produce an activation signal as indicated by the ON state at 82 in the figure.
Finally, the signal Y MINUS94 is generated in the fourth quarter and the line MINUS94 as shown at 86 in the figure.
Corresponding operating states in CONTROL 78, 79 ie O
In combination with the N state, Y CON as shown at 90 in the figure
The operating state, that is, the ON state, is forced on the TROL lines 74 and 75.

With the configuration shown above, the source 50 is first added to one boundary, then to the opposite boundary in the x-axis direction, and then the same configuration is applied to the y-axis direction. However, the unused switch in this coordinate direction is opened to also allow opposite boundary pairs to "float" and avoid phenomena such as pin cushioning. With the use of the bus connections described above, the number of switches that would otherwise be required to implement such switching logic would require two discrete switches for each contact or electrode in the array in its border area. Significantly reduced compared to active switching systems.
This desired reduction in the number of switching elements is actually effective because the number of switches connected to the required bus remains the same and the size of the resistive area supporting the tablet, such as 30, is increased. is there. Generally about 30 x 30
For tablets with a surface size of 12 cm (12 x 12 inches), the number of switches required is 40% smaller than the conventional structure, and this reduction in number increases the size of the tablet. It becomes more remarkable as it does.

In general, the 30 such resistive layer has a resistance value that is selected at about 6.45 cm ² (1 square inch) per about 100 to a range of values of 10,000. However, even lower resistance values are desirable because of the often encountered interference phenomena, such as interference from an operator's hand or a human part in contact with or near a surface. However, from the standpoint of avoiding stray capacitance or ambient noise input phenomena, it is desirable that this resistance be as low as possible, with 250 to 500 Ω / in 2 being considered most appropriate. Frequency selection for source 50 is also a consideration with regard to avoiding interfering frequency levels most often encountered in typical use of digitizer devices such as 28. As a first consideration, energizing signals below about 5 KHz are tracer or stylus 32 and resistance surfaces.
It is not desirable because the capacitive coupling with 30 is very small. However, with energizing signals above 2 MHz, the cost of electronic components handling such frequencies is unreasonably high. Furthermore, in the intermediate frequency range, for example around 200 KHz, there is interference from equipment normally associated with the digitizer environment. Thus, although harmonics from a visual display terminal (VDT) of about 200 KHz have been evidenced, such disturbing signals result from sync pulses and the like.

In general, the controller in block 70, which includes a microprocessor and associated components, has features such as processing signals in digital format. However, the inputs to the controller 70 from which the coordinate pair digital information is to be generated are pre-processed in analog form. Thus, the locator or pickup 32 has a shielded cable 96 extending to the input side of the impedance matching circuit shown in block 98 and the associated pre-amplification stage 100.
Combined by The pre-amplification stage has its feedback and R on the input side modified to obtain the amplified position signal for optimum input matching from this stage.
It has a C circuit. In fact, the distributed resistance of the sheet 30 and the capacitive coupling defined by the gap in the pickup 32 provide the transfer function of the RC circuit. In order to achieve the optimum coupling of the signal output of the circuit, it is necessary to send the signal output of the circuit to the corresponding matching circuit where the transfer function is reversed.

Since the quality of the coupling between the pickup 32 and the resistance sheet 30 varies with the type of pickup used, it is further necessary to obtain the consistency of the received position signal for uniform processing. For example, it has been found that if the tracer or cursor comprises a flat receiving ring placed in the vicinity of the coordinate point of interest, the resulting coupling state is excellent. Conversely, when using a pointed stylus as a locator, a slightly poorer quality bond is obtained. Therefore, the cable for the preprocessing signal stage
Appropriate coding of the mounting of 96 can result in automatic attenuation of the received signal corresponding to the selected pick-up, and such modifiable or selectable attenuation of the received signal is indicated at block 102. Be done. Simultaneously with the adjustment in stage 102, the signal at this time is filtered in a bandpass filter shown in block 104, which produces a filtered position signal constructed according to the frequency of the energization at source 50.

Due to the change in distance on the surface of the resistance sheet 30 of the tracer or pickup 32, the system causes the automatic gain control shown in block 106. This automatic gain control for the signal is controlled from the control mechanism shown in block 70 via the associated elements shown by line 108. Following this automatic gain control stage 106, the resulting gain controlled position signal is converted to a DC level as indicated by block 110. At this time, the signal is blocked
Sent to the input side of the sample and hold circuit shown at 112. The circuit 112 acts to capture the voltage applied to its input, slightly diminishing the action of the controller 70 contained in the microprocessor or the noise level of the digital elements of the system during the capture of the initial analog signal. It gives rise to what is called "software degrees of freedom", which can be significantly reduced. This allows the analog components of the system to operate in a more noise free electronic environment. Therefore, when DC level data (DC level position signal) is generated, such level information is converted into a digital binary value by the A / D conversion circuit shown in block 114. The sample / hold circuit 112 is searched. The digital value (digital signal of the position) thus generated in the circuit 114 is supplied to the controller 70 as shown by the line 116.
To a multi-lead bus.

At the same time as receiving the digital position signal from the bus 116,
The control function, shown at block 70, provides the previously mentioned difference-to-sum ratio formation, allows for widening deviations, and corrects for non-linearities caused by changes in resistive layer 30. This latter corrective action is sent exclusively through a two-part system, where each point along a grid-like row of positions that can be physically found to obtain a digital position signal in the signal domain. The resistive surface 30 is first tested in the physical area by a locator type device at. These digital position signals, which can be considered to be in the signal domain, are then adjusted to ensure some regularly incremented sequence of address values within the same signal domain. Indeed, a grid is formed in the signal domain which covers the actual output found in the signal domain. Then
For each of these address values, the coordinate value of the respective physical area is calculated and placed in a read-only memory in a look-up table form for each of the above address values. This read-only memory is then accessed in the correction subroutine by the microprocessor component of controller 70. Therefore, the control device can access the memory at any position of the locator 32 and can obtain the coordinate value of the calculated physical area. The controller then performs a two-dimensional interpolation weighting operation on the coordinates of these calculated physical regions according to the given or actual signals received from locator 32.

A time interval that is fully acceptable for the intended digitizer or related application because the calculated physical area coordinates and address values are obtained and placed in memory as part of the manufacturing of the system (offline). The correction operation can be carried out by means of a simple computational process, which requires only relatively inexpensive microprocessing elements within. The resulting coordinate pair or digital data signal output is the line 11
It may be provided sequentially at the sequential ports shown at 8 or in parallel as shown at line 120. These outputs are combined with the host computer mechanism.

As previously indicated in the text, the resistance sheet 30 is first for the digitizer device 28 to be energized by an AC source.
The structure is as shown. However, the system also operates when the cable 96 of the pickup 32 is coupled with the source 50 to produce a signal at the required coordinate position.
Due to operation in such an architecture, line 52
Are connected to the analog or signal preprocessing elements beginning at block 98.

In FIG. 6, a hand held locator or tracer is shown generally at 130. Tracer 130
Included is a transparent plastic substrate plate (not shown) nestably secured within an integrally formed top housing portion shown at 132. For example, the front portion 134 of a transparent substrate formed of transparent acrylic is configured with a cross hair cursor and a peek circle 138. The peek circle 138 and the cross hair cursor help to assist the operator in placing the device 130 in place on the resistance surface 30. A printed circuit board is adhered to the base plate member, the bottom of which is for reception in the case of the first embodiment described above or for transmission of an AC signal in another embodiment of the invention. It includes an annular ring located below the rim 140 that can be used for this purpose. The upper surface of the printed circuit board includes a shield cable forming a part thereof for connection to an array of fingertip-operated switches 142, as well as leads connecting the annular ring to the leads. Each switch of array 142 may be provided, for example, as an elastic, over-centered type that has a hard feel when pressed. The tracer 130 further includes a light emitting diode 144 shown at such a time that the data representing the coordinate pair is received and accepted by the mechanism of the host computer with which the device 28 is operatively associated. The switch 142 can also have various displays, for example, indicating the generation of coordinate data for a series of different colored prints. Due to the size of the annular ring installation portion 140, in order to avoid distortion due to edge effects, etc., the resistance sheet 30
It will be appreciated that the write active area for must be located approximately 4 cm inward from the actual edge of the ITO layer.

8A showing details of the switching system described in connection with FIG. 4 to show the above circuit in particular detail.
See Figures and Figure 8B. In the figure, the same component numbers are assigned when appropriate. The fluctuating signal generated in connection with the AC source 50 is obtained from the controller 70 as a square wave and is generally 164 via the connector 162.
Is sent to the signal processing circuit indicated by.

In the preferred embodiment in which resistive surface 30 is energized, the frequency value represented at this connector 162 is approximately 211 KHz.
Becomes On the other hand, if the resistive surface 30 is used in connection with a mode in which the biasing condition occurs via a stylus or tracer, then this frequency value will necessarily be doubled. The initial stage of circuit 164, as shown at 166, uses an operational amplifier 168 formed by capacitor 170 as an integrator which serves to remove the initial Harsh or harmonic content from the square wave, which is typically 0-5V. To do. This step also acts to center the waveform symmetrically at + 2V.
The signal so processed is then passed through resistor 172 to a bandpass filter stage, generally indicated at 174.
For this reason, the filter stage 174 has an operational amplifier 176 configured in a typical filter scheme using capacitors 178, 180.
including. The bandpass filter stage, at this location, first removes all harmonics and then signal processing circuitry to remove the DC bias that may result from the first stage 166.
Used at 164. Generally, it has a Q of 10 centered around the 211 KHz base frequency input at connector 162. The output of stage 174 on line 182 is generally
Sent to the opposite side of the current drive stage shown at 184.
For example, when provided as a model LHOO2 current driver circuit, stage 184 acts to drive the impedance of resistive surface 30 and actually acts as a buffer stage. The output of drive stage 184 is passed through capacitor 186 and line 185 to
It is shown coupled from lines 185, 187 to the first two of said switching stages 56, 57. Switch 56,
57 is shown as an analog version, and in its quad package shown at 188, the switch 66,
Combined with 67. The control for the switch 57 is a control mechanism.
Corresponding control for switch 56 is provided by the selective addition of a logically compatible voltage signal from 70 through line 78 through connector 190, but line 76 carrying the signal from controller 70 through connector 192. , 77. Similarly, switch 66 is selectively grounded via line 191 and controlled by the addition of a logically compatible voltage signal from line 78 coupled to connector 190 via line 78. Finally, switch 67 is selectively grounded via lines 193 and 191 and controlled via line 192, which is further coupled to controller 70 via connector 192.

Referring to FIG. 8B in more detail, the AC energizing signal is selectively sent to line 194 via switch 56 and line 58, and then to the immediate contact pads 34a-34d (FIG. 6) as shown. It will be appreciated that the outputs are coupled to the switching outputs of switch array 42. Switch array 42 selectively receives logically compatible voltage signals from controller 70 via connector 196 and mating lines 73, 72. It will be recalled that such a switching action energizes the x ⁺ coordinate boundary region to receive an AC energized condition. Similarly, switch 57, y ^- in connection with the generation of the coordinate information, quad energizing signal via line 60a and 197
Given to Switch Array 48. Control over the array of four switches 48 is provided by controller 70 via lines 74, 75 and its connector YCONTROL198. Similarly, line 60a is routed to line 199 and the input side of switch array 44 to cause the x ^- coordinate energization of resistor sheet 30. Switch array 44 is further controlled from lines 72, 73 and an input XCONTROL as shown at connector 196 from controller 70. Switch
Grounding for arrays 44 and 48 is from controller 70 to connector 19
Provided by line 60b originating from switch 67 which is selectively activated via 2. 9A-9C, the analog signal processing elements of device 28 are shown in detail. These figures should be considered adjacent to the parallel relationship in their alphabetical order, as indicated by the label attached to them. The output side of the tracer or stylus, shown as pickup 32 in FIG. 4, is connected to connector 200 and line 202 as shown in FIG. Of the combinational circuit of FIG. The pre-amplifier stage 100 has an operational amplifier 206 having RC circuits 208, 210 in each of its feedback and input paths.
It consists of As mentioned previously, it is important to match the impedance between the signal pickup device and the input side of the analog circuit. According to one embodiment of the present invention, the desired signal-to-noise ratio is achieved by the pickup 32 operating in receive mode because the pickup device itself is a high impedance device and is driven by capacitive coupling with the resistive surface 30 itself. To be done. Conversely, when the energizing signal is generated from the tracer or stylus, the capacitive coupling in the resistive surface creates a high impedance, which is the voltage drop associated with the system in which a relatively small signal is generated at resistive surface 30. Represents a high impedance that goes into the state. This causes unwanted signal loss on both sides of the coupling.

With respect to the pre-amplified signal occurring at the output line 212 of stage 100, the coupling between the resistive surface 30 and the stylus does not characterize as a corresponding coupling state using a tracer as described in connection with FIG. Some selective damping is required. To produce this selective attenuation condition, a type 4501 analog switch, such as 214, is used. The input to this circuit from line 212, which is sent to either input pin Y0 or pulse Y1 coupled to resistor 218, is provided through resistor 216. For this reason, if a tracer as described in connection with FIG. 6 is provided, the line 220 extending to the A0 terminal is connected to the line 222.
Not grounded, but a + 5V signal is applied from line 224 to line 220, resulting in the reception of the signal from line 212 through terminal Y1 to be attenuated accordingly and applied to output line 226. On the other hand, if using a stylus, line 220
Is grounded via connection 222 and a signal which is not attenuated to feed output line 226 is received on line 212 to terminal Y0.

Output line 226 is coupled to bandpass filter circuit 104 via capacitor 228. On the other hand, the circuit 104 includes a high pass filter stage 230 that provides a very sensitive leading edge filter that is coupled to the band pass filter stage 234 via a capacitor 232 in a cascade fashion. The stages 230, 234 are of a one-pole construction and the output of each stage in line 236 is fed to a filter stage 238 which is constructed in substantially the same manner as that of the filter stage 174 (FIG. 8A) described above. To be Generally, tier 2
30, 234 and 238 are configured in a preferred embodiment of the present invention, much like the type LF356 arithmetic amplifier. However, if the frequency is higher, eg 400 KHz
Range is used (for configurations where the tracer or stylus produces an alternating signal to the resistance sheet 30)
Use of a type 2625 arithmetic amplifier is preferred.

The output of bandpass filter 104 on line 240 is sent to the input of automatic gain control stage 106 as shown in FIG. 9B. This automatic gain control stage is used because of the wide dynamic range of the signal that occurs at the input to the analog portion of the circuit. The vibration range of such a signal is determined by the tracer or stylus on the resistance sheet 30 during use.
It is often caused by a change in height of 32 and a change in insertion time of a dielectric material such as paper between the pickup device and the resistance sheet 30. Since the signal will eventually be converted to digital form, some gain control is required.
To perform this gain control, a selector circuit 242, which may be, for example, type 4051, is used. Input terminals Y0-Y7 of circuit 242 provide taps to resistor circuit 244 to which the input to line 240 is coupled. By providing suitable binary control at terminals A0-A2 from lead 246 and connector 248, controller 70 taps the resistor circuit at any of input terminals Y0-Y7, thus selectively dampening. Output the output signal line 25
Occurs at 0. Circuit 242 also includes line 230 for measuring deviation.
It can also be controlled to force a ground voltage signal on.
It will be appreciated that due to the hysteretic characteristics that become apparent in devices such as 242, the program to get the appropriate taps is adjusted accordingly.

The output line 250 containing the gain adjustment signal is coupled to the input side of a precision full wave rectifier circuit shown at 118. Rectifier circuit 110
The first stage 252 consists of two stages including diodes 254, 256 which produce half-wave rectification at its output. This half rectified signal is then sent to a second stage 258 with feedback including line 260 and resistor 262 for full wave rectification. The averaging operation is performed by providing the capacitor 264.

Stage 110 further includes a diode 268 and an offset bias circuit 266 including resistors 270, 272. This circuit is coupled to line 260 and serves to create a positive bias at all DC levels in the analog signal processing systems described thus far. All active elements of the system have some offset voltage that will cause some error. Since this voltage has a negative value and the analog / digital converter device which encounters after that can only convert a positive value, the latter positive value is secured by this configuration. It becomes possible in the whole control program of. For example, the line
The input at 204 can be grounded and the resulting voltage eventually converted to some digital level that can be error-corrected and collected by some subtraction. Steps 252 and 258 are of known type LF356
It can be configured by using the operational amplifier.

The output on line 274 of converter circuit 110 is
Routed through a two-pole low pass filter, generally designated 276, consisting of resistors 278,280 operating in conjunction with 282,284. The output thus filtered is then fed to a sample holding circuit 112, which has a sample and holding integrated circuit 286 as its main component, which integrated circuit is provided, for example, as type LF398, It may be selectively energized to hold a signal at the input from line 288 which extends to controller 70. The output on line 290 of the sample and hold circuit 286 effectively acts as an operating stage to isolate the relatively noisy activity of the system microprocessor or digital components from the generation and reception components of the analog signal or position. 9th C
It is sent in a controlled manner to the input terminal R27 of the analog / digital conversion circuit 292 of the conversion circuit 114 as shown. The converter 292, which is energized at levels of ± 12V, initiates the conversion operation of the signal on line 240 upon receipt at the SC terminal of the appropriate conversion start signal from line 294. Line 294 is held at ± 12V by pull-up resistor 296, this level is further
It is buffered by a type 74LS38 open circuit collector buffer 298 which receives its common input from line 300 which extends to a flip-flop 302 which may be a 4HC74. The clear terminal CLR of flip-flop 302 is maintained at a logic high by line 304, which device has its input line 306 coupled to controller 70 as indicated by connector 308.
Is triggered by the conversion start signal at. Flip-flop 302 functions to synchronize converter 292 with the clock of controller 70, which is from controller 70 to flip-flop as shown by connector 310 and lines 312, 314 extending to the opposite input side. This is done by giving an input signal of 102.4 KHz.
The signal provided on line 294 is not a continuous logic level because the signal that initiates the conversion is cleared by the continuously running clock on line 314 which is activated in flip-flop 302. Line 312 also has an open collector buffer 316 and a pull-up resistor coupled to + 12V.
It will be appreciated that the coupling condition with line 318, which is always held high by 320, provides a clock input to converter 292. This 12-bit converted output of converter 292 is present on its Q0-Q11 parallel outputs as shown by line array 322. The output lines within array 322 are individually converted to 5V logic by a Type 74C901 buffer coupled thereto as in the array shown at 324. The resulting parallel 12-bit output is returned to the controller 70, as indicated by connector 328, on the data bus 32.
Sent to 6. The output terminal Vcc on line 330 takes an active logic low at such a time that conversion by converter 292 is complete, which active logic low from 12V to 5V due to field effect transistor 332.
Converted to V logic level. Transistor 332 has a signal line 334 which extends to controller 70 as shown by connector 336. Note that line 288 is coupled to the same connector via coupling with line 334. Transistor 332 may be provided, for example, as type SD1117N. Line 294 takes an active logic low, but terminal Vcc on line 330 follows this when it sees the start of conversion and goes high.
Simultaneous with the conversion to a lower level by transistor 332, the resulting signal is returned to sample and hold circuit 286 to hold the signal on line 290. Upon completion of the digital conversion, the signal on terminal Vcc on line 330 takes an active, logic low, which is asserted on line 334 and polled by controller 70. In effect, this is a data ready signal. The same logic level change is caused by the line 288 and the sample case holding circuit 286.
Proved in.

When the resistive sheet 30 is used in conjunction with an active area format of, for example, about 30 × 30 cm (12 × 12 inches), 13-bit A / D conversion is required for the 12-bit converter element 292. In order to generate this 13 bits, the internal 8V full scale signal on the input line 290 is converted to 12 bits so that it is within the range of 0 to 4V or 4 to 8V. Processed by criteria. Controller 70 determines if the signal on line 290 is less than 4V and, if so, the 13 bit is zeroed. If the signal on line 290 is higher than 4V, another conversion is made, in which case the reference in converter 292 is changed to produce 13 bits. This determination is made using the internal resistance in converter 292 as accessed from terminals R25 and R26. These terminals are tied to either ground or + 12V depending on the need for the 13th bit in the higher voltage range. Controller 70 determines if the input on line 290 is higher or lower than the above half scale or 4V. At the same time, a signal occurs on line 338 from connector 340 to one side of comparator 342 of type LM339. Comparator 342 produces a level that varies from the computer logic to the ± 12V level of converter 292. Thus, when the signal is at the negative input to the converter 342, its gate will
A type J111EET coupled to the output side of the converter 342 via 46 is energized and connected via line 348 to the converter.
292 is biased to produce + 12V associated with the resistors coupled to terminals R25 and R26. Conversely, the internal resistance is grounded by the signal on line 338 sent to FET 350 as a result of the signal on line 352.
As will be appreciated, the opposite input to converter 342 is regulated by resistor 354 and diode pair 356 connected thereto via line 358.

In FIG. 10 a small circuit for energizing the light emitting diode 144 in the tracer embodiment shown in FIG. 7 is shown. For example, LED 144 is a type MPS2907 whose emitter is collected at + 5V as shown in line 362 and whose base is coupled to controller 70 via line 364 and resistor 366 as shown by connector 368. Good. The emitter of transistor 144 is coupled to ground of the power supply via resistor 370, while the base coupled line 364 is coupled to + 5V via pullup resistor 372. Obviously, when line 366 goes low active, LED 144 is illuminated.

11A-11C, the digital elements of the digitizer 28 circuit are shown in particular detail. These figures are placed in adjacent positions in alphabetical order as indicated by their combined label. 11th in the middle first
In Figure B, the microprocessor under which the circuit operates is shown at 380, and the microprocessor shown is a type 8085, but a slightly improved capability type 8088 is considered desirable for this application. To be Microprocessor 380 is driven from a crystal controlled oscillator 382 which obtains an output of 6.5536 MHz at its X1 and X2 terminals. As a result, the clock terminal CLK is
It produces a corresponding output on line 386 which is coupled to the input of counter 386 which divides by four. Counter 386 of 4
One of the two outputs is tapped at line 388, which is coupled to the connector 162 (shown here with a '), and energized to the resistive surface 30 via a tracer or stylus 32. Is about 40 for the energized filter stage shown at 164 in FIG. 8A in an embodiment of the invention where
Produces a 9.6 KHz square wave input. On the other hand, in the first embodiment, the counter 386 taps on line 390 and the same connector 162 which extend to line 392 to produce the 204.8 KHz frequency signal required in the preferred embodiment where resistive surface 30 itself is energized. Can be taken. Line 390 also
It is fed to the input side of another divide-by-4 counter 394, the output of which is tapped on line 396 which extends to connector 310 described in connection with flip-flop 302 in FIG. 9C. Output signal frequency at connector 310 is 102.4KH
Recall that it is z. The other output of counter 294 is provided on line 398, which is, for example, type 815.
A composite random access memory (RAM) and timer circuit 400 (Fig. 11B) provided as 5H, "TIME"
RIN ”. Complex circuit 400 also provides 12 bits of I / O port functionality for use by microprocessor 380. To bring about that control association,
IO / M, ALE, RD, RD, WR, and RST commonly shown in composite circuit 400 and microprocessor 380
The terminals are commonly connected. Note that these common connections 380 are coupled to the + 5V power supply through an array of discrete pull-up resistors 401. Circuit 40
0 RAM input terminals PA2-PA7 and PB0
.About.PB6 are coupled to bus 326, which in turn is coupled to connector 328 for receiving the parallel digital output of analog to digital converter 292 (FIG. 9C). Address / data terminal AD0 of circuit 400
AD7 is coupled via a common address / data bus 402 to the corresponding port with microprocessor 380N9 as well as the corresponding data ports D0-D7 of Universal Asynchronous Receiver / Transmitter (UART) 404. Circuit 40
0 terminals PC0 and PC1 are connectors 368, 34
Combined with 0, it also energizes LED 144 (FIG. 10) to provide converter 292 with bit 13 information. As mentioned earlier in the text, the LED 144 is only activated when a symbol pair signal is sent to the host computer.
Bus 402 is shown to continue to an array of discrete pull-up resistors 406 coupled to a + 5V power supply (Figure 11A). Bus 402 is also a connector line up to the continuation of bus 410
Combined as indicated by 408, one element of which leads to an output terminal 00-07 of a programmable read only memory (PROM) 412. The PROM 412 can be provided as a type 2764, for example. The device is further equipped with a writing terminal ▲ ▼ for the microprocessor 380.
It is energized at its OE terminal from line 414 extending to. Higher level address of PROM412
Terminals A8-A12 are coupled by bus 412 to corresponding address terminals of microprocessor 280, but at a lower order address terminal A0.
.About.A7 are coupled by bus 418 to each terminal 1Q-8Q of the address latch or buffer 420.
Latch 420, which may be, for example, a Type 74HC373, is shown as having its data terminals 1D-8D coupled to bus 410 through bus 410 to microprocessor 380. The G (enabled) terminal of the latch 420 is coupled to the read terminal ▼ of the microprocessor 380 via line 422. Latch 42
A 0 is required in this circuit because the microprocessor 380 has a multiplexed address and the data bus 402 and address information must be retained or captured.

Bus 410 further extends to the Y terminal input of buffer 424, to which the opposite or A terminal input is connected via lead array 426 to the individual switches of dip switch array 428. Note that each lead in array 426 is coupled to a corresponding pull-up resistor in resistor array 430, which resistor is coupled to the + 5V power supply. Individual switches in switch array 428 allow the operator to select various operational characteristics, such as the velocity of propagation of the paired coordinate signals per second.
Therefore, the coordinate pair signal is 1 pair per second, 5 pairs per second, 40 pairs per second.
Can be transmitted at pairwise, etc. speeds. The user may also select a set of mode switches, eg, mode "points", to which coordinate pair information or signals are sent when the operator presses a selected button on switch array 142. In addition, a "stream" mode can be selected in which coordinate pair signals are continuously sent despite the switches in array 142 being turned on. It is possible to select a "switch stream" mode in which coordinate pair information is sent as a stream of coordinate signals when a button or switch in array 142 is pressed, but the transmission of such signals is stopped when the switch is released, You can also select an "idle" mode in which no coordinate pair is sent. Switch 428 can also be set to select an English or metric calibration. In addition, turning on this switch allows the operator to choose to place a carriage return (line feed) or carriage return line feed character as a suffix to the transmission, but the switch ▲ ▼ / BCD selection is a binary number. Or the data converted into the ASCII format.

A similar switch is shown at 432 in Figure 11C. Looking at this switch, the operator can select the baud rate by manipulating the switch labeled 4 so labeled. In the next sequence,
The operator can choose to produce row-by-row data at the trailing or leading edge of the strobe input by manipulating the "data strobe". In the next sequence, the operator can also choose to perform a condition validation. In the next adjacent switch element, even-odd parity can be selected by the operator, but the switch in the next sequence will select the operator with or without parity.
Finally, the switch 432 is the same as about 0.076 or 0.127mm
Allows selection of (3 mil or 5 mil) circle resolution. The latter three switch inputs in the switch 432 are input ports 2A4 and 2A3 of the buffer 434, respectively.
And 2A1. Like buffer 424, buffer 433 may be a Type 74HC244, the output terminal of which is shown coupled to a common data / address bus 402. Buffer 434 port 1
A1-1A4 are also coupled to input lines 436-439 from the corresponding four switches of that array of tracer 130 (FIG. 6). All inputs to buffer 434 are each coupled through a pull-up resistor in array 440 that also extends to a + 5V source.

Bus 402 is also shown leading to the output port of input buffer 442, which may be, for example, a type 74LS244. The input port to buffer 442 is coupled to a line array 444, etc., each line of which is coupled to a + 5V source through a pull-up resistor in that array indicated at 446. The line array 444 processes to provide a parallel connection with a host computer or the like, for example corresponding to and overriding data that may otherwise result from the operation of the switches 424 and 432 previously described by the user. Functions to receive structural or programming data. The parallel output port of this circuit is shown as a line array 448 extending from the connection of output latch 450 with 1Q-8Q. For example, if the type is 74LS273, the latch
The 450 input ports 1D-8D are coupled to bus 402 and, as will be appreciated, this latch produces 8-bit output data for the host computer with which device 28 operates. Immediately before the latch 450 is the input port 1D-8D of another output latch 452 to which it is coupled with the bus 402, as well as various outputs that provide control functions within the system. For example, in the case of type 74HC273, latch 452
Terminal 1Q of FIG. 8B has the same connector number 19 as the Yuni connector shown in FIG.
Acts to send the signal X CONTROL represented by 6. Terminal 2Q of latch 452 is connector 198
And signal Y as shown in FIG. 8B on line 74.
With CONTROL, the former is also shown in the figure. Terminal 3Q is described above with respect to connector 192 in FIG. 8A, and the signal PLUS CONTROL is shown above in which the reference number for that connector is shown.
, But terminal 4Q has connector 190 in the figure.
, And sends the corresponding signal MINUS CONTROL as shown in FIG.
Finally, the terminals 6Q to 8Q of the latch 452 are connected to the 9B
The representation of that connector, as shown by connector 248 in the figure, sends a gain control input to an automatic gain control circuit 242 which is repeated in the figure.

Returning to FIG. 11B, microprocessor 380 is shown to provide the start conversion signal at connector 308 via its direct data out terminal (SOD) as described with respect to FIG. 9C. Similarly, this microprocessor uses a comparator as shown in FIG. 9C.
Serial data input from connector 336 starting at 292 (S
ID) receives the conversion completion signal. The same connector representation is shown in the same figure. An interrupt to the microprocessor 380 is sent from the circuit 400 timing function to line 454.
And via its Type 74LS86 gate 456 at its RST6.5 terminal. The opposite input to this exclusive-OR gate comes from the + 5V source. Similarly, UAR
An interrupt is issued from T404 to the microprocessor 380RST7.5 port to display the reception of 1 byte.
In this regard, the reception ready terminal RX has a line 458.
And terminal 748C332 OR gate 460 to the above terminals. The opposite input to gate 460 comes from line 462, but
This is also another 74LS8 whose input is dedicated from the top lead of the parallel input port lead array 444.
6 Combined with the output of OR gate 464. The signal sent by the lead is ANDed with the + 5V source and sent to the input 1A1 of the buffer 442. Similarly, the upper reset signal input carries a + 5V source on line 466 and the microprocessor 380 terminal input TRAP.
Is shown in FIG. 11C as being sent via line 468 which feeds inverter 470 to.

The element controller or system mapping generated by the microprocessor 380 includes a pull-up resistor array 47.
2 is coupled to the + 5V source via 2 and is also provided from terminals A13-A15 which are coupled to the control input terminals CS1, 1B, 1B, 2A, 2B of the decoder 474.
Decoder 474 is offered as type 74HC139, part 1
Y0 terminal 474 serves to provide a chip select input along line 476 to the CE terminal of PROM 412 (FIG. 11A). Similarly, the 1Y1 terminal of decoder 474 provides a chip select signal along line 478 to chip select terminal CS of circuit 400. Decoder 47
4 1Y2 terminal, UART404 via line 480
Of the chip select terminal CS.

The terminal CS2 of the decoder 474 is coupled to the output of the OR gate 482, one input of which separates from the output of the inverter 486 on line 482, the other input of which is coupled to the terminal A15 of the microprocessor 380 on line 48.
Given by 8,490. The opposite input of gate 482 comes from line 492 which extends to read terminal RD of microprocessor 380.

Terminal 1Y0 of the second group of terminals of decoder 474 is shown coupled by line 494 to the available input terminals of buffer 442 (FIG. 11C), while the next adjacent output terminal 1Y1 is line 496.
Via a corresponding available terminal of buffer 434. Similarly, this second group of terminals 1Y2 is coupled via line 498 to provide enablement to the corresponding available input terminals of buffer 424 (FIG. 11A).

To provide further decoding capability in the present system, terminal 1Y3 of the upper terminal group of decoder 474 is coupled by line 500 to one input of OR gate 502. For example, gate 502 is type 7
Given as 4HC32. The opposite input to gate 502 is obtained from the write terminal WR of microprocessor 380 by a connection via lines 504,506. Line 508
The output of the gate 502 at
Coupled to the clock input CLK of FIG.

Similarly, line 506 is coupled to the input side of another OR gate 510, while the opposite input is provided by line 512 which extends from line 484. Gate 510 on line 514
Output extends to the clock input CLK of output latch 450. The clear terminal CLR of latch 450 is further coupled by line 516 from line 518 to the commonly coupled terminal RST of microprocessor 380, circuit 400 and UART 404. The signal from line 518 is output from inverter 520 before it is present on line 516.
Flipped at.

Microprocessor 380 performs the initialization function at the same time as power is supplied to the system or by the operator turning on switch 520 shown in FIG. 11A. One side of switch 520 is grounded while the other side is coupled to line 522 which extends to terminal RIN of microprocessor 380. The line 522 is a capacitor 5 in the RC circuit.
It is held at the + 5V source through resistor 524 which operates in conjunction with 26. Thus, closing switch 520 allows capacitor 526 to discharge, causing the application of a pulse along line 522. Diode 528 acts to provide protection against transients above + 5V. Resuming power-up is also done automatically with the resistor 524 / capacitor 526 circuit. Obviously, this circuit causes the required small delay.

UART 404 is used to communicate in series with a host computer associated with a serial interface port, shown generally at 118 in FIG. 11B. UART
Input to 404 is from microprocessor 3890 to bus 402
Output to the data input port D0 to D7 from the device is provided at the data transmit port TXD on line 530 and the output is buffered at gate 532 to provide on line 534. UART404
The corresponding serial input to is provided on line 536 which includes inverter 538 and extends to terminal RXD. Below these terminals, conventional initial procedure functions are included. Therefore, the READY TO SEND signal provided at the terminal RTS is stored in the buffer 542.
Given on line 540, including CLEAR T
The OSEND signal is input at terminal CTS from line 544 which is coupled to the + 12V source through resistor 546. Line 544 also incorporates inverter 548. This data terminal output ready signal is provided at the DTR terminal of the UART 404 and sent via the line 550 containing the buffer 552.

As previously mentioned in the text, the baud rate selected for the operation of the UART 404 depends on the switch array 432 (11C).
Selected by the operator in connection with the operation of the components in FIG. This baud rate selection is based on a 4-lead array
It is provided to the AD input side of the baud rate timer 558 via 556. The frequency output from timer 558 so selected is provided on line 560 to the TXC and RXC terminals of UART 404.

Digitizer 28 for giving to some superordinate component
The parallel output port 120 of FIG. 11 (FIG. 11C) requires a select timing input. This select timing input is provided as a data strobe signal on line 562 as shown in FIG. 11C. Line 562 extends from the output of exclusive-OR gate 564 and one input is at the available logic level of line 566 extending from the operator-controlled data strobe select in switch 432. Line 566 is always held at the + 5V source via resistor 568. The opposite input to gate 564 holds the data strobe timing signal from combination counter 572 and inputs it to JK flip-flop 574 as shown in FIG. 11B. The J input terminal of the flip-flop 574 is line 5
It is always coupled to receive the timing output provided to the output latch 450 because it is connected to line 514 via 75 and 576. flip flop
The clock input to the 574 is counter 386 and line 39.
0, 392 (Fig. 11A) and holds the above 104.8 KHz signal. This same signal is provided to counter 572 via inverter 580 and line 582
Its output at 570 is fed back via line 584 to the K input terminal of flip-flop 574. The output on line 584 for this purpose, indicating division by four, resets or initializes flip-flop 574. The output on line 570 is further delayed by a predetermined amount of about 60 .mu.sec to represent the data strobe signal for the host device. Thus, the latch 450 is loaded with data, which is followed by a signal on line 562 indicating that data is available.

When the digitizer receives data from the host device, it sends a data ready signal to this host device, for example array 444.
It can be given on line 586 (Fig. 11C). Line 5
86 leads to the J input terminal of another flip-flop 588 shown in FIG. 11B. Flip-flop 588 is a line 384 that holds the clock output of microprocessor 380.
Clocked from line 590, which extends to the junction with. The K terminal of this flip-flop is grounded and its Q
The output terminal is coupled to the input 2A3 terminal of parallel input buffer 442 via line 592. The clear terminal of flip-flop 588 is coupled to line 574 so that the clear operation occurs in connection with the write command. The flip-flop 558 has a function of holding the data ready signal received from the host computer until the microprocessor 380 can bowl or read the signal.

In Figures 12A-12C, a microprocessor is shown.
The overall control program performed by the 380 is shown diagrammatically. As shown at the top of Figure 12A, the program starts at the same time as the start-up procedure. This procedure can be initiated by power-up, as already mentioned in the text. Further, since the capacitor 526 is charged, the switch 520 can be restarted by an instantaneous operation. Following startup, block 600 of Figure 12A.
As shown, all interrupts in the system are disabled so that the interrupt procedure cannot be performed during initialization of the control system. Following this disabling task, the program proceeds to initialize the stack pointer and memory variables as shown in block 602. Following this task, switch 428 (11A
) And 432 (Fig. 11C) to produce operator selected parameters for operation of the system. First
It can be recalled from the description in connection with FIGS. 11A-11C that these supercomputers can override the selection of switches. Based on the selection of the switch, as shown in block 604, the system then sets the mode register as shown in buffer 606. "point",
There are four possible operating modes of the system described above as "stream", "switch stream" and idle. Following the setting of the mode register, the resolution flags are set for high and low resolutions, as shown in buffer 608, as selected by the switch, and based on the operator's selection in these switches as shown in block 610. The formula or metric flag is set. The program then proceeds to the instructions of block 612, where the flag is set according to the serial or parallel transmission selection in the switch above. Finally, the port of UART 404 is initialized, as shown in block 614.

An exact offset is identified and then this offset is counted because the DC boost or similar operating component of the digitizer 28 circuit exhibits drift characteristics associated with any operating environment as described in connection with FIG. 9B. Is measured or measured. This is done by having the microprocessor 250 command the selection circuit 242 to bring the line 250 to substantially ground level. This command is block 616
And the amount of offset is measured and held. Subsequent to the offset measurement shown in block 618, the microprocessor causes circuit 244 and associated circuit 2
The gain at 42 is set to the maximum value in anticipation of the worst case where such gain is required. This program
Continue until the command shown in FIG. 12B as indicated by node or connector A. According to the figure, connector A is shown as following the instructions in block 620, at the same time that the completion of the initialization procedure is followed by instructions that enable interrupts for normal operation.

The system then makes measurements along the x-coordinate direction and the system gain is set to the x-axis gain set point as indicated by the instructions in block 622. This instruction sets the maximum value for the first cycle of the program, but as the program continues to cycle, the XGAIN selection will be adjusted. Upon setting the gain, the analog switch is set for the x ⁺ form, as shown in instruction buffer 624. Thus, it will be recalled in FIG. 4 that the signals XCONTROL and PLUSCONTROL are manipulated so that the switches 56, 67 in addition to the switches in the arrays 42, 44 are set or closed. By providing this switch logic, block
As represented by the instruction at 626, the subroutine ADREAD is called so that a digital evaluation is produced corresponding to the measurement instruction XPLUS being made. This subroutine ADREAD is related to the pending R.R. It is described in detail in Kable, US Patent Application No. 06 / 665,302, "Electronic Graphic Devices." At this time, the program proceeds to the instructions in block 628 where the measurement content XPLUS in digital format is stored. As shown in block 630, the system then converts to a negative direction control while maintaining the switch setting XCONTROL so that an opposite direction evaluation of the X coordinate can be made. Subroutine ADREAD is called and XMINU is called, as described in block 632.
An evaluation in digital form for S occurs, block 634.
This value is stored, as shown in, and all such storage operations are performed in RAM in well-known fashion.

As shown at node B, the program then proceeds to the corresponding node heading in FIG. 12C and proceeds to the match shown at block 636 which determines if the X axis hysteresis flag has been set. This flag is set when there is a possibility given for the coordinates evaluations XPLUS and XMINUS with two valid but different gain control evaluations. If the flag is not set, the program goes to the instruction in the same figure, shown by line 638 and node C, which begins at the join node shown in FIG. 12D.

In general, the program shown in Figure 12D determines if the two X-axis readings previously made are valid for gain. In this regard, a window is established which has upper and lower threshold values for which digital measurements are made and compared within that range. In general, the criterion in this comparison is that both readings must be below the high threshold of the window and one of them must be above the low threshold. Looking at the match at block 640, a determination is made as to whether the value of XPLUS is greater than a high threshold, and if so, the value of XGAIN is greater than the minimum gain of the system, as indicated by line 642. Check if block 644
It is carried out as shown in. If so, block 64
As shown at 6, the value XGAIN is decremented by one increment as represented by one resistor in circuit 244 shown in FIG. 9B. It will be appreciated that the resistance values for the individual resistors in circuit 244 are selected to ensure about 18% increments in impedance. This ratio increment is considered to be the optimal way to make gain changes without causing variations between adjacent gain values that might otherwise result from lower ratio resistance increments. XGAIN
Following the adjustment of, the program returns, as shown at node or connector D, to set the gain of the system as at block 622 as indicated by the corresponding node and line 648 in FIG. 12B. Block 644
If the result of the match at is negative, then the program returns to set the gain of the system again, as shown by block 622, as indicated by line 650.

If the inquiry at block 640 indicates that the value XPLUS is greater than the high threshold, then a determination is made as to whether the value XMINUS is greater than the high threshold, as indicated by block 652. In that case, line 654
The same procedure is followed for selectively decrementing the value XGAIN, as indicated by the values XPLUS and XMINU.
If both S are below the high threshold, then a determination is made as to whether the value XPLUS is greater than the low threshold level, as shown in block 656. If this value is not greater than the threshold, then a determination is made as to whether the measurement result XMINUS is greater than the lower threshold, as indicated by line 658 and block 660. If so, the value XGAIN, as indicated by line 662 and block 664.
Is stored. Similarly, if the inquiry at block 656 indicates that the value XPLUS is greater than the low threshold, then
The value XGAIN is stored as indicated by line 666. This value of XGAIN is used as described in connection with block 622 in Figure 12B when the next operating cycle occurs. At this time, the program proceeds to perform a hysteresis test as indicated by connector E.

If neither the value XMINUS or XPLUS exceeds the low threshold, a determination is made as to whether the value XGAIN is less than the maximum system gain of the system, as indicated by line 668 and decision block 670. If this test is met, then the value XGA, as shown in block 672.
IN is incremented. Conversely, if the value XGAIN is not less than the maximum allowable gain, then the program returns to the corresponding node at line 648 and line 648 in FIG. It turns out that there is. Conversely, if the increment in value XGAIN is made by the instruction in block 672, then this increment value will be forced at the position represented by line 648 and the system gain will reflect that value as shown in block 622. .

As already mentioned in the text in connection with block 636 of FIG. 12C, where a single point is evaluated along one coordinate direction by first providing the AC source to one boundary and then to the other. It has been found that two different gain levels can occur due to the measurement of the same point, resulting in erroneous readings for coordinate points where there is non-linearity in the resistance sheet 30 or the system itself. Therefore, the routine shown in FIGS. 12C and 12E is used. According to the routine shown by this, the largest possible reasonable gain is selected for the system, in which case two reasonable gains are obtained. In FIG. 12E, the connector or node E from the stored instruction XGAIN stored in block 664 is first evaluated and, if the gain signal is incremented by one gain step, eg, a factor of 18%, then It is determined that the resulting increment remains within the window that accepts the threshold. Therefore, in block 676, the signal XPL is based on maintaining this value within the high threshold of the window of evaluation, eg, if increased with respect to a gain increase of 1/18% or one step.
The US is evaluated. Block 676 implements this evaluation result, and if the value XPLUS can be incremented by a gain factor of one, the program can continue, as indicated by line 678 and connector F. Signal XP
If the LUS can be modified in this way, the same evaluation is given by the signal XM, as indicated by block 680.
INUS will also be held. Signal XMINUS is 1
If the gain factor of can be increased, then line 68
As indicated by 2, the program continues with unchanged gain.

On the other hand, if both signals XPLUS and XMINUS fail the evaluation of blocks 676 and 680, there is a condition that the measurement result is not greater than the maximum window threshold. Therefore, as shown in block 683, the X axis hysteresis flag is set as discussed in connection with block 636 and FIG. 12C. At this time, there is a prediction that a double gain state will occur for one coordinate point. However, in case this prediction is incorrect, the last measured values XPLUS and XMINUS are stored as indicated by the instructions in block 684.

Returning to FIG. 12B, it can be seen that node D continues to line 684 and the program continues to node B. As in the previous case, this node leads to the corresponding node in Figure 12C.
In FIG. 12C, it can be observed that the match at block 636 is now affirmative, representing the prediction that there is a relatively high gain in the system, which produces a reasonable reading for the gain window defined by the high and low thresholds. Therefore, the program now proceeds to the instruction at block 686, where the X-axis hysteresis flag is reset to O and, as indicated at decision block 688, the first whether the gain change is valid. Judgment is made. Therefore, if the incremented value XPLU
If S is greater than the high threshold, line 690 and block 692.
The final value XPLUS has been restored in the program and the prediction has been betrayed, as shown in.
Similarly, if the value XPLUS is not less than the high threshold, then the incremented value XMI, as shown in block 694.
The same rating is obtained from NUS. If the value XMINUS exceeds a high threshold, as indicated by line 696,
The last value is used as shown in block 692. If the determination at block 694 is no, or if the last number is used, then the program proceeds to the node or connector F, also shown in FIG. 12F, as shown by lines 689 and 700. To continue. In the same figure, the first measured value XPLUS is processed by the instructions of block 702, where this value is placed in a temporary register to avoid its loss. This program then runs the last XPL of the software filter, where any transients or sudden changes in the system are wiped out.
Depending on the US reading mode, the process proceeds to average the reading values XPLUS at that time. This instruction is shown in block 704. The last reading XPLUS is then placed in a temporary register for the current reading as indicated by the instruction in block 706. This same procedure is XMINU
The measurement of S is repeated and the value XMINUS is placed in a temporary register to avoid its loss as shown in block 708, while at the same time the value XMINUS is averaged over the last reading as shown in block 710. , This last reading is then placed in a temporary register for immediate use, as shown in block 712.

With the final processing of such X coordinate measurements, the program then shifts to perform the corresponding set of coordinate measurements along the Y coordinate direction. In Figure 12G,
It can be seen that node G causes the program to continue in connection with the instructions of block 714, where the value YGAIN is recalled from memory and the system gain is set to the value of YGAIN. Next, as shown in block 716, the analog switch is set to a configuration in which the AC source 50 is applied to the positive boundary of the Y coordinate. For this reason,
Still referring to FIG. 4, the switches 56 and 57 are closed, but the value YCONTROL is added to the switch arrays 46 and 48. Subsequent to the setting of the switch, as shown in block 718, the subroutine AD
READ is called to convert the received signal to digital format. Following this conversion, block 720
The digitized result YPLU as shown in
S is stored and the switch system is now block 72
Set to add an AC source to the Y-coordinate boundary shown as negative as shown in 2. For this reason, the signal MINUS CONTROL is applied to close the switches 57, 64 as shown in FIG. Following the collection of readings, subroutine ADAREAD is called to digitize the resulting value, as shown in block 724, and the result is stored as reading YMINUS, as shown in block 726. The program then continues as shown at node H, shown again in FIG. 12H. In FIG. 12H, this node H is a block
Shown as following the determination made at 728, a determination is made as to whether the Y axis hysteresis flag has been set. If this is not set, the program will
Proceed as shown at node I, which reappears in Figure I.
In FIG. 12I, the program first checks for a high threshold and inquires whether the measured value YPLUS5 is greater than the threshold as shown in block 731.
The program proceeds to the inquiry made at block 734 as shown by line 732. At block 734, YG
A determination is made as to whether AIN is greater than the minimum gain, and if so, the value YGAIN is decremented by one increment, eg, 18%, as shown in block 736. As shown in line 738, the program then proceeds as shown in node J shown in FIG. 12G to reach the input for the instruction in block 714 via line 740, where the system gain is set to YGAIN. To be done. If the determination at block 734 indicates that YGAIN does not exceed the minimum gain, then the program returns again to node J and line 740, as shown in FIG. 12G, as shown in line 742.

Returning to FIG. 12I, the query at block 731 reads Y
If PLUS indicates that it is not greater than the high threshold of the gain window, then a corresponding inquiry is made as to whether the measurement result YMINUS is greater than the high threshold of the gain window, as shown in block 744. If so, as indicated by line 746, Y
GAIN is decremented and the program continues as described in connection with node J. If the query in buffer 744 indicates that both measurements are less than the high threshold, then
As shown in block 748, a determination is made as to whether the measured YPLUS is greater than the low gain window low threshold. Otherwise, the corresponding measurement is the value Y, as indicated by line 750 and block 752.
Performed on MINUS. The result of the inquiry in block 748 is either yes or the result is a block
If yes from 752, the resulting effective gain is stored as shown in block 758, as shown by each line 745, 756. At this time, the program continues as indicated at connector K.

If the inquiry at block 752 determines that YMINUS is not greater than the low threshold, then a determination is made as to whether YGAIN is less than the maximum allowable gain factor, as shown at block 760. If so,
YGAIN is 1 as indicated in block 762
It is incremented by one factor, for example 18%. If the query in buffer 760 results in no, the program goes through node J and line 740 to the first, as indicated by line 764.
The set value YGAIN of the system as shown in Fig. 2G
Return to. This same procedure is performed concurrently with the YGAIN increment as shown in buffer 762.

If YGAIN is stored as shown in block 758, the program proceeds as shown by connector K reproduced in Figure 12J. In this figure, the value YPLUS as incremented by one gain factor is compared to the maximum allowable gain change as described in connection with block 676 at the X coordinate. If the result of the inquiry is yes, then an increment is obtained, and as shown in line 768,
The program proceeds to connector L. If the result of the inquiry at block 766 is negative, then the same inquiry is made for the value YMINUS, as shown at block 770, and if the result is yes, as shown on line 772, The program proceeds in the same way as indicated by connector L. If the result of the inquiry in block 770 is no, the Y axis hysteresis flag is set to 1 as shown in block 744, followed by the last of the YPLUS as shown in block 776. The value becomes YPLUS and the corresponding last value YMINUS
A storage function occurs in which is YMINUS. The program then returns as shown at node J as shown in Figure 12G. When the program is repeated, this is the 12th H
The query at block 728 as shown is again encountered. In this case, the query indicates that the Y-axis hysteresis flag is set and the program continues until the instruction in buffer 778, where the hysteresis flag is reset to zero. Upon resetting this hysteresis flag, a determination is made as to whether expanded YPLUS is greater than the high gain window threshold level as shown in block 780, as shown in block 780. If so, the line
The value YP, as shown in 782 and block 784.
LUS and YMINUS are set back to their last values.
At that time, the program proceeds as shown on line 786,
Continue as shown again at connector M. Block 78
If the determination at 0 indicates that the value YPLUS is less than the high threshold level, then as shown in block 788,
A corresponding determination is made as to whether the expanded value YMINUS is greater than the high threshold level of the gain window. If this threshold is exceeded, the last values for YPLUS and YMINUS are recalled, as indicated by line 790, and the program continues. Similarly, if the value YMINUS is less than the high threshold level, as indicated by line 792, the program continues.

As in the case of the X coordinate, the program then performs some form of software filter operation on the measurement of the Y coordinate to smooth transient or abrupt changes in the system. It can be seen in FIG. 12K and connector M that the program stores the value YPLUS in a temporary register, as shown in block 794. At the same time that such a store operation occurs, block 79
The value YPLUS is the last read YPLU, as shown in 6.
Averaged by S. At this time, the final value YPLUS is stored in the temporary register, as shown in block 798, and the value YMINUS is placed in the temporary register, as shown in block 800. The next instruction in block 802 averages the value YMINUS and then the value YMINU.
S is averaged by the last value YMINUS. At this time, as shown in block 804, the last value YMINU
S is used and stored in the temporary register. At this point, the program is at the stage where all the combinations of measurements to obtain the X and Y coordinates are made, and then the program searches from this value for the coordinate information or position. In FIG. 12L, node N has been regenerated and is shown as following blocks 806, 808 which serve to prepare the system for the next read. In this regard, the instructions at block 806 set the system gain to XGAIN and block 808 sets the analog switch to XPLU.
Read out S form.

At this time, the program proceeds to the instructions in block 810, where the normalized value of X, or XNORM, is obtained using the subtractive method. It is considered that this value was normalized because it was obtained from the natural coordinates of the resistance sheet 30. Therefore, the value at this junction has a range from a negative value to a positive value. It is required to convert this normalized value or XNORM to a value in the coordinate system for positive integers, i.e. to convert the value 0 to another positive value. The actual read value from one boundary to another does not follow the exact sequence because the resistance sheet 30 changes in its structure. As a result, the minimum value of the resistance sheet 30, that is, the value of 0 is read in advance and stored in the ROM for proper use. This value is represented as XMIN. Correspondingly, the corresponding measuring method is also carried out in the Y-coordinate direction and the value YMINUS is obtained and placed in memory.

The program then proceeds to XN, as indicated by block 812.
The value XMIN is subtracted from the value for ORM and this is multiplied by the expansion factor X $ EXPAND. The latter term is simply an expansion factor that provides a large number suitable for digital processing, eg 64,000.

The program then checks the resulting value for the X axis,
Make sure there are no unacceptable numbers. Such false values may occur, for example, when the tracer is placed outside the active area of the resistance sheet 30.
Therefore, as shown in block 814, the value of X is known X.
A determination is made as to whether it is greater than the maximum value of XMAX. If so, the program starts again, as indicated by line 816 and connector 0, and
Return to the corresponding connector instruction in Figure B, where block 62
As shown in 6, an instruction to perform analog / digital conversion reading is issued. Note that node 0 in the figure leads to the program via line 818.

If the value X is acceptable for the smallest evaluation, the program looks for a comparison made in block 820, where the value of X is compared to the smallest or zero evaluation result. If the value of X is such a small evaluation of 0, the line
The program returns to line 818 as described above, as indicated by 822,816. If the value of X is correct with respect to 0, then
The corresponding operation is performed on the evaluation of Y, as indicated by line 824. Thus, as shown in block 826, the normalized value of Y, or YNORM, is obtained as the ratio of the difference and the sum, and at the same time, the corrected and expanded value for Y is obtained, as shown in block 828. If so, this value is tested according to the instructions in block 830 to determine if it exceeds the value of YMAX.
If so, the program returns to line 818 in Figure 12B, as indicated by line 832 and connector 0. If the value of Y is correct for YMAX, then the value Y is tested for 0, as shown in block 834. If it is less than 0, the program returns to line 818 as previously described, as indicated by lines 836 and 832. If the value of Y is incorrect with respect to the position of the tracer, etc., it is digital in nature, as shown in block 838, and will most likely compensate for changes in the coating thickness of the resistive sheet 30. The error correction procedure provided is implemented. A subroutine for correcting this error will be described below. Following error correction, the program is
Call the output subroutine shown in block 840 described in 06 / 665,302. This completes the entire program and the program returns to line 818 and connector 0 as described with respect to Figure 12B.

The error correction system of the present invention using the subroutine described generally in buffer 838 in FIG. 12L is primarily associated with the necessarily encountered changes in the resistance of the resistive surface or layer 30. Due to variations in the manufacture of such devices, the energizing signals provided by the boundary inputs at opposite positions, or from the locator or tracer, produce a voltage or display signal which is parallel to the coordinate axes and bounded by one boundary. It will be found that the evaluation deviates from the required linearity in order to evaluate against other boundaries. Some form of correction for this non-linearity is required in a system that obtains an accurate digital output signal that corrects for the position on resistive surface 30. However, this correction requirement is a system and method that allows the correction to be made without costly and unreasonable delays, for example, delays that may occur accidentally due to computer operations involved in the implementation of arithmetic procedures. Must be satisfied by. Especially when such procedures involve multiplications or divisions, the time factor becomes important and the corresponding cost factor unreasonably increases in order to develop a product with desirable broad marketability.

In FIG. 7, a predetermined physically positionable grid array of previously secured positions or points represented by ξ coordinate lines 850-854 and η coordinate lines 856-861 is set thereon. A schematic view of a resistive sheet 30 is shown. It can be considered that the grid lines of these ξ and η coordinates indicating a certain physical region are regularly spaced, perpendicular to each other and aligned with the boundary of the resistance surface 30. When the boundaries are biased as described in connection with FIG. 4 and a locator 32 is placed at each intersection of this grid, one boundary to another in the ideal direction described in connection with FIG. 3 and curve 24. A linear signal output is obtained when moving to the boundary of. However, generally in the case of some presenting surfaces 30, the positioning of the locator 32 at the intersection or position of such a grid will not give a linear output, for example given to some host computer. This will result in a distorted representation of the lattice array shown with the displacement of the dashed line of the lattice array. For purposes of illustration, this grid array is denoted by the coordinate values x, y (considered to be in the signal domain) with grid values for ξ and η above.

To show the requirement for one correction, locator 32 is placed at point 864 shown in FIG. 7, which is grid lines 853, 854 and 85.
Let's think that it can be considered that it hits within the intersection of 6,857 lattice arrays. Locator 3 at point 864 (,)
The signal output from 2 does not have linearity with respect to the standard linearity output exhibited by a rectangular grid array, but has some signal value. The final required or standard coordinate value for point 864 in the linear grid array is (,)
Thus, one attempt at correction represents a mathematical mapping or transformation method. That is, = f (x, y) = g (x, y) Excluding the inversion symbol for simplicity, (1) ξ = f (x, y) (2) η = g (x, y) Since the transformation formulas are evaluated each time the value (x, y) of the signal is received, these formulas must be very simple, while maintaining high accuracy. Another important attribute is that this transformation is unique to each tablet because the resistive film non-uniformity of each tablet is different.

The correction system according to the present invention is, firstly, a coordinate line 850 of FIG.
~ 854 and 856-861, including the formation of a regular grid-like array (physical area). The number of grid lines in this array, or the size of the "square" defined by the resulting grid lines, is large enough to ultimately obtain the address of the memory from the above x, y values. Are chosen to produce regular discrete regions of sufficient fineness to achieve the required accuracy of interpolation. Therefore, following the determination of such a grid array of physically positionable positions, for a system in which an electrical signal (data set) of a signal domain represents a value for each of the intersections of said grid array. To be measured. To produce this signal data, a device 32 such as a locator is placed at each of the intersections of a regular grid array in the physical domain in an off-line procedure and read (x, y) is given in the usual manner. The set of electrical signals (x, y) for all grid array intersections is
It cannot be used immediately to determine the conversion values f and g that can be effectively used in an online microprocessor. Note that the physical domain values ξ and η in this measured data set change with constant physical increment, but the corresponding electrical signals x, y change non-linearly. This is why it is difficult to obtain a computationally valid functional form of f and g using the measured values x and y.

In this example, the physical area (ξ,
η) value and the electrical signal (x, y) in the corresponding signal region
The relationship between is reprocessed as follows. That is, first consider a grid array in another signal domain in the xy coordinates, in which the grid lines are orthogonal and equally spaced. The size of the xy grid in the signal domain is wide enough to contain all the electrically measured coordinates (x, y) corresponding to the grid array in the physical domain on the tablet, and for the transformation. Fine enough to yield good accuracy.

Secondly, the coordinate values ξ and η of the physical area corresponding to the intersection of the grid array of the signal area on the (x, y) coordinates are mathematically obtained by the solution of the following set of equations. That is, (3) x = F (ξ, η) (4) y = G (ξ, η) where x and y are the coordinates of the intersection points of the grid array in the signal region.

In the above equation, F and G are ξ on the tablet
And η are interpolated conversion values (ξ, η) into (x, y) based on the electrical signals x and y measured at each intersection of the lattice array on the intersection of the lattice array.

A pair of pairs of values (ξ, η) calculated for each grid array on the (x, y) coordinates in this way is called a “correction table”.
In the correction table, it is important to recognize that the values x, y change with constant increments, while the values ξ and η change non-linearly. Using the correction table thus obtained, the transformations (1) and (2) can be represented mathematically easily and effectively in the interpolation method. Further details regarding the provision of a "correction table" are described in the text with respect to FIG.

The method described thus far consists of the following two steps. That is, step 1 (a): measurement of electrical signals x, y for each grid array on the tablet step 1 (b): equations (3) and (4) are solved to find this, and (x, y) Off-line calculation of the correction table corresponding to the values of x, y on the intersection of the grid array in coordinates: Step 2: Include an on-line microprocessor built into the tablet system. This on-line microprocessor contains Equations 1 and 2 with correction tables and interpolation methods.

All of this correction table data is placed in read-only memory as part of the manufacturing of system 28. Therefore, in actual use, the second part of the calculation is to obtain the necessary data for carrying out the track maintenance by a simple interpolation method which is desirable in a quick way and which can be done by a relatively simple microprocessor device. You just need to address this table, which is held in memory.

Considering now the second part of the system, the online calculation, the subroutine "ERROR CORRE"
CT "is shown in connection with the flow charts of Figures 14A and 14B. In particular, this subroutine starts with the formation of an error pointer or index for accessing the read-only memory with the above index correction table. It will be recalled that the position digital signals x, y produced by the system are 16 bits in length. The five most significant bits of the digital signal x, y at these locations are used to identify the appropriate grid region.
It will be seen in FIG. 14A that the instruction in the first block 870 masks the lower N bits of signal x. In this regard, the lower 11 bits of the 16-bit signal
Bits are masked. Following the instruction at block 870, the corresponding lower N bits of signal y are also masked, as shown in buffer 872. Therefore, the five upper bits for the values x and y are now obtained. These two upper bits are concatenated to obtain the 10-bit corrected memory address used to access the correction look-up table in ROM 412, as shown in block 847. Further in FIG. 13, this access finds the intersection of grid locations or points, which is to the lower left of the grid's rectangle or discrete "area" of the signal domain at which it lies, eg, 864. Memory access will also find the remaining grid points of the rectangle of interest. At this time, a weighting factor is added to each of the coordinate values of the calculated physical region of the above four grid lines, and the four values thus processed are the corrected coordinate values for the coordinate x, y. A weighted average method is performed to obtain the output signal. As shown in FIG. 13, in the above interpolation method, the weighting method performed on the coordinate values of the calculated physical area at the intersections of the grid lines 910 and 912 is indicated by F1, and the weighting is the product. It is calculated as (1-x) (1-y). However, the values x and y are obtained as an electrical signal from the locator online. Block 876 in Figure 14A.
It will be seen that by expanding this equation, as shown in, there is only one step in the multiplication, that is, the rest of the weighting factors are products of subtraction and addition. FIG. 13 shows that the weighting factor F2 is applied to the intersection points of the remaining lattices viewed clockwise.
Is (1-x) y, the factor F3 is xy, and the weighting factor F4
Indicates that (1-y) x. It will be appreciated that these factors are obtained as shown in the instructions of blocks 876, 878, 880 and 882. It is desirable that factor F3 (block 880) be obtained first, because the term xy is used in obtaining factor F1, which is further used to obtain factor F2.

At this time, the program continues until the instruction at block 886, as shown at line 884, where YFLAG
Is being set to 0 to produce a corrected x-coordinate output signal, and is further accumulated or the product of four correction weighting factors multiplied by the corresponding calculated physical area coordinate values. It indicates that the correction value that causes the arithmetic mean in the register is set.

At this time, the subroutine that converts the display of the index or address into the error correction table and becomes the error pointer advances to the instruction shown in block 888. Following this construction, the four values of the intersection of the previously mentioned surrounding grids are accessed from memory by the clockwise error pointer described above. However, the first weighting factor multiplication is performed on the first lower left intersection of the discrete rectangle, ie, the intersection of the grid lines 910, 912 as shown in FIG. The correction coordinate values are then multiplied by the weighting factor F1 to obtain the first correction factor as shown in block 890. Then block 89
As shown in 2, the index pointer is incremented to find the coordinate value of the calculated physical area for the intersection of the grid lines 911, 912, as shown for example in FIG. Upon obtaining this value, this value is multiplied by the weighting factor F2, as shown in block 894, and the resulting value is added to the corrected moving average, ie in register CORR. At this time, the program again returns to lines 911 and 9 as shown in block 896, for example, as shown in FIG.
Increment to access the calculated physical area coordinates for the 13 intersections. The weighting factor F3 is then multiplied by this accessed value, as shown by the instruction in block 898, and the resulting product is then added to the value in the correction register CORR. The program then continues as indicated at connector Q until the instructions shown in FIG. 14B shown at block 900.
Block 900 has index pointers such as grid lines 853 and 85.
It is shown to be incremented relative to its last position shown in Figure 13 as the intersection of 7. The resulting standard coordinate value is accessed from memory and this value is multiplied by a weighting factor F4, as shown in block 902, and the result is added to a register CORR to obtain the weighted coordinate value ξ Obtain the final value, the moving sum. At this time, the program proceeds to the inquiry as shown in block 904 and returns YFL.
Determine if AG is set to a logical one. If not, then as indicated by block 906,
The added value in the register CORR is established as the coordinate position ξ. The program then proceeds to the instructions shown in block 908 where the error pointer is made equal to the error pointer and offset value η so that the value η can be accessed from memory. Following this, as shown in block 910, YFLAG is set to a logical 1 and the subroutine calls connector R in FIG. 14A.
And proceed as indicated by line 912 to execute the weighting factor routine as described above. If the inquiry at decision block 904 indicates that YFLAG is equal to a logical one, then the weighting factor routine described above is completed for the coordinate value η and the added register value CORR, as indicated by line 914 and block 916. Is made equal to the position coordinate η for the set. At this time, the subroutine returns to the main program as shown in Figure 12L to implement the subroutine CALL OUTPUT shown in block 840.

Coordinate values ξ, η of the physical area corresponding to the signal area values x, y
Considering the above formation of the "correction table" obtained in connection with the above, the attenuation of the read-out signal is first a display of the grid plotted by the upper computer shown in FIG. The grid incrementally arranges tracers or the like so as to be regularly spaced along the coordinates of the electronic graphic resistive surface 30, and also for example analog line 116.
It can be formed by plotting the data (set of data) received from (FIG. 4) at a given time to the control function 70. For generation of the correction table, the correction subroutine as described in connection with block 838 in Figure 12L is bypassed to generate the first set of data for the electronic graphics device. In Fig. 15, the boundary of the physical area of the active area of the resistance surface is rectangular.
Represented within 1000. Tracer lines 850-854 and 855
The slightly distorted output shown at 1002, as described in connection with FIG. 7, arranged regularly spaced along the grid points defined by ~ 861 and without correction. A plot arises. The error correction method and system of the present invention produces the above correction table.
Use this data set as shown graphically at 02.
For this reason, the readings of the data set are measured or used off-line and stored in a file for the generation of a correction table containing the above coefficients used in the process of on-line rapid error correction.

With further reference to FIGS. 16A and 16B which combine to produce a high level or further generated procedure at the beginning of the preparation of the correction table as shown in block 1004, the above data sets are collected. .. For this collection procedure, for example, a pickup or tracer is used to
Can be moved from one position to another. The spacing of grid points for such acquisition may be, for example, in increments of about 12.7 mm (half an inch) in both the x and y directions. The resulting collection of signal domain data representing coordinately aligned rectangular grid positions in the physical domain of surface 30 is x (n, m) at block 1004.
, And y (n, m), where the value n goes from 1 to n _max and the value m goes from 1 to m _max . This maximum depends on the selected incremental interval and is approximately 30
For a grid spacing of about 12.7 mm (half inch) given above for an active area 30 of × 30 cm (12 × 12 inches), such a maximum would be 25. In FIG. 15, plot 1002 is a 25 × 25 grid matrix located within active area boundaries 1000.

Upon completion of the collection of data sets, the procedure will block 10
Proceed to the active state shown in 6. Such activity is
a group of increments along the x-axis including the establishment of a normalized index configuration set to 1 as indicated by i = 1,
Y as the value defining 1 is indicated by the instruction (j = 1)
Established along the axis. Furthermore, the limits of the values of the signal domain of the data set are determined, the values x _min , x _max , yx _min , y _max.
Indicated by. Simultaneously with the determination of the limit of this input data set, the grid case or the number of points to be used for generating the error correction table is determined. Thus, a finer form of correction can be obtained by expanding the number of grid positions used for correction, which also determines the size of the error correction matrix or table. Therefore, the maximum value for the index, i, j, is i _min ,
It is determined and represented by i _max . In the case of the lattice structure shown in FIG. 15, 32 for both coordinates i and j.
Segment is selected. Finally, initialization is performed on the numbers ni, nj, which represent the number of grid points to be analyzed even when the activity at block 1006 is below. In the case of FIG. 14, the maximum value obtained is 25.

The program then proceeds to provide a sequence of 32 × 32 signals whose values are generated in accordance with the relationships shown in block 1008, the sequence of values of the signal region having regularly incremented or spaced intervals indicated by xr, yr. Obtain two indexable values of regularly incremented addresses constructed for a grid or matrix of regions. Thus, in the illustrated example, there are 32 regularly incremented values for xr, yr. A physical representation of such an indicator structure relative to the physical area is partially shown at 1010 in FIG. The distribution of the signal region can also be represented by this lattice 1010.

Simultaneously with the generation of the regularly incremented signal region values xr, yr, the program is now at the location of regularly spaced physical regions for each of the regularly incremented signal region values xr, yr. Find out. At the same time as the generation of such data, the information y in the online memory holds the completed correction table.

The first attempt to generate the locations of the irregular locations, now denoted i'and j ', of these physical regions is one of the two method-based evaluation methods, one of which is the formation of the resistive surface. Predicted on a history-based basis, and others are more dependent on research regimes based on broader initial data. Thus, an initial evaluation is performed for physical area locations i ', j', as shown in block 112. Following this initial evaluation, the system further defines the evaluated values i ', j' using Newton's interpolation method.
By such an attempt, the interpolated physical region values resulting from the first evaluated physical region location as i ', j'and the adjacent values of the input data set, the signal region values x', y '. The coordinate location is obtained. The values of these areas are a function of the physical area locations i ′, j ′ evaluated from the beginning,
Therefore, as shown in block 1014, x '(i',
j '), y' (i ', j'). Following the generation of the signal domain values x ', y', the block
As shown in 1016, the coordinate position i ′ of the physical area,
Re-evaluation of j'is performed based on the values x ', y'in the signal domain. This new or subdivided physical region value i ', j' is then tested for convergence as indicated at decision block 1018. This test determines the difference between the new subdivided i ', j' value and the next preceding value of this value. If this test determines that the difference between these two tested values is greater than the predetermined error value, then the input side of block 1014 is reached, as indicated by line 1020 and node 1A, and the program is subdivided again. The Newton's interpolation method is performed based on the calculated values of i ', j'. When there is a desired state of convergence of values, as shown in line 1022 and block 1024, j
A determination is made whether the value incremented for reaches the previously defined maximum j _max , which represents the completion of the analysis along the y coordinate direction. If the result of the determination at block 1024 is yes, then a determination is made as to the indexing of the physical area value i, as indicated by line 1026 and block 1028. If the maximum value i _max is obtained, then the error correction routine is complete and all the information is stored in memory to serve as an online correctable table, as shown in line 1030 and block 1032.

If the query at block 1024 indicates that the indexing of the i or j coordinate direction is not complete, then the previous value for j is incremented by one, as shown at block 1034. This time the program is line 1036 and block
1038, where the value y is set equal to the value of the determined j ', the error correction memory
Filed in the table. Similarly, if the query at block 1028 indicates that the indexing value for i did not reach the maximum value, then the last value for i is incremented by one, as shown at block 1040, and the line 1036 and block As shown in 1038, the value xa in the error correction table for the address of the signal area at that time is i ′.
Is set equal to the value of. Upon setting either xa or ya and providing its value to memory, the program returns to determine the next xr or yr value associated with the instruction at block 1008, as shown at node 1B.

In FIG. 17, an irregular position i ′ of the physical area,
The first of the above two methods for evaluating j'is described at the extended level of detail. This evaluation routine, generally labeled 1012, which corresponds to the similarly numbered blocks in FIG. 16A, is shown as entered at line 1042, at the same time as to whether the indexing i, j is equal to one. Will be queried. In this context, this index actually represents the physical area grid 1010 as described in connection with FIG. If the query result is yes, then the value i ', as shown in block 1046.
Is evaluated by a relatively simple formula, and a value x representing the value of the signal domain shown therein is obtained in the first data set and placed in the above positions (ni, 1) and (1,1)). . If the inquiry at block 1044 yields a negative result,
As shown in line 1048 and block 1050, the value i'is determined from the last value provided for the correction table, i.e., the value xa at location (i, j-1).

Following the above determination of the value i ', the program determines whether the index i is equal to 1 as shown in query block 1052. If an acceptance decision is made at block 1052, then the evaluation for the physical region location j'is made using the above equation, as shown at block 1054. In this equation, y (1, nj) and y
The value for (1,1) represents the evaluation of the signal domain of the data set originally obtained at the grid location. block
If the indication at 1052 is that the value i is not equal to 1, the evaluation for j'of the last ranked index table is (i-1,
j) is taken from the place designated. Upon completion of the above evaluation procedure, the same program continues for the operations described in connection with block 1041 of Figure 16A, as indicated by line 1060. Generally, the evaluation method shown in FIG.
It is generated when the product history indicates that such an attempt is an acceptable value. For example, the misalignment in the grid assembly 1002 shown in FIG. 15 indicates a lack of severity such that predictions can be made according to a simpler attempt. In effect, this attempt seeks to establish the first value at the beginning of a column or row of the grid as generated in relation to the information in blocks 1046 and 1054. Then, the evaluation can be performed from the value at the last position in the correction table including the generated memory.
A more elaborate attempt for use in connection with higher levels of strain or in the context of products with a history of known behavior is described in connection with Figure 20 below.

In FIG. 18, Newton's interpolation method, as generally described at block 1014 in FIG. 16A, is shown at a more detailed level. This numbering is used again in the figure to generally indicate the interpolation measure. With this routine, the program searches that location to find the actual value of the first evaluated coordinate value i ', j'. For example,
Again in its enlarged sub-view in FIGS. 15 and 15A, it can be observed that the program is arranged in relation to a grid of regularly spaced signal regions, as previously generated, at coordinates i ', Search to find the actual location of the physical region of the point with j '. One physical point is
It can be derived from the original data set with some known physical location on the resistive surface 30 but with the x, y signal regions representing distortion. Due to the interpolation layer, this is the signal value from which this latter known physical location and from which it is calculated to find the actual estimated value in the physical domain for the coordinates i ', j'. Ensuring that the required points or positions i ', j'in the table represent one corner of a regularly spaced grid, and that the information components of the selected data set are in the squares represented thereby. Please pay attention. Providing a normalized increment of 1 from one regular grid spacing 1010 of the grid to another in the physical region index values i, j starting from the rightmost position in the generated square, The coordinates surrounding the points of the selected data set are generally i, j; i + 1, j; i + 1, j + 1 and i, j + 1. This interpolation method uses these data to produce the required actual values i ', j'.

Returning to FIG. 18, the program for interpolation is block 10
It is shown starting at line 1062 leading to the operation shown at 64. These operations include the generation of coefficients as well as numbers. In the case of a numerical value, i represents the difference between the sought i'point and the value of i shown (i'-i). A similar relationship is obtained for the coordinate of j. Following the generation of these relationships, a series of calculations are performed in accordance with the relationships shown in block 1064 to provide the weighting factor coefficients identified as emm, epm, emp, epp.

At this time, the program proceeds to block 10 where the value x'is expanded.
Proceed to activities described in connection with 66. This signal domain value is associated with the previously mentioned value xr and represents the signal domain value of the data set for x appropriately weighted with respect to the estimated physical location of the desired point. In addition, buffer 1066
, The partial derivative of x with respect to i is performed with the partial derivative of x with respect to j according to Newton's interpolation. Following these calculations, the same activity occurs at the generation of the signal domain value y ', as shown in block 1068.

Simultaneously with the generation of the partial derivative and the values x ', y', a determinant (det) representing the form of the sum of partial derivatives is generated according to the formula shown in the above block. Further, the value x is the regular value xr of the signal domain and the calculated signal domain function x ′.
Calculated as the difference between and. The corresponding value for Δy is expanded as represented by the equation in block 1070. These latter delta estimates are then used in the re-evaluation of the bids i ', j'as described for block 1016 in FIG.

In FIG. 19, the above re-evaluation of the program is shown at an expanded level of certain detail labeled with the overall designation 1016. The behavior of this reevaluation is shown on line 1074 by the calculation of the values Δi and Δj according to the equation shown with the previously developed partial derivative values Δx and Δy and the previously calculated definite number (det). To start. Depending on the resulting values of i and j, the re-evaluated values of i ', j'are added as shown in this block.

The program then tests the degree of convergence as described above in connection with block 1018 and by decision block 1078 as shown in FIG. As shown therein, the values of i and j are used to test for convergence and these values are compared to a predetermined error value. If the test shows no convergence, the line 1080
And as shown at node 1A, the program is 16A
As shown, re-interpolation is performed based on the last value for i ', j'. If convergence occurs, the line
As shown at 1082, the program continues as shown in Figure 16B.

In Figures 20A and 20B, a more elaborate or second valuation method flow chart is described as previously described with respect to block 1012 in Figure 16A. This method can be used when only a more crude initial information is available, i.e. when there is a lack of history in the evolution of the assessment or when the distortion is at a higher level than is suitable for the first disclosed method. .

This evaluation method is a method that realizes that the data set is not excessively distorted so that a reasonable evaluation of the location of points can be made. For example, one point will be valid where it can be considered as the ratio of the distance between the opposite boundary and the actual physical location of the point of the measured data set.
The present method is a method of first searching for such a ratio to secure a substantially rectangular window having a size based on a square defined by a grid of a data set of a physical area. For example, the longitudinal size of the squares that define such two grids can be used in determining the size of the window. For this reason, the first localization operation of some required evaluation point begins with the selection of a window in the physical area established by the data set.

In FIG. 20A, the first evaluation of the location of points in the x-coordinate direction is labeled "ibase" and is multiplied by the physical area value i, which is the maximum number of grid positions for the number of points ni used. Equivalent to a function of integers representing the ratio to "i _max ". The method also considers that the ratios that define the appropriate locations of points in the physical domain are approximately valid in the signal domain as well.

The program then begins to locate a window within which it can find a point in the desired physical area, which is a reference to the coordinate position of x, ii and m.
This is done by calculating m. For this reason, the value "iwind", which is the length of the selected physical area for a certain window value, is used. Note that the activity state of block 1092 indicates that the window is defined as a window value of 1 to the right and left of the co-selected origin in the x coordinate direction. At this time, the program indexes the activity of block 1094 in which the indices jj and nn are generated as in block 1092, but along the direction of the y coordinate resulting from the value of the first jbase. In effect, the program then searches within this window area to produce an accurate assessment of the points of the desired physical area. The first procedure for initiating this search is shown in block 1096, where the initial evaluation value i'for the point requested by the physical region is set equal to ii and the corresponding required physical region point j'is set. Is set equal to jj. The program then performs a series of tests and evaluations of this first hypothesis. In fact, the search for this discrete, selected range is in the range from ii to mm in the x coordinate direction and from jj to nn in the y coordinate direction. This first selection at block 1096 sets the evaluated point at the lower boundary ii, jj of the search area.

The first test performed began with that shown in connection with decision block 1098. The signal domain value xr calculated before block 1098 is tested against the first signal domain value (data set) at locations i ', j' and i ', j' + 1. If the value xr is greater than these values, the program proceeds to the next test as shown in decision block 100. The activity in this block determines whether the signal domain value xr is greater than the signal domain value of the corresponding data set at location i '+ 1, j' as well as location i '+ 1, j' + 1. Otherwise, as indicated by decision block 1102,
A first evaluation of the signal domain value yr is performed on the signal domain data set values y (i ', j') and y (i '+ 1, j'). If this test is not satisfied,
The program proceeds to the test in decision buffer 1104,
Here, the signal area value yr is the signal area value y of the data set.
Compared to (i, j + 1) and y (i + 1, j + 1). If the criteria of this test are not met, the program proceeds to make some form of proportional error test that actually seeks for the desired point symmetry with respect to the established window boundaries. If the desired point is generally not symmetrically surrounded by window boundaries, the search procedure will not be of adequate accuracy. Therefore, the first test of this character is done according to the relationship shown in block 1106,
Here, the value Z is determined. Once this initial value Z is determined, the value yr is tested against it as shown in block 1108. If the value yr becomes greater than the initially calculated value Z, then the next value Z is calculated, as shown in block 1110, and this next value Z is calculated as shown in block 1112. Compared to y. If this value yr becomes less than the next calculated value Z, then another value of Z is calculated, as shown in block 1114, and the signal domain of the signal domain, as shown in block 1116. The value xr is compared against this calculated value of Z for x. If this value xr becomes greater than the last calculated value Z, then the value Z is calculated, as shown at node C in FIG. 20B and at block 1118,
The value xr is again compared against the last calculated value of Z, as shown in block 1120. If the value xr is not greater than this last calculated value of Z, then the test is terminated and the program proceeds to Newton as previously described in connection with block 1014 of FIG. 16A, as indicated by line 1112. The implementation of the interpolation method of is started.

If any of the above tests, such as in blocks 1098, 1100, 1102, 1104, 1108, 1112, 1116 or 1120 result in a decision of acceptance indicating failure of the test, then the program immediately passes through line 1124 and connector A. As shown, decision block 1126 (FIG. 20A) illustrates omitting the evaluation. In this block, an inquiry is made as to whether the selected value j'is equal to the window coordinate nn. In that case, as shown in line 1128 and block 1130, the following determination is made as to whether the corresponding coordinate i'is equal to the position mm of the window, i.e. if this point corresponds to a corner of the window. . If this decision in the instruction at block 1130 is yes, then these values are chosen as the evaluated positions, as shown at line 1132 and node D, and the program is shown at lines 1134 and 1122. Proceeding to the function of Newton's interpolation method in block 1014 of FIG. 16A.

If the determination as shown in block 1126 is that the value j'is not equal to nn, then the original evaluation value j'is incremented by one unit value, as shown in block 1136, and the line 1138.
And as shown on connector B, the program is line 11
Begin testing the new value as indicated at 40.
As a result, if the value j'is found to be equal to nn and the value i'is not found to be equal to mm, then
As shown in block 1142, the value i ′ is the next value i ′ +
The test is further performed on this new evaluation, indexed to 1 and shown in line 1144 and connector B.

Certain changes and modifications are possible in the systems and methods described herein without departing from the scope of the invention, and therefore all matter contained in the description and shown in the drawings is illustrative and not intended to be limiting. Should be interpreted as

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a one-dimensional model of an electronic graphic device of the present invention, FIG. 2 is a similar schematic circuit diagram of the model of FIG. 1, and FIG. 3 is a voltage in a resistance layer shown in FIG. FIG. 4 is a schematic diagram showing a circuit and a switching element of the present invention, and FIG. 5 is a graph showing timing and control sequence characteristics of the device of the present invention with respect to sequential operation, that is, data mode. FIG. 6 is a plan view showing a tracer or locator used in the present invention, FIG. 7 is a schematic view showing a resistive surface having a row of grid positions and an array of distorted grids superimposed thereon, FIG. 8A. And FIG. 8B is a schematic diagram showing the electronic components of the driving and switching operations of the system of the present invention, and FIGS. 9A to 9C are circuit diagrams showing the analog processing elements of the system of the present invention.
FIG. 10 is a circuit diagram showing an LED drive circuit of the system of the present invention, FIGS. 11A to 11C are circuit diagrams of digital processing elements of the system of the present invention, and FIGS. 12A to 12L are of the system of the present invention. FIG. 13 is a flow chart explaining the main control program, FIG. 13 is an enlarged view of the signal area, FIG. 14A and FIG.
FIG. 14B is a flow chart for explaining the error correction subroutine of the control program of the present invention, and FIG. 15 is for positioning the cursor at regularly spaced increments along the coordinate axis of the digitizer table of the resistance surface. Figure 15A, which shows the grid in which the resulting computers are plotted.
The figure shows an enlarged view of one corner of the plot of Figure 15, Figure 16
Figures A and 16B are general high level flow charts showing the method of producing the correction table according to the present invention.
FIG. 16 is a flow chart showing one evaluation routine of the flow charts of FIGS. 16A and 16B, and FIG.
A flow chart showing a routine for the implementation of the Newton interpolation method as generally shown in the flow charts of Figures A and 16B, Figure 19 being shown in Figures 16A and 16A.
A flow chart of a routine for implementing the reassessment method generally shown in the flow chart of FIG. 16B,
And Figures 20A and 20B together are a flow chart showing another routine for performing the evaluation method generally described with respect to Figures 16A and 16B. 10 ... Resistive layer, 12 ... Dielectric material, 14, 15 ... Electrode, 16,
17 …… line, 20 …… stylus (tracer), 21, 22…
… Line, 28 …… Digitizer device, 30 …… Resistance sheet (side), 32 …… Stylus (tracer), 34 …… Bad array, 36,38,40,42,44,46,48 …… Array, 50
…… AC source, 52,54 …… Line, 56,57,66,67 ……
Single pole single role analog switch, 62, 64 …… line, 70 ……
Controller, 72-79 ... Line, 100 ... Front widening stage, 112 ...
… Sample and hold circuit, 114 …… Buffer, 116, 118, 1
20 …… line, 138 …… peep circle part, 140 …… edge frame part, 142…
… Switch, 144 …… Light emitting diode, 162 …… Connector, 164 …… Signal processing circuit, 168 …… Comparison amplifier, 170…
… Capacitor, 172… Resistor, 174… Bandpass filter stage,
176 ... Computational amplifier, 178 ... Capacitor, 180 ... Capacitor, 182 ... Line, 184 ... Current drive stage, 185, 187 ...
… Line, 186… Capacitor, 188… Quad package, 190… Connector, 191… Line, 192… Connector, 193… Line, 194… Line, 196… Connector, 200
...... Connector, 202,204 ...... Line, 206 ...... Arithmetic amplifier, 208,210 ...... RC circuit, 212 ...... Line, 214 ...... Analog switch, 216,218 ...... Resistance, 220,222, 224, 2
26 …… line, 228, 232 …… condenser, 230, 234, 238
...... Filter stage, 240 ...... Line, 242 ...... Selector circuit,
244 ... Resistor circuit, 246, 250, 260 ... Line, 248 ... Connector, 254, 256, 268 ... Diode, 262, 270, 27
2, 278, 280 ... Resistance, 276 ... Low-pass filter, 282, 284
...... Capacitor, 286 …… Sample and holding circuit, 288, 29
0, 294, 300, 304, 306, 312, 314, 318 ... Line, 292
...... Analog / digital conversion circuits, 296, 320 ...... Pull-up resistors, 298,316 ...... Buffers, 302 ...... Flip-flops, 310,328,336,340 ...... Connectors, 322,324
...... Line array, 326 …… Data bus, 330,338 ……
Line, 332 ... Field effect transistor, 342 ... Converter, 366,370 ... Resistance, 380 ... Microprocessor, 382 ... Oscillator, 386,394 ... Counter, 400 ... R
AM / timer circuit, 402, 410, 416, 418 ... Bus, 40
4 ... UART, 406, 446, 472 ... Pull-up resistor, 41
2 ... PROM, 420, 450, 452 ... Latch, 424, 434,
442 ... Buffer, 426,444 ... Line array, 428,432
...... Dip switch array, 430 ... Resistance array, 474 ... Decoder, 502,510 ... OR gate, 520 ...
… Switch, 524 …… Resistance, 526… Capacitor, 528…
… Diodes, 532… Gates, 538, 548, 578, 580…
... Inverter, 542, 552 ... Buffer, 558 ... Timer, 564 ... OR gate, 572 ... Counter, 574, 588 ...
…flip flop.

Claims (30)

[Claims] 1. In an electronic figure system, means for defining a figure making surface (10), and locator means movable near the figure making surface and interacting with the figure making surface to generate a position signal. (20)
And a digital position signal (x
Circuit means for generating (n, m), y (n, m)), and regularly between the maximum value (x _max , y _max ) and the minimum value (x _min , y _min ) of the digital position signal. Incremented value (x
The calculated coordinate value (x _a , y _a ) of the physical area as a value corresponding to a predetermined number of digital signals of the digital position signal in the signal area, which is the digital position signal of _r + y _r ).
Is a storage means for storing, and the coordinate value of the physical area is
Storage means for storing an address value produced by the regularly incremented value, and in response to each of the digital position signals, generating one of the address values corresponding to the digital position signal, The storage means is accessed by the generated address value to search for the coordinate value of the physical area, and the coordinate value of the searched physical area is adjusted by an interpolation weighting operation corresponding to the digital position signal, and corrected. And a control means for generating a coordinate pair output signal. 2. The electronic figure system according to claim 1, wherein the address value of the storage means corresponds to a rectangle of a signal area which defines its corner by four coordinate values of the physical area. An electronic figure system characterized in that 3. An electronic figure system according to claim 1, wherein the address value of said storage means is made up of a predetermined number of upper bits of said digital position signal. 4. An electronic graphic system according to claim 3, wherein the interpolation weighting operation by the control means is executed on a predetermined number of lower bits of the digital position signal. . 5. The electronic graphic system according to claim 2, wherein said control means is responsive to said digital position signal and corresponds to four coordinate values of a physical area.
One weighting factor is generated and the weighting factor is added to each to obtain a weighted coordinate pair value, and the obtained coordinate pair values are added to generate the corrected coordinate pair output signal. An electronic graphics system configured to perform an interpolation weighted operation. 6. The electronic figure system according to claim 5, wherein the address value of said storage means comprises a predetermined number of high-order bits of said digital position signal, and said interpolation weighting operation by said control means comprises: An electronic figure system characterized by being performed by a predetermined number of lower bits of a digital position signal. 7. An electronic graphic system according to claim 6, wherein said control means is of the formula x · y (where x
And y are lower bits), the weighting factor is obtained. 8. An electronic figure system according to claim 1, wherein said control means performs a two-dimensional interpolation weighting operation in response to the received digital position signal. 9. A method performed in an electronic graphics system for producing an electrical signal that is selectively accessed on one surface to produce an output corresponding to the accessed location, the method comprising: In the method of correcting the value of the output, the calculated coordinate value of the physical area obtained as a value corresponding to the output of the signal area, each of which is within a predetermined grid array of the physical area. A step providing storage means for storing the coordinate values of the physical area, which are set for the position and adjusted to set a sequence of regularly incremented address values in the signal area; A step of obtaining the address value, a coordinate value search step of accessing the storage means at the obtained address value to retrieve the coordinate value of the physical area corresponding to the address value. Adjusting a coordinate value of the searched physical region to obtain a correction output by a two-dimensional interpolation weighting operation corresponding to the output, outputting the correction output to determine a position accessed on the surface. A method comprising the step of generating coordinate information representing. 10. The method of claim 9 wherein the address value is obtained from a predetermined number of high order bits of a digital signal generated as the output. 11. The method according to claim 10, wherein the adjusting step is a weighting factor obtained from the output and added to the coordinate value of the searched physical area. The method is characterized by being performed by an interpolation weighting operation with a weighting factor that is set. 12. The method according to claim 11, wherein each address value of the storage means corresponds to a rectangle of the signal area, and four corners of the rectangle are four coordinate values of a physical area. And the interpolation weighting operation is performed by four weighting factors each added to a coordinate value of a physical region corresponding to one of the four corners. 13. The method according to claim 9, wherein the adjusting step is performed by a two-dimensional interpolation weighting operation corresponding to the output. 14. A surface of known geometry is selectively accessed on the surface to generate an electrical signal, the electrical signal providing a digital output indicative of the location of the accessed physical region. A method for use in an electronic graphics system that is processed in a method for compensating the obtained digital output for changes in the surface, the method comprising: physically positioning on the surface in a physical region. Determining a grid array having a plurality of possible positions; in the signal domain, generating the electrical signal to associate the digital output with a position of the grid array in a physical domain; in the signal domain, the digital output The value of the signal region (x _r , which is regularly incremented between the maximum and minimum values of the output)
y _r ), generating an address value from the sequence of values of the signal domain, coordinate values (xa, ya) of the physical domain corresponding to each of the values of the signal domain in the sequence A step of storing the coordinate values of the generated physical area in the address value of the storage means, a step of generating the address value from the digital output, the storing at the generated address value Accessing the means to retrieve the coordinate value of the physical area, the coordinate value of the retrieved physical area is corrected by an interpolation weighting operation for weighting with a factor obtained from the digital output to obtain a corrected output. Generating an interpolation weighting step, outputting the corrected output to provide coordinate pair information representing a physical region Wherein that you are. 15. The method according to claim 14, wherein the interpolation weighting operation of the coordinate values of the physical area is performed by a two-dimensional interpolation weighting operation. 16. The method according to claim 14, wherein the grid array is a rectangular grid array made up of grid lines whose positions are defined by respective sections, and the address value of the storage means is The method is characterized by corresponding to each area of the signal area including a number of areas approximately equal to the coordinate value of the physical area. 17. The method according to claim 16, wherein the address value of the storage means in each of the individual areas is given as a predetermined number of high-order bits of the corresponding digital output. . 18. The method according to claim 14, wherein each of the digital outputs is obtained as a digital signal, and the address value for correction is obtained as a predetermined number of upper bits of the digital signal. A method characterized by. 19. The method according to claim 14, wherein the interpolation weighting step is performed by a two-dimensional interpolation weighting operation corresponding to the digital output. 20. A method implemented in a system in which a resistive surface is positionally accessed to produce an output of a position in a signal domain with respect to a grid position that constitutes a predetermined array within a physical area of the resistive surface. Then, in the method of correcting the output, a value corresponding to the output of the signal area is set, each position of the physical area in the array is set, and the address value of the signal area is regularly incremented. Providing storage means for storing the calculated coordinate values of the physical area, adjusted to form a sequence, obtaining said address value from said output, accessing said storage means by said address value Providing a coordinate value of a physical area, and performing access by performing a two-dimensional interpolation weighting operation corresponding to the output. Adjusting the coordinate value of the physical area provided by to obtain a corrected output of the output, and outputting the corrected output to generate coordinate value information representing the position of access on the surface. A method characterized by including. 21. A method of generating a look-up table in a storage means used to interpolate an output of a position in a signal area corresponding to a position in an accessed physical area on a resistance surface, the resistance surface. Representing the physical and signal domain characteristics of
A step of collecting an input data set from the resistance surface; a step of determining a boundary of the input data set as a maximum value and a minimum value of a signal region with respect to first and second coordinate directions; And an increment value generating step for generating a value (x _r , y _r ) of the signal region which is regularly incremented between the minimum value and the respective values of the signal region for each of the first and second coordinate directions. A first evaluation value (i ', j') of the corresponding position coordinate of the physical region on the resistance surface, which is determined based on the known position and the characteristic of the signal region of the input data set. Providing a first evaluation value of position coordinates, interpolated for each of the first and second coordinate directions from the first evaluation value of the input data set and a value adjacent to the evaluation value. Physical area An interpolated coordinate generation step of generating the coordinate value of the interpolated coordinate area, and a step of storing the interpolated coordinate value of the physical area in the storage means at the address value obtained from the value (x _r , y _r ) of the signal area. A method characterized by being out. 22. The method according to claim 21, wherein the method is predetermined from the coordinate value of the interpolated physical area obtained immediately before the address value of the storage means is determined. And testing the coordinate values of the interpolated physical region for changes in the error level. 23. The method of claim 21, wherein the input data set corresponds to a set of grid point positions aligned with predetermined coordinates in a physical region. 24. The method of claim 23, wherein said collecting step accesses said resistive surface by reading means at regularly spaced grid point positions aligned with a predetermined number of coordinates. To generate a row voltage level and a column voltage level at the grid point position, and to convert the row and column voltage levels into digital values constituting the input data set. . 25. The method according to claim 21, wherein the increment value generating step is performed using a number of increments greater than a predetermined number of grid point positions of the input data set. How to characterize. 26. The method of claim 21, wherein the interpolated physical region coordinate values are obtained using Newton's interpolation. 27. The method according to claim 21, wherein the interpolation coordinate generation step determines a correction value in an interpolation manner, and the correction value is the first evaluation value of the coordinate value of the physical area. To obtain a second evaluation value thereof. 28. The method of claim 26 including the step of testing the coordinate values of the interpolated physical area by comparing the correction value with a predetermined tolerance criterion. how to. 29. The method according to claim 21, wherein the first evaluation value of the coordinate value of the physical area is given as the next interpolation value. 30. In an electronic graphics system for selectively accessing a surface of a known form to generate an electrical signal that is processed to produce an output corresponding to the physical location accessed, with respect to changes in the surface. A method of correcting the value of the output, comprising: collecting from the surface an input data set representing physical area characteristics and signal area characteristics of the surface; a maximum value of the signal area in the first and second coordinate directions; Determining a minimum value to determine a range of a signal region of the input data set, addressable at regular increments between the maximum and minimum values for the first and second coordinate directions. Na first
And a second set of values, the coordinate position of a physical region on the surface corresponding to the first and second addressable sets of values for each of the first and second coordinate directions. A step of performing an evaluation to obtain a first evaluation value; a step of obtaining the coordinate value of the physical region for each of the first and second coordinate directions from a first evaluation value and an adjacent value of the input data set; Storing the interpolated value of the coordinate value of the physical area in the storage means in combination with the set of addressable first and second values of the area; Accessing the storage means to retrieve the coordinate value of the physical area; adjusting the coordinate value of the physical area by interpolation weighting operation to obtain a corrected output corresponding to the output; outputting a corrected output Then, How it is assumed that the features, including the step of generating the coordinate pair information representing the physical position of the over data.