JPH0621455A - Thin-film transistor - Google Patents

Abstract

PURPOSE:To increasing the channel width of gate electrode of thin-film transistors while preventing short circuits by coating the upper surface, lower surface and opposite sides of a semiconductor region. CONSTITUTION:A first gate electrode layer 3 is formed on an insulating layer 2 covering a silicon substrate 1, and it is etched into a band. After a first gate insulator 4 is formed, a semiconductor layer 5 is deposited and etched into a band perpendicular to the first gate electrode layer 3. A second gate insulator 6 is formed over the exposed surface of the semiconductor layer 5. As a result, the gate insulators 4 and 6 takes an annular shape that continuously covers all the sides of the semiconductor layer 5. After contact holes 7 are opened in the second insulator 6, a second gate electrode layer 8 is deposited and it is etched into a band to form an annular gate electrode. An active semiconductor region 5a is formed, and finally an insulator 9 and electrodes are formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (TFT) used for an active matrix type liquid crystal display or the like.

[0002]

2. Description of the Related Art In recent years, active research has been conducted on forming TFTs on a silicon substrate or an insulating substrate. One of the aims is to realize a thin, high-quality, large-diameter active matrix display. That is,
TFTs are formed in a matrix on a substrate, and the switching characteristics of the TFTs are applied to achieve thin displays such as liquid crystals. Regarding the transistors of the active matrix type liquid crystal display configured in this way,
There are many reports, including "Flat Panel Display 91 '" (published by Nikkei BP).

Among such displays, in particular,
For liquid crystal televisions, it is necessary to significantly reduce the area occupied by pixels in order to support high definition. In order to realize this, it is required to reduce the gate electrode, the video signal line, and the size of the switching transistor.

As described above, the miniaturization of the TFT is unavoidable in the future, but at this time, there arises a problem that the current driving capability of the TFT is reduced due to the miniaturization and miniaturization of the TFT and the reduction of the channel width.

In order to avoid this, a gate electrode is provided not only on the upper surface of the semiconductor active region of the TFT but also on the lower surface,
So-called double gate type TFTs have been proposed which can substantially increase the channel width of the TFT.

However, in the double gate type TFT, not only is there a practical limit to the effect of widening the channel width, but also the upper and lower gate electrodes are formed thin to suppress the increase in the thickness of the TFT. This has a drawback that an accident of short-circuiting the gate electrode is likely to occur.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned prior art, and it is possible to substantially increase the channel width while avoiding a short circuit of the gate electrode due to the miniaturization of the TFT. Is realized.

[0008]

A TFT of the present invention is a thin-film semiconductor region, a ring-shaped gate insulating film that continuously covers the upper and lower and opposite side surfaces of the semiconductor region, and the surface of the gate insulating film is continuous. And a source electrode connected to one end of the semiconductor region, and a drain electrode connected to the other end of the semiconductor region.

[0009]

According to the TFT of the present invention, not only the upper and lower sides of the semiconductor region of the TFT, but also the opposite side surfaces are continuously covered with the gate insulating film and the gate electrode film. The presence of the two side portions enables the channel width to be effectively expanded, and the upper and lower gate electrodes are electrically coupled by the two side portion gate electrodes, so that one electrode is short-circuited and electrically isolated. You can avoid accidents.

[0010]

EXAMPLE FIG. 1 schematically shows a plan view of a TFT according to an example of the present invention. Further, FIG. 2 shows the TFT A of FIG.
-A 'sectional view, FIG. 3 shows the BB' sectional view of the TFT of FIG. 1 in order of process.

In these figures, 1 is a silicon substrate, 2 is
Is an insulating film, 3 is a first gate electrode film, 4 is a first gate insulating film, 5 is a semiconductor film, 5a is a semiconductor active region, 5b is a doped semiconductor region, 6 is a second gate insulating film, and 7 is a gate insulating film. 4 is a contact hole, 8 is a second gate electrode film, 9 is an inter-membrane insulating film, and 10 is a metal electrode used as a source electrode or a drain electrode.

The manufacturing method of the TFT of the present invention will be described below with reference to the sectional views of the manufacturing steps of (a) to (d) in FIG. 2 and (a) to (d) in FIG.

In FIG. 2A and FIG. 3A, an insulating film 2 is formed on the surface of the silicon substrate 1 by using a thermal oxidation method. The substrate temperature in this thermal oxidation process is about 1
At 000 degrees, the thickness of the insulating film 2 is about 200 nm. Three
Is a first gate electrode film, a polycrystalline silicon film having a thickness of about 200 nm is deposited on the insulating film 2 by using a low pressure CVD method, and a sheet resistance value is about 10 by using a phosphoric acid diffusion method.
It is formed with 0%.

In FIG. 2B and FIG. 3B, the first gate electrode film 3 of the laminated body obtained in the above step is formed into a band shape by photolithography. Reference numeral 4 is a first gate insulating film, which is formed on the surface of the stacked body by a thermal oxidation method. The substrate temperature at that time is about 100.
At 0 degrees, the film thickness is about 50 nm. Reference numeral 5 is a semiconductor film, and a polycrystalline silicon film having a film thickness of 2 is formed by using the low pressure CVD method.
It is deposited to a thickness of 00 nm on the surface of the stacked body, and is further photolithographically etched to form a strip shape that intersects the first gate electrode film 3.

2C and 3C, the second gate insulating film 6 of the laminated body is formed on the entire exposed surface of the semiconductor film 5 by the thermal oxidation method. The substrate temperature at that time is about 10
At 00 degrees, the film thickness is about 50 nm. In this case, the insulating films 6 on the side surfaces facing the insulating films 4 and 6 above and below the semiconductor film 5,
6 continuously forms an annular gate insulating film covering the periphery of the semiconductor film 5. Reference numerals 7 and 7 are contact holes, and openings of a predetermined shape are provided in the second gate insulating film 6 by using photolithography etching. Reference numeral 8 is a second gate electrode film, which has a film thickness of 200 n using a low pressure CVD method.
After depositing a polycrystalline silicon film of m, photolithography is used to form a strip shape along the extending direction of the first gate electrode film 3. At this time, the contact holes 7, 7 bring the first gate electrode film 3 and the second gate electrode film 8 into conduction, thereby forming an annular gate electrode. Then, when phosphorus is doped into the semiconductor film 5 and the second gate electrode 8 by using an ion implantation method, the semiconductor film 5 has non-doped semiconductor active regions 5a and TF.
Doped semiconductor regions 5b serving as T drain regions or source regions are formed, respectively.

2 (d) and 3 (d), the inter-layer insulating film 9 in the upper layer of the laminated body is formed of silicon oxide on the surface of the laminated body with a thickness of 300 nm by the CVD method. Deposition and photolithography are used to provide openings of predetermined shape to form the source and drain electrodes. Reference numeral 10 denotes a source electrode and a drain electrode, which are respectively connected to the doped semiconductor regions 5b exposed from the opening by using a usual aluminum sputtering method.

The TFT thus obtained has the gate insulating films 4 and 6 and the gate electrode films 3 and 8 which continuously cover not only the upper and lower sides of the semiconductor active region 5a but also the opposite side faces. By providing the gate insulating film and the gate electrode, the two side surfaces of the semiconductor active region 5a are provided. Therefore, the channel width can be surely expanded by adding both side surface portions of the semiconductor active region 5a, and the upper and lower gate electrodes are electrically coupled by the two side surface partial gate electrodes. It is possible to avoid an accident in which the electrodes of 2 are short-circuited and electrically isolated.

Although the silicon substrate is used as the substrate in the above-mentioned embodiments, the present invention can be applied to a TFT formed on an insulating substrate such as quartz glass.

[0019]

According to the TFT of the present invention, not only the upper and lower sides of the semiconductor active region, but also the opposite side faces are continuously covered with the gate insulating film and the gate electrode film, so that the semiconductor active region is covered with the gate insulating film. The presence of two side surface portions can effectively increase the channel width, and since the upper and lower gate electrodes are electrically coupled by the two side surface portion gate electrodes, one of the electrodes is short-circuited and electrically connected. It is possible to avoid the accident of isolation and contribute to the improvement of reliability as a transistor.

[Brief description of drawings]

FIG. 1 is a plan view of a TFT of the present invention.

FIG. 2 is a process cross-sectional view of the TFT of the present invention in the AA ′ direction in FIG.

FIG. 3 is a process cross-sectional view of the TFT of the present invention in the BB ′ direction in FIG.

[Explanation of symbols]

 1: Silicon substrate 2: Insulating film 3: First gate electrode film 4: First gate insulating film 5: Semiconductor film 5a: Semiconductor active region 5b: Doped semiconductor region 6: Second gate insulating film 7: Contact hole 8: Second 2 gate electrode film 9: semiconductor region 10: inter-membrane insulating film 11: metal electrode

Claims (1)

[Claims] 1. A thin-film semiconductor region, a ring-shaped gate insulating film continuously covering upper and lower and opposite side surfaces of the semiconductor region, a ring-shaped gate electrode continuously covering the surface of the gate insulating film, A thin film transistor comprising a source electrode connected to one end of a semiconductor region, and a drain electrode connected to the other end of the semiconductor region.