JPH06214525A - Method for driving gas discharge light emitting device - Google Patents

Abstract

PURPOSE:To provide a method for driving a gas discharge light emitting device capable of avoiding erroneous discharge even when the dispersion in the shape of a priming slit exists. CONSTITUTION:In the case of impressing an erasure pulse PE to a cathode immediately after a scanning pulse PK, at least one of a cathode maintaining pulse PCP is impressed to the cathode side for lowering the erasing voltage VK level of the erasure pulse to a cathode prebias voltage VCP transiently. At this time, the cathode maintaining pulse is impressed in the timing of the maintaining voltage level of at least one maintaining pulse PSP. Further, the pulse width tauCP of the cathode maintaining pulse is made shorter than the pulse width tauCP of the maintaining pulse.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gas discharge light emitting device,
For example, a DC type gas discharge display panel (so-called D
The present invention relates to a method for driving a C-type PDP), particularly a method for driving a gas discharge light emitting device of a memory type.

[0002]

2. Description of the Related Art In recent years, panel displays have been actively developed and put to practical use, and small televisions have been realized by liquid crystal or flat CRT in the field of television display. However, large panel displays have not been put to practical use. Instead, the introduction of the memory function into gas discharge display panels is being promoted toward the practical application of large-sized panels.

Regarding a conventional gas discharge display panel, there is one disclosed in Document I (Document I:
"Flat configuration panel memory-type discharge panel for color television display", Journal of Television Society, Vol. 40, No.
10, 1986).

The structure and driving method of the gas discharge display panel disclosed in Document I will be briefly described below with reference to FIGS. 2, 7 and 8.

FIG. 7 is a perspective view showing the structure of the gas discharge panel disclosed in Document I.

This panel includes a rear plate 10 and a front plate 2.
It is mainly composed of 0s. A plurality of cathodes 12 are arranged in parallel on the back plate 10, and a display cell 16 is provided on the cathode side.
Further, a partition wall 18 that defines the auxiliary cell 14 is provided.

Further, an anode 22 and an auxiliary anode 24 are arranged in parallel on the translucent front plate 20 (for example, a glass substrate) so as to intersect with the cathode 12, and a phosphor 26 is applied.

This structure has a rear plate 10 and a front plate 20.
In a state where the substrates are aligned so that the electrode formation surfaces of the substrates face each other and the cathode 12 and the anode 22 and the auxiliary anode 24 intersect with each other, the outer peripheral portions of these substrates are sealed via the airtight sealing portion. A gas medium for discharge is contained in the enclosed area between them.

FIG. 2 is a diagram schematically showing a wiring structure for explaining a conventional memory type driving method. Further, FIG. 8 is a time chart for explaining a conventional memory type driving method.

First, the wiring structure for driving the panel will be described with reference to FIG. In order to simplify the description, the gas discharge panel has four display anodes 22 _{01 to} 22 _04.
And it comprises four cathodes 12 _{01-12 04,} thus 4x4
It is assumed that the display cells 16 _MN are arranged in columns (reference numeral 16 _MN represents a display cell in the Mth row and the Nth column).

The display cell 16 _MN is formed in a region where the display anode and the cathode intersect. The auxiliary anodes 24 ₀₁ and ₂₄₀₂ are arranged between the display anodes 22 ₀₁ and 22 ₀₂ and between the display anodes 22 ₀₃ and 22 ₀₄ .

According to the wiring of the document I, in order to drive the panel 28, each of the anodes 22 _{01 to} 22 ₀₄ is connected to the write pulse generating circuit 30 via the diode D ₂ and is maintained via the diode D _1. It is connected to the pulse generation circuit 32. The connect each of the cathode 12 _{01-12 04} and the scan pulse and the erase pulse generating circuit 34, further, the auxiliary anodes 24 ₀₁ and 24 ₀₂ through resistor 36 Power 38
Connect to. The diodes D ₁ and D ₂ form an adder for mixing the write pulse and the sustain pulse. Further, one ends of the power supply 38, the scan pulse and erase pulse generating circuit 34, the sustain pulse generating circuit 32, and the write pulse generating circuit 30 are grounded.

Next, a conventional method of driving a gas discharge panel will be described with reference to FIGS. 2 and 8.

First, when the panel 28 is driven, FIG.
As shown in, the scanning pulse P _K (pulse width τ
_K , amplitude V _K ) in the first, second, third, and fourth rows
The cathodes 12 ₀₁ , 12 ₀₂ , _{120 3} , ... Of the row are sequentially applied. Note that FIG. 8 shows only the cathodes in the first to third rows.

On the other hand, the sustain pulse P _sp (pulse width τ _sp , amplitude V _sp ) is applied to the anodes 22 _{01 to} 22 ₀₄ at a cycle T. The scan pulse P _K and the sustain pulse P _sp are applied so that their timings do not overlap. For example, time t ₁ to time t ₂
During the period of, the scanning pulse P _{K is applied} to the cathode (12 ₀₂ ) of the second row.
Apply to. At this time, the sustain pulse P _sp is _generated by the anode 22 _01-
Applied to the scan pulse P _K and the sustain pulse P _sp.
The discharge of the display cell is not started because the timings do not overlap with.

A constant positive potential is constantly applied to the auxiliary anodes 24 ₀₁ and ₂₄₀₂ by the power source 38. Therefore, when the scanning pulse P _K is applied, the auxiliary cells of the cathode are sequentially discharged. (In the figure, the first line, the second line, the third line, ... Of the auxiliary cell currents). Since the scanning pulse P _K is applied to the second row ( ₁₂₀₂ ) during the period from time t ₁ to time t ₂ ,
A discharge current flows through the auxiliary cells in the second row (12 ₀₂ ).

For example, when the display cell 16 ₂₂ is written, the writing pulse P _W (pulse width τ _W , amplitude V _W ) is applied to the second writing pulse P _W at substantially the same timing as the discharge of the auxiliary cells in the second row.
Apply to the anode 22 ₀₂ of the column. At this time, the display cell 16 ₂₂
Charged particles, metastable particles, or the like from the auxiliary cells in the second row, which are discharged in the vicinity, are diffused into the display cell 16 ₂₂ . Therefore, since the discharge delay time of the display cell 16 ₂₂ can be shortened, the variation in the discharge delay of the display cell is greatly reduced. Even if the writing pulse width τ _W is narrowed and the writing voltage V _W is reduced, the writing voltage V _W and the scanning voltage V _W
The display cell 16 ₂₂ discharges due to the potential difference of _K.

The driving method of this document I is such that the write pulse P
After the discharge is stopped by _W , the sustain pulse P _sp is applied so that the sustain pulse P _sp is applied in a state where the discharge is likely to occur again.
The period T of _sp is set. Therefore, the write pulse P _W
After the display cell 16 ₂₂ is discharged by the need not to apply a write pulse P _W, e.g. in the period of time t ₃ ~ time t _4, the discharge of display cells 16 ₂₂ second row of anodes (22 ₀₂₎ The pulse is maintained (intermittently) by the sustain pulse P _SP applied to the. At this time, the ultraviolet light generated by the discharge reaches the phosphor 26 and is absorbed by the phosphor 26.
Light is emitted, and the display cell 16 ₂₂ enters the display state.

Next, when stopping the discharge of display cells 16 _22, the cathode 12 ₀₂ by applying an erase pulse P _E to the cathode 12 ₀₂
The potential difference between the erasing voltage V _E and the anode pre-bias voltage is reduced by forcibly raising the potential. For example the period of time t ₅ ~ time t _6, the discharge by the sustain pulse P _sp by applying an erase pulse P _E so as not occur more than once. Therefore, the charged particles and the like decrease or disappear, and the display cell 16 ₂₂ does not re-discharge even when the sustain pulse P _sp is applied.

Further, the driving method of the literature I, after discharge by a write pulse P _W, as sustain pulse P _sp is applied within the re-discharge state of easily, to set the period T of the sustain pulse P _sp The memory driving method is adopted, and by doing so, the emission intensity is improved so that sufficient brightness of the panel can be obtained even when the number of scanning lines is large (for example, the number of scanning lines is 1000). .

Next, reference II (Japanese Patent Laid-Open No. 63-12729).
0) discloses a method for preventing erroneous discharge due to over-priming.

The driving method disclosed in Document II will be briefly described with reference to FIG.

First, the sustain pulse P _SP is applied to the anode at a constant cycle. Next, the write pulse P _W is applied at substantially the same timing as the scan pulse P _{K for the} cathode. In addition, V
_SP represents the sustain voltage.

On the other hand, the cathode is a cathode pre-bias voltage V _CA.
Immediately after the scan pulse P _K is applied from the state, the erase pulse P _E is applied for a predetermined period T _R.

Next, the cathode sustaining bias voltage V _{CA is} lowered. In the figure, V _E represents the erase voltage and V _K represents the scan voltage.

In the driving method disclosed in Document II, immediately after the scan pulse P _K is applied to the potential of the cathode, a T _R erase pulse is applied for a predetermined period to erase voltage level V V for a predetermined period.
Hold at _E. By such a method, the erase pulse P
_{Even if the E} application period T _R is lengthened, the maximum voltage V _PSmax of the sustain voltage V _SP increases, so that the voltage _margin also expands.
It is reported that erroneous discharge due to bar priming can be suppressed (see FIG. 10). The maximum voltage V _PSmax is
The maximum voltage that can be driven without erroneous discharge.

[0027]

However, in the driving method disclosed in the above-mentioned conventional document I, the write pulse is applied at almost the same timing as the application of the scan pulse, and the auxiliary cell and the display cell are discharged. Wake up. Immediately thereafter, the sustain pulse is applied. Therefore, many charged particles or metastable particles generated by the auxiliary discharge of the auxiliary cell are supplied to the display cell adjacent to the auxiliary cell (this phenomenon is called over-priming).
Therefore, there is a problem in that the sustain pulse P _SP causes an erroneous discharge in the display cell immediately after the auxiliary discharge without applying the write pulse.

The driving method disclosed in Document II is an example of a driving method for improving erroneous discharge due to over-priming.

However, in this driving method, the maximum voltage (hereinafter, V
_It is called _SPmax . ) Was reduced. This point will be described in detail with reference to FIG.

FIG. 5 is an experimental data diagram showing a relationship in which V _SPmax changes depending on the size of the priming slit.

In the figure, the horizontal axis represents the erase pulse period T _R and the vertical axis represents the sustain pulse voltage V _SP . Further, the curve 105 is V _SPmax , and the curve 107 is the minimum voltage (hereinafter, V _SPmax) .
_{Called SPmin} . ) Is shown. It should be _noted that V _SPmin represents the minimum voltage at which all cells can be pulse- _memorized .

FIG. 5 is a plot showing the relationship between the erase pulse voltage level period T _R immediately after the scan pulse and the sustain pulse voltage V _SP with the sustain pulse period T of 4 μs and the pulse width τ _s of 1 μs.

[0033] According to this V _SPmin is the V _SPmin rising period T _R is short and sustain pulse voltage of the erase voltage levels were scarcely seen, increase gradient becomes larger as the period T _R becomes longer. The reason for this is that the write pulse P _w
This is because the charged particles and the like generated in step 1 disappear with time. While the period T _R is short, the priming effect is strong even if the number of charged particles and the like is reduced, so that all cells can be pulse-memorized by discharging their own cells. However, as the period T _R becomes longer, the charged particles and the like decrease with time, resulting in an increase in V _SPmin .

On the other hand, V _SPmax is influenced by charged particles and the like supplied from the auxiliary cell through the priming slit, and originally the charged particles and the like supplied to the display cell are small, so that the cycle T _R becomes long. With V
_SPmax will also rise.

As can be understood from FIG. 5, when the priming slit of the gas discharge cell is increased, the value of V _SPmax is lowered as shown by the dotted line 109. Therefore, the voltage margin that can be driven stably becomes smaller,
There was a problem that it could lead to erroneous discharge.

The present invention has been made in view of the above-mentioned problems, that is, an object of the present invention is to drive a gas discharge light emitting device capable of avoiding erroneous discharge even if there are variations in the shape of the priming slit. To provide.

[0037]

In order to achieve this object, according to the method for driving a gas discharge light emitting device of the present invention,
At least an anode sustain pulse is applied to the anode, and at least a scan pulse and an erase pulse are applied to the cathode immediately after the scan pulse to drive the gas discharge light-emitting device of the pulse memory system. A cathode sustaining pulse for temporarily lowering the cathode pre-bias voltage is applied to the cathode during at least one sustaining pulse.

Further, it is preferable that the pulse width of the cathode sustain pulse is shorter than the pulse width of the sustain pulse.

[0039]

According to the method of driving the gas discharge light emitting device as described above, the erase pulse is applied immediately after the scan pulse. At this time, in order to temporarily lower the voltage level of the erase pulse to the cathode sustaining bias, the cathode sustaining pulse is applied to the cathode side during at least one sustaining pulse. With such a driving method, the margin of the sustain pulse voltage at the time of writing can be expanded. Therefore, erroneous discharge due to overpriming can be improved without being affected by the variation in the shape of the priming slit.

The cathode sustain pulse width is set shorter than the sustain pulse width. By such a method, the voltage margin of the sustain pulse can be expanded.

[0041]

Embodiments of the present invention will now be described with reference to the drawings. First, before entering the method of the present invention, FIG.
The main structure of the gas discharge light emitting device (hereinafter referred to as DC type PDP) used in the embodiment of the present invention will be described with reference to FIG. Next, as an application example in which this device is driven, the driving method of this embodiment will be described using the time chart of FIG.

It should be noted that each of the drawings used for the description only schematically shows the shape, size, and positional relationship of each constituent component to the extent that the present invention can be understood.

FIG. 3 is a perspective view showing the structure of the DC type PDP used in the embodiment of the present invention. Note that the structure of FIG. 3 is described in Document III (“Ultra-low reflectance color display discharge panel (I
V) ”Sakai et al., IEICE Technical Research Report, EID
87-72, p55-60, Feb. (1988)).

In the figure, 10 is a back plate, 12 is a cathode, 14 is an auxiliary cell, 16 is a display cell, 18 is a partition wall, 20 is a front plate, 22 is an anode, 24 is an auxiliary anode, 26 is red, green and blue. And a reference numeral 27 indicates a priming slit.

Next, FIG. 2 shows a drive circuit used in the embodiment of the present invention. Since this drive circuit diagram has a wiring structure similar to that of the drive circuit of Document I, detailed description thereof will be omitted.

Next, referring to FIG. 1, FIG. 5 and FIG.
A method for driving the operation of the type PDP will be described.

FIG. 6 is a diagram showing the relationship between the sustain pulse width τ _SP and the margin of the sustain pulse voltage (see Reference III).

In the figure, the horizontal axis represents the sustain pulse width τ _S (μs),
The vertical axis represents the sustain pulse voltage V _S (V). Also,
The dotted line 101 is V _SPmax and V _SPmin when the erase pulse is not applied after the scan pulse P _K , and the solid line 103
_Represents V _SPmax and V _SPmin when a predetermined erase pulse P _E is applied after the scan pulse P _K.

As can be understood from FIG. 6, by making the sustain pulse width τ _s smaller than _{1.0 μs} , V _SPmax of the solid line 103 is sharply increased.

On the other hand, as τ _SP becomes shorter, the solid line 10
V _SPmin of 3 shows a gradual increase as compared with V _SPmax . The period T of the sustain pulse when this experimental data was obtained was driven at 4 μs.

A method of driving the write sustaining characteristics in consideration of having such margin characteristics will be described with reference to FIG.

First, the sustain pulse P _SP and the write pulse P _W are applied to the anode, while the scan pulse P _K is applied to the cathode.
And erase pulse P _E is applied. The high voltage level of the sustain pulse P _SP at this time is referred to as the sustain voltage V _SP, and the low voltage level thereof is referred to as the anode pre-bias voltage V _AP . Incidentally, the anode, for explaining the maintenance operation by the write pulse P _W, represents the address pulse P _W and sustain pulse P _SP synthesized and.

The low voltage level of the scan pulse P _K of the cathode (the voltage level is opposite to that of the anode because the sign is negative) is called the scan voltage V _K, and the high voltage level is the cathode Pare bias voltage V _CA. To call.

The high voltage level of the erase pulse V _E is called the erase voltage V _E. Further, at least one pulse having a small amplitude width applied during the erase pulse is referred to as a cathode sustaining pulse P _CP .

When the discharge is started, immediately after the scan pulse P _K (the period from time t ₁ to time t ₂ ) is applied to the cathode side, the erase pulse P _E for about two cycles of the period T of the sustain pulse P _SP is applied. Is applied to the cathode (time period from t ₃ to t ₄ ).
At this time, the erase voltage V _{E is set} to 0V, for example. In addition, the sustain pulse width τ _SP applied at time t ₃ and the voltage marker
The relationship with gin is known from the curve of curve 103 from FIG. In this embodiment, the pulse width of the cathode sustaining pulse P _CP is set to, for example, 0.6 μs. At this time, from FIG. 6, τ = 0.
_Margin (value of V _SPmax −V _SPmin ) of _{6 μs} is about 32.
It becomes V. In Reference II, since it is 1.0 μs, the voltage margin is about 22V. Therefore, by shortening the pulse width, it is possible to increase the margin by about 10 V as compared with Reference II.

As described above, since writing is performed in a region where the voltage margin is large, the display cell can maintain stable discharge. Further, the display cell in which writing is not performed does not maintain the discharge.

Next, a cathode sustaining pulse P is applied to the erase pulse P _E.
After applying at time t ₅ and t ₇ the _CP, lowered to the cathode pre-bias voltage (e.g. -80 V) (time t _7). The cathode sustaining pulse width τ _CP is, for example, 0.6 μs.

Further, since the display cell in which the writing is performed maintains the discharge by the cathode sustaining pulse P _SP , V at the time t _{7
The SPmin} value is about 142V from Fig. 6 (sustain pulse width τ
_SP = value of V _SPmin of _{1.0 μs} ).

On the other hand, no discharge is generated by the cathode sustaining pulse P _{CP in the} display cells in which writing is not performed. At this time, the period of the sustain pulse corresponds to ₁₆ μs, and the value of V _SPmax is shown in FIG.
To about 175V. Sustain pulse width τ _SP = 1.0 μs
_Since the value of V _SPmin is about 142 V, the
Zin becomes 175V-142V = 33V. This value is
The voltage margin with a pulse width τ _SP = 1.0 μs was about 23 V, which is an improvement of about 10 V for the margin.

Further, even if the priming slit becomes large, V _SPmax does not decrease by increasing the number of cathode sustaining pulses P _CP applied. For this reason,
A malfunction due to over-priming can be suppressed. The reason is that by applying the cathode sustaining pulse P _CP ,
This is because charged particles and the like can be generated at appropriate times.
Therefore, since the writing operation is performed in a wide range of the voltage margin, the discharge of the display cell can be intermittently and stably maintained.

On the other hand, the display cells in which writing is not performed do not maintain discharge. Therefore, stable writing and erasing operations can be performed without being affected by variations in the shape and size of the priming slit.

Next, referring to FIGS. 2 and 4, a DC type PDP will be described.
The driving method of will be described in detail. Note that the description of the wiring structure used for driving the panel is the same as that in Document I, and thus the description thereof is omitted.

First, the scan pulse P _K , the erase pulse P _E and the cathode sustaining pulse P _CP are applied to the cathode. At this time, the voltage level of the pulse is set as follows. Scanning voltage V
For example, _K is −220 V, erase voltage V _E is 0 V, and cathode pre-bias voltage V _CP is −80 V, for example.

In the embodiment of the present invention, the cathode sustaining pulse width τ _CP is, for example, 0.6 μs, and the erase voltage level period T _R immediately after the scan pulse is, for example, 8 μs.

On the other hand, the sustain pulse V _K and the write pulse P _W are applied to the anode. The voltage level at this time is, for example, 160 V for the sustain voltage V _SP and 8 for the write voltage V _W.
The anode pre-bias voltage is 0V. At this time, the sustain pulse width τ _SP is, for example, 1 μs, and the sustain pulse period T is, for example, 4 μs.

In order to drive the panel 28 (see FIG. 2), a voltage is applied to the auxiliary anodes 24 ₀₁ and ₂₄₀₂ by using a power source 38, and an arbitrary suitable constant positive voltage is applied by the resistor 36.

Next, the scanning pulse P _{K is applied} to the cathode in the first row (12 ₀₁ ), the second row (12 ₀₂ ), and the third row ( ₁₂₀₃ ).
And the fourth line (12 ₀₄ ) are sequentially applied. At this time, the auxiliary cells to which the scan pulse P _K is applied are 22 ₀₁ , 22 ₀₂ , 2
It discharges in the order of ₀₃ and 22 ₀₄ .

For example, when the display cell 16 ₂₂ is discharged, the write pulse P _W is applied to the anode 22 ₀₂ in the second column at almost the same timing as the scan pulse P _{K for the} cathode (time t ₁ to time t _2). Period). At this time, charged particles and the like are diffused into the display cell 16 ₂₂ from the auxiliary cell in the second row which is discharged in the vicinity of the display cell 16 ₂₂ through the priming slit. Therefore, the discharge delay period of the display cell 16 ₂₂ can be reduced. After that, two cycles of the sustain pulse P _SP (T _R
Erasing pulse P _E of 8 μs) is applied (time t ₂ to time t ₃ ). Further, the charged particles and the like generated in the display cell 16 ₂₂ at this time are reduced. However, since the priming effect is still strongly maintained due to the charged particles generated by the own cell, the discharge of the display cell is maintained by applying the cathode sustaining pulse P _SP (time t ₃ to time t ₄ and time t _4). t period of ₅ to time t _6). Two cathode sustaining pulses P _CP were applied.

Next, the erase voltage (0 V) is lowered to the cathode pre-bias voltage (-80 V), and then the sustain pulse P _SP is applied to sustain the discharge (time t ₇ to time t).
Period of ₈ and time t ₉ ~ time t _10).

The cells other than the display cell 16 ₂₂ are the second cells.
Even if charged particles or the like generated in the auxiliary cells of the row are supplied to cells other than 16 ₂₂ cells, the discharge is not maintained by the cathode sustaining pulse P _CP . Therefore, the address sustain discharge can be selectively performed.

Further, the phosphor 26 is excited by using the ultraviolet rays generated by the discharge, and the panel is made to emit light.

Next, when the discharge of the display cell 16 ₂₂ is to be stopped, the erase pulse P _E is applied to the cathode 12 ₀₂ to apply it to the cathode 12.
By increasing the potential of _02, the potential difference between the erase voltage V _E and the sustain voltage V _CP is made smaller than the sustain voltage V ₀ (for example, 170 V) to reduce or eliminate charged particles (time t). period of ₁₁ to time t _12). Therefore, after the discharge is stopped by the application of the erase pulse P _E , it is necessary to apply the write pulse P _W when re-discharging.

By the driving method as described above, the voltage margin of the sustain pulse can be expanded during the write operation,
Even if there are variations in the priming slit, V _SPmax does not decrease. Further, since the margin is expanded, malfunction due to over-priming can be suppressed.

The present invention is not limited to the above-described embodiment, and therefore, the wiring structure or the driving circuit for realizing the driving method of the present invention, the signal waveform, the application timing of each signal, the pulse width, etc. The voltage value such as application time and pulse amplitude, numerical conditions, and the like can be arbitrarily changed.

In addition to this embodiment, the present invention can be applied to various gas discharge light emitting devices such as a display device, an optical head and the like.

[0076]

As is apparent from the above description, according to the driving method of the gas discharge light emitting device of the present invention, when the erase pulse is applied to the cathode immediately after the scanning pulse, the erase voltage level of the erase pulse is set to In order to temporarily lower the cathode pre-bias voltage, at least one cathode sustaining pulse is applied to the cathode side. At this time, the application timing of the cathode sustaining pulse is performed during the period of at least one sustaining pulse. The sustain pulse voltage is controlled by the driving method as described above.
Since the gin (the region of the difference between V _SPmax and V _SPmin ) can be made large, malfunction due to the over-priming effect can be remarkably suppressed. Therefore, even if the shape of the priming slit of the gas discharge light emitting device varies, the maximum voltage (V _SPmax ) does not decrease. Therefore, the gas discharge device can realize stable driving of the DC PDP with few malfunctions.

The pulse width of the cathode sustain pulse is set shorter than the pulse width of the sustain pulse.

By such a method, the margin of the sustain pulse voltage can be expanded. Therefore, malfunction due to over-priming can be improved.

[Brief description of drawings]

FIG. 1 is a time chart for explaining a write operation according to an embodiment of the present invention.

FIG. 2 is a wiring structure diagram for explaining an embodiment of the present invention and a conventional driving method.

FIG. 3 is a perspective view for explaining the structure of the gas discharge panel of the present invention.

FIG. 4 is a time chart diagram for explaining an embodiment of the driving method of the present invention.

FIG. 5 is a relationship diagram between an erase level period immediately after a scanning pulse and margin.

FIG. 6 is a diagram showing a relationship between sustain pulse width and margin.

FIG. 7 is a structural diagram of a conventional gas discharge display panel.

FIG. 8 is a time chart for explaining a conventional driving method.

FIG. 9 is a time chart of a conventional drive waveform.

FIG. 10 is a diagram showing a relationship between an erase voltage level period and a voltage margin.

[Explanation of symbols]

10: back plate 12: cathode 14: auxiliary cell 16: display cell 18: partition wall 20: front plate 22: anode 24: auxiliary anode 26: phosphor 27: Priming slit 28: panel 12 _{01-12 04:} number of rows in the cathode 22 _{01 to} 22 ₀₄ : Number of rows of anodes 24 ₀₁ , 24 ₀₂ : Number of rows of auxiliary anodes 30: Write pulse generation circuit 32: Sustain pulse generation circuit 34: Scan pulse and erase pulse generation circuit 36: Resistor 38: Power supply

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiro Toyama 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd.

Claims (2)

[Claims] 1. Applying at least a sustaining pulse to the anode,
In order to temporarily reduce the erase voltage level of the erase pulse to the cathode pre-bias voltage when driving the pulse memory type gas discharge light emitting device by applying at least the scan pulse and the erase pulse immediately after the scan pulse to the cathode. The method for driving a gas discharge light-emitting device, wherein the cathode sustaining pulse is applied to the cathode during at least one sustaining pulse. 2. The method for driving a gas discharge light emitting device according to claim 1, wherein the cathode sustain pulse has a pulse width shorter than a sustain pulse width. .