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JPH0621360A - Epitaxial semiconductor substrate - Google Patents

Epitaxial semiconductor substrate

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Publication number
JPH0621360A
JPH0621360A JP20041192A JP20041192A JPH0621360A JP H0621360 A JPH0621360 A JP H0621360A JP 20041192 A JP20041192 A JP 20041192A JP 20041192 A JP20041192 A JP 20041192A JP H0621360 A JPH0621360 A JP H0621360A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
layer
epitaxial
region
film thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20041192A
Other languages
Japanese (ja)
Inventor
Tadahide Hoshi
忠秀 星
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP20041192A priority Critical patent/JPH0621360A/en
Publication of JPH0621360A publication Critical patent/JPH0621360A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To obtain an epitaxial semiconductor substrate which reduces fail rate of product characteristics by a construction wherein an epitaxial growth layer is formed immediately on a buried layer. CONSTITUTION:A silicon dioxide film is formed on a P-type substrate 30, and a prescribed burying region and a burying region 32 of a width 50mum are opened by patterning in an element forming region 31 and a region 33 to be a dicing line, respectively. Then, a coating diffusion agent containing antimony is applied by spin-coating, thereby a coating film of 250nm is formed and diffused only in the opened parts, so that an N<->buried layer 32 be formed, and the silicon dioxide layer and the coating film are wholly exfoliated by a fluoric acid. By introducing SiH, Cl, gas and PH gas, accordingly, an N-type epitaxial growth layer 34 is deposited by a cylinder-type epitaxial apparatus and thereby an epitaxial semiconductor substrate having a structure which reduces defectiveness of product characteristics and also can improve a throughput in an epitaxial growth process can be attained.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、エピタキシャル半導体
基板の構造に関するもので、特に高速性、低消費電力化
が必要とされるBiCMOS用のエピタキシャル半導体
基板に使用されるものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the structure of an epitaxial semiconductor substrate, and more particularly to an epitaxial semiconductor substrate for BiCMOS which requires high speed and low power consumption.

【0002】[0002]

【従来の技術】近年、ロジックやメモリ等の各種IC製
品は、従来用いられていたCMOS構造から、CMOS
構造にバイポーラ領域を取り入れたバイポーラCMOS
(BiCMOS)構造にすることにより高速化が図られ
ている。
2. Description of the Related Art In recent years, various IC products such as logic and memory have been changed from the conventional CMOS structure to the CMOS
Bipolar CMOS with bipolar structure incorporated in the structure
Higher speed is achieved by adopting a (BiCMOS) structure.

【0003】図5は従来のCMOS構造を有する半導体
装置の断面図である。周知のようにCMOS構造はN基
板1にPチャネルMOSFETを、またPウェル2にN
チャネルMOSFETを設けたものである。PMOSF
ETとNMOSFETは、素子分離用のシリコン酸化膜
3により、素子形成領域の表面周縁を取り囲まれる。ゲ
ート電極4は、ゲート酸化膜5を介して基板表面のチャ
ネル領域と対向し、いわゆるMOS構造を形成する。チ
ャネル領域を挟んで、PMOSFETの場合には、ソー
ス・ドレインとなるP+ 層6、またNMOSFETの場
合には、N+ 層7が設けられる。また符号8及び9はチ
ャネルストッパ層と呼ばれるN- 層及びP- 層である。
CMOSデバイスは、消費電力が極めて小さいという特
徴を持っているが、技術進歩により高集積化も可能とな
った。
FIG. 5 is a sectional view of a conventional semiconductor device having a CMOS structure. As is well known, the CMOS structure has a P channel MOSFET on the N substrate 1 and an N channel on the P well 2.
A channel MOSFET is provided. PMOSF
The ET and the NMOSFET are surrounded by the silicon oxide film 3 for element isolation, which surrounds the surface periphery of the element formation region. The gate electrode 4 faces the channel region on the substrate surface via the gate oxide film 5 and forms a so-called MOS structure. A P + layer 6 serving as a source / drain in the case of a PMOSFET and an N + layer 7 in the case of an NMOSFET are provided with the channel region sandwiched therebetween. The reference numeral 8 and 9 N is referred to as a channel stopper layer - a layer - layer and P.
The CMOS device has a characteristic that the power consumption is extremely low, but due to technological progress, high integration has become possible.

【0004】このようなCMOSデバイスの低消費電力
性、高集積性とバイポーラトランジスタの高駆動力、高
速性とを同一チップに共存させるBiCMOSデバイス
が開発され、応用が広がっいてる。
BiCMOS devices have been developed and are widely used in which the low power consumption and high integration of such CMOS devices and the high driving power and high speed of bipolar transistors coexist on the same chip.

【0005】図6は、BiCMOS構造を持つ半導体装
置の概略の構成を示す断面図である。領域50にはNP
Nバイポーラトランジスタ、領域51にはNチャネルM
OSFET、領域52にはPチャネルMOSFETがそ
れぞれ形成されている。なお図5と同じ符号は同一部分
または相当部分をあらわす。このBiCMOS構造を有
する半導体装置は、通常P基板10上の所定の領域に高
濃度N+ 埋め込み層11及びP埋め込み層12を形成し
た後、N型のエピタキシャル層13を成長させたエピタ
キシャル半導体基板を用いて、通常のCMOSプロセス
及びバイポーラプロセスを通して作成される。なお図6
において、符号14はP+ ベース層、15はP- ベース
層、16はN+ コレクタ引き出し層、17はNウェルを
あらわす。
FIG. 6 is a sectional view showing a schematic structure of a semiconductor device having a BiCMOS structure. NP in area 50
N bipolar transistor, N channel M in region 51
P-channel MOSFETs are formed in the OSFET and the region 52, respectively. Note that the same reference numerals as those in FIG. 5 represent the same or corresponding portions. A semiconductor device having this BiCMOS structure is usually an epitaxial semiconductor substrate in which a high concentration N + buried layer 11 and a P buried layer 12 are formed in a predetermined region on a P substrate 10 and then an N type epitaxial layer 13 is grown. Used to fabricate through conventional CMOS and bipolar processes. Note that FIG.
In the figure, reference numeral 14 represents a P + base layer, 15 a P base layer, 16 an N + collector extraction layer, and 17 an N well.

【0006】図7は、BiCMOS構造の半導体装置に
使用されるエピタキシャル半導体基板の一例を示す断面
図である。該基板は、P型基板24にN+ 埋め込み層2
1、23及びP埋め込み層22を形成した後、N型のエ
ピタキシャル成長層20を堆積したものである。
FIG. 7 is a sectional view showing an example of an epitaxial semiconductor substrate used for a semiconductor device having a BiCMOS structure. The substrate is a P-type substrate 24 and an N + buried layer 2
1 and 23 and the P buried layer 22 are formed, and then the N type epitaxial growth layer 20 is deposited.

【0007】従来技術において、図7に示すようなエピ
タキシャル半導体基板のN型エピタキシャル層20の膜
厚は、通常フーリエ変換型赤外分光計(FT−IR)を
用いて、高濃度N+ 埋め込み層上の膜厚を測定して得ら
れている。
In the prior art, the thickness of the N type epitaxial layer 20 of the epitaxial semiconductor substrate as shown in FIG. 7 is determined by using a Fourier transform infrared spectrometer (FT-IR) to obtain a high concentration N + buried layer. It is obtained by measuring the film thickness above.

【0008】前記FT−IR法による膜厚測定は、赤外
線を被測定エピタキシャル層に入射し、該層と光学的性
質の異なる高濃度N+ 埋め込み層で反射させ、反射して
エピタキシャル層から外方に戻される反射光の吸収スペ
クトルのデータを処理して行われる。このため、反射光
量が所定値以下の微少量になると測定できなくなる。例
えばSRAM等のようにバイポーラ領域が少ない、すな
わち高濃度N+ 埋め込み層が少ないデバイスに使用され
るエピタキシャル半導体基板の膜厚は測定できなかっ
た。
In the film thickness measurement by the FT-IR method, infrared rays are incident on the epitaxial layer to be measured, reflected by a high-concentration N + buried layer having a different optical property from the epitaxial layer, and reflected to the outside of the epitaxial layer. This is done by processing the data of the absorption spectrum of the reflected light returned to the. For this reason, measurement becomes impossible when the amount of reflected light becomes a very small amount below a predetermined value. For example, the film thickness of an epitaxial semiconductor substrate used in a device such as SRAM having a small number of bipolar regions, that is, a high concentration N + buried layer, cannot be measured.

【0009】したがって、高濃度N+ 埋め込み層が少な
い基板のエピタキシャル成長工程においては、高濃度N
+ 埋め込みが十分なされているテストピース(膜厚測定
用ウェーハ)を、製品に用いられる半導体基板と同時に
エピタキシャル成長させ、このテストピースの膜厚を測
定し、製品に使用されるエピタキシャル半導体基板の膜
厚の代表値としていた。このため、テストピースの膜厚
と製品に使用される基板の膜厚とが相異し、実際に製品
化されたときに、この膜厚が規格からはずれてしまい、
製品特性不良となってしまうことがあった。またエピタ
キシャル成長時に、必ずテストピースを導入しなければ
ならず、コストアップとなるほか、通常のエピタキシャ
ル成長工程において、例えば24枚同時に処理されるの
に対し、2枚のテストピースをいれればその分スループ
ットが悪くなるなどの問題があった。
Therefore, in the process of epitaxial growth of a substrate having a small amount of high-concentration N + buried layer, high-concentration N +
+ Epitaxially grow a test piece (wafer for film thickness measurement) with sufficient embedding at the same time as the semiconductor substrate used for the product, measure the film thickness of this test piece, and measure the film thickness of the epitaxial semiconductor substrate used for the product. Was used as a representative value. For this reason, the film thickness of the test piece and the film thickness of the substrate used for the product are different, and when it is actually commercialized, this film thickness deviates from the standard,
There were cases where product characteristics became defective. In addition, the test piece must be introduced at all times during the epitaxial growth, which increases the cost. In addition, in the normal epitaxial growth process, for example, 24 pieces are processed at the same time. There was a problem such as getting worse.

【0010】[0010]

【発明が解決しようとする課題】これまで述べたよう
に、BiCMOS構造の半導体装置などに使用されるエ
ピタキシャル半導体基板にあっては、エピタキシャル層
の膜厚の管理は非常に重要である。そのためエピタキシ
ャル成長のロットごとに膜厚を測定し、その結果に基づ
き次のロットのエピタキシャル成長条件を決めている。
従来は、FT−IR方法を用いて膜厚測定をしている
が、高濃度埋め込み層の少ないエピタキシャル半導体基
板に対しては、膜厚測定ができないという問題がある。
このため高濃度埋め込みが十分なされているテストピー
スを別に用意し、製品用基板と同時にエピタキシャル成
長させ、このテストピースの膜厚をそのロットの膜厚の
代表値として使用している。しかしこの代表値が製品用
基板の実際の膜厚と相関が薄く、製品の特性不良発生の
原因となることがしばしばあった。他方製品用基板とは
別にテストピースを作成するため、その分、エピタキシ
ャル成長工程におけるスループットが低下するという問
題がある。
As described above, in the epitaxial semiconductor substrate used for the semiconductor device having the BiCMOS structure, it is very important to control the thickness of the epitaxial layer. Therefore, the film thickness is measured for each lot of epitaxial growth, and the epitaxial growth condition of the next lot is determined based on the result.
Conventionally, the film thickness is measured using the FT-IR method, but there is a problem that the film thickness cannot be measured for an epitaxial semiconductor substrate having a small number of high-concentration buried layers.
For this reason, a test piece that is sufficiently filled with high concentration is prepared separately, and epitaxially grown at the same time as the product substrate, and the film thickness of this test piece is used as a representative value of the film thickness of the lot. However, this typical value has a small correlation with the actual film thickness of the product substrate, and often causes the occurrence of defective characteristics of the product. On the other hand, since the test piece is prepared separately from the product substrate, there is a problem that the throughput in the epitaxial growth process is reduced accordingly.

【0011】本発明は、上記従来技術の問題点に鑑みな
されたもので、製品に使用されるエピタキシャル半導体
基板の膜厚管理を改善し、製品特性の不良率を減少さ
せ、かつエピタキシャル成長工程におけるスループット
を向上させることのできる構造のエピタキシャル半導体
基板を提供することを目的とする。
The present invention has been made in view of the above-mentioned problems of the prior art. It improves the control of the film thickness of the epitaxial semiconductor substrate used in the product, reduces the defective rate of the product characteristics, and increases the throughput in the epitaxial growth process. It is an object of the present invention to provide an epitaxial semiconductor substrate having a structure capable of improving

【0012】[0012]

【課題を解決するための手段】本発明は、半導体基板上
にエピタキシャル成長層を堆積したエピタキシャル半導
体基板において、該エピタキシャル半導体基板の素子形
成領域外の領域に高不純物濃度の(約1018 atoms/cm3
以上)の埋め込み層を有し、該埋め込み層直上にエピタ
キシャル成長層が形成されていることを特徴とするエピ
タキシャル半導体基板である。
According to the present invention, in an epitaxial semiconductor substrate in which an epitaxial growth layer is deposited on a semiconductor substrate, a high impurity concentration (about 10 18 atoms / cm 3) is formed in a region outside the element formation region of the epitaxial semiconductor substrate. 3
The epitaxial semiconductor substrate has the buried layer described above) and the epitaxial growth layer is formed directly on the buried layer.

【0013】[0013]

【作用】本発明の特徴は、半導体基板上に堆積したエピ
タキシャル成長層の膜厚を測定できる大きさの高不純物
濃度の埋め込み層が、素子形成領域に存在しないエピタ
キシャル半導体基板において、あらかじめ素子形成領域
外の領域(たとえばダイシングラインとなる領域)に、
膜厚測定可能な大きさの高不純物濃度の埋め込み層を形
成した上で、エピタキシャル成長させてエピタキシャル
半導体基板を作製する。
The feature of the present invention is that, in the epitaxial semiconductor substrate in which the buried layer having a high impurity concentration of a size capable of measuring the film thickness of the epitaxial growth layer deposited on the semiconductor substrate does not exist in the element formation region, the buried layer is previously formed outside the element formation region. In the area (for example, the area that becomes the dicing line),
After forming a buried layer having a high impurity concentration of a size capable of measuring the film thickness, epitaxial growth is performed to manufacture an epitaxial semiconductor substrate.

【0014】これにより従来技術では、別に膜厚測定用
のテストピースを使用したのに対し、本発明では、製品
に使用される基板を使用し、その上に堆積される膜厚を
測定するので、容易にかつ正確にエピタキシャル半導体
基板の膜厚管理が可能となり、膜厚測定のため別にテス
トピースを作成しないのでスループットも向上する。
Thus, in the prior art, a test piece for film thickness measurement was separately used, whereas in the present invention, the substrate used for the product is used and the film thickness deposited thereon is measured. The film thickness of the epitaxial semiconductor substrate can be easily and accurately controlled, and the throughput is improved because a separate test piece is not prepared for measuring the film thickness.

【0015】なお、試行結果(後述)によれば、良好な
膜厚測定精度を得るためには、前記素子形成領域以外の
領域に設けられる埋め込み層の幅は、25μm 以上とする
必要がある。
According to the trial results (described later), the width of the burying layer provided in a region other than the element forming region must be 25 μm or more in order to obtain good film thickness measurement accuracy.

【0016】[0016]

【実施例】以下に本発明の実施例について、図面を参照
して説明する。図1は、本発明のエピタキシャル半導体
基板の平面図、図2は、該基板のダイシングラインとな
る領域の部分拡大図で、同図(a)は平面図、同図
(b)は同図(a)に示すXY線断面図である。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view of an epitaxial semiconductor substrate of the present invention, FIG. 2 is a partially enlarged view of a region serving as a dicing line of the substrate, FIG. 1A is a plan view, and FIG. It is the XY sectional view shown in a).

【0017】図1及び図2において、エピタキシャル半
導体基板は、直径 150mmのP型(100)基板(比抵抗
6Ωcm)30と素子形成領域31外のダイシングライン
となる領域33に形成されたN+ 埋め込み層32と、該
層32の直上を含むP型基板30上に堆積された約 2μ
m の膜厚の抵抗 0.5ΩcmのN型エピタキシャル成長層3
4とから構成されている。
In FIGS. 1 and 2, the epitaxial semiconductor substrate is a P-type (100) substrate (resistivity: 150 mm).
6 Ωcm) 30 and an N + buried layer 32 formed in a region 33 to be a dicing line outside the element formation region 31, and about 2 μ deposited on the P-type substrate 30 including immediately above the layer 32.
N type epitaxial growth layer 3 with m film thickness and resistance of 0.5Ωcm 3
4 and.

【0018】このエピタキシャル半導体基板の製造方法
は次のとおりである。P型基板30上に厚さ 800nmの二
酸化シリコン膜を形成し、素子形成領域31に図示して
ない所定の埋め込み領域と、ダイシングラインとなる領
域33に幅50μm の埋め込み領域32とをパターニング
し、開孔する。その後アンチモンを含有した塗布拡散剤
をスピンコートし、開孔部分にのみ 250nmの塗布膜を形
成し、1190℃にて約 1時間拡散させ、N+ 埋め込み層3
2を形成する。次に二酸化シリコン層及び塗布膜を弗酸
にて全剥する。次にシリンダー型エピタキシャル装置に
て、Si H2 Cl 2 ガス及びPH3 ガスを導入し、約 2
μm の膜厚のN型エピタキシャル成長層34を堆積し
て、図1に示すエピタキシャル半導体基板が得られる。
The method of manufacturing this epitaxial semiconductor substrate is as follows. A silicon dioxide film having a thickness of 800 nm is formed on the P-type substrate 30, and a predetermined buried region (not shown) in the element forming region 31 and a buried region 32 having a width of 50 μm are patterned in the region 33 to be a dicing line. Make a hole. Then antimony was spin-coated a coating diffusing agent containing, to form a coating film of 250nm only opening portion, it is about 1 hour diffusion at 1190 ° C., N + buried layer 3
Form 2. Next, the silicon dioxide layer and the coating film are completely stripped with hydrofluoric acid. Next, Si H 2 Cl 2 gas and PH 3 gas were introduced by a cylinder type epitaxial device, and about 2
An N-type epitaxial growth layer 34 having a thickness of μm is deposited to obtain the epitaxial semiconductor substrate shown in FIG.

【0019】次にエピタキシャル半導体基板について、
上記実施例の基板と従来例の基板との比較を行なった。
従来例の試料として、素子形成領域内の所定の埋め込み
領域にのみN+ 埋め込みを行なったウェーハ12枚と、全
面にN+ 埋め込み層を形成したテストピース用基板 2枚
とを 1ロットとし、 5ロット製作した。実施例の試料
は、12枚を 1ロットとし、 5ロット合計60枚を準備し
た。なおシリンダー型エピタキシャル装置に同時に装着
され、処理されるウェーハを 1ロットとする。
Next, regarding the epitaxial semiconductor substrate,
The substrate of the above-mentioned example and the substrate of the conventional example were compared.
As a sample of the conventional example, 12 wafers in which N + burying was performed only in a predetermined burying region in the element formation region and 2 test piece substrates in which an N + burying layer was formed on the entire surface were set as one lot. Lot made. For the samples of the examples, 12 sheets were treated as one lot, and 60 sheets were prepared in total for 5 lots. Wafers that are simultaneously mounted and processed in a cylinder-type epitaxial device are treated as one lot.

【0020】従来例の場合には、 1ロットのエピタキシ
ャル成長を終了ごとに、該ロットの2枚のテストピース
の膜厚を測定し、次のロットの成長条件を決定した。
In the case of the conventional example, the film thickness of two test pieces of each lot was measured every time the epitaxial growth of one lot was completed, and the growth conditions of the next lot were determined.

【0021】本発明の場合には、製品に使用される12
枚のウエーハのダイシングライン上の埋め込み層にて膜
厚を測定し、つぎのロットの成長条件を決定した。
In the case of the present invention, 12 used in products
The film thickness was measured in the buried layer on the dicing line of each wafer, and the growth conditions of the next lot were determined.

【0022】このようにして製作されたエピタキシャル
ル半導体基板を製品プロセスへ投入し、特性試験を行っ
た。その結果を図3に示す。同図において、横軸は従来
例及び本発明実施例のそれぞれの区分を示し、縦軸は製
品歩留まりを示す。テストピースにて膜厚管理を行なっ
た従来例では製品歩留まりが50%であったのに対し、本
実施例のようにダイシングラインとなる領域に埋め込み
層を導入し、膜厚管理した場合は80%と歩留まりが向上
した。
The epitaxial semiconductor substrate thus manufactured was put into a product process and a characteristic test was conducted. The result is shown in FIG. In the figure, the abscissa indicates each of the conventional example and the embodiment of the present invention, and the ordinate indicates the product yield. The product yield was 50% in the conventional example in which the film thickness was controlled by the test piece, whereas it was 80% when the film thickness was controlled by introducing the embedded layer in the region to be the dicing line as in this example. % And the yield improved.

【0023】図4は、膜厚分布と製品特性の相関図であ
る。横軸は膜厚で、縦軸は製品の特性値を示す。同図中
の○印は従来例の、また△印は前記実施例のそれぞれの
基板を使用したとき、膜厚とその膜厚の製品特性とを示
す。膜厚が悪く、規格値から外れると、その製品特性が
悪化していることを示しており、図3に示す結果を示唆
している。
FIG. 4 is a correlation diagram between film thickness distribution and product characteristics. The horizontal axis represents the film thickness, and the vertical axis represents the characteristic value of the product. In the figure, the mark ◯ shows the film thickness and the product characteristics of the film thickness when the respective substrates of the conventional example and the above-mentioned example are used. When the film thickness is bad and deviates from the standard value, the product characteristics are deteriorated, and the results shown in FIG. 3 are suggested.

【0024】次にダイシングラインとなる領域に形成さ
れる埋め込み層の幅が、それぞれ15μm 、25μm 及び50
μm となるエピタキシャル半導体基板を、前記実施例と
同様の方法で、複数枚製作し、各ウェーハの同一箇所を
10回ずつ測定したところ、その結果のバラツキは、それ
ぞれ± 2.5%、± 0.8%、± 0.6%となった。すなわち
埋め込み層の幅が25μm 近傍の臨界値をこえると、バラ
ツキが急激に減少し、さらに埋め込み層の幅が増加する
とバラツキは飽和する傾向を示す。この結果、良好な膜
厚精度を得るためには、幅を25μm 以上とする必要があ
る。
Next, the widths of the buried layers formed in the regions to be the dicing lines are 15 μm, 25 μm and 50, respectively.
A plurality of epitaxial semiconductor substrates with a size of μm were manufactured in the same manner as in the above-mentioned embodiment, and the same position on each wafer was manufactured.
When the measurement was performed 10 times, the variations in the results were ± 2.5%, ± 0.8%, and ± 0.6%, respectively. That is, when the width of the buried layer exceeds the critical value near 25 μm, the variation sharply decreases, and when the width of the buried layer increases, the variation tends to be saturated. As a result, in order to obtain good film thickness accuracy, the width needs to be 25 μm or more.

【0025】本実施例ではダイシングラインとなる領域
にすべて埋め込み領域を形成したがこれに限定されな
い。膜厚管理が可能であれば良く、25μm ×25μm 以上
の領域が少なくとも素子形成領域外の領域に一箇所以上
入っておれば良い。
In this embodiment, the buried region is formed in all the regions to be the dicing line, but the present invention is not limited to this. It suffices that the film thickness can be controlled, and it is sufficient that at least one region having a size of 25 μm × 25 μm or more is provided outside the element formation region.

【0026】[0026]

【発明の効果】本発明においては、製品となるエピタキ
シャル半導体基板の、例えばダイシングラインとなる領
域のように素子形成領域外の領域に、あらかじめ膜厚測
定可能な大きさの高不純物濃度の埋め込み層を形成した
上で、エピタキシャル成長させてエピタキシャル半導体
基板を作製するので、従来技術の課題は解決される。本
発明により、製品に使用されるエピタキシャル半導体基
板の膜厚管理が改善され、製品特性の不良率を低下させ
ると共にエピタキシャル成長工程におけるスループット
を向上させることのできる構造のエピタキシャル半導体
基板を提供することができた。
According to the present invention, a buried layer having a high impurity concentration and having a size capable of preliminarily measuring a film thickness is formed in a region outside an element forming region such as a region serving as a dicing line of an epitaxial semiconductor substrate to be manufactured. Since the epitaxial semiconductor substrate is manufactured by forming the film and forming the epitaxial semiconductor substrate, the problems of the prior art can be solved. According to the present invention, it is possible to provide an epitaxial semiconductor substrate having a structure capable of improving the film thickness management of the epitaxial semiconductor substrate used for the product, reducing the defective rate of the product characteristics, and improving the throughput in the epitaxial growth process. It was

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明のエピタキシャル半導体基板の平面図で
ある。
FIG. 1 is a plan view of an epitaxial semiconductor substrate of the present invention.

【図2】同図(a)は図1に示す基板のダイシングライ
ンとなる部分の拡大平面図、同図(b)は断面図であ
る。
2 (a) is an enlarged plan view of a portion which becomes a dicing line of the substrate shown in FIG. 1, and FIG. 2 (b) is a sectional view.

【図3】従来例及び本発明の実施例に係るエピタキシャ
ル半導体基板を使用した製品の歩留まりの比較図であ
る。
FIG. 3 is a comparison diagram of yields of products using the conventional example and the epitaxial semiconductor substrate according to the example of the present invention.

【図4】膜厚分布と製品特性値の相関を示す図である。FIG. 4 is a diagram showing a correlation between film thickness distribution and product characteristic values.

【図5】CMOS構造を有する半導体装置の断面図であ
る。
FIG. 5 is a cross-sectional view of a semiconductor device having a CMOS structure.

【図6】BiCMOS構造を有する半導体装置の断面図
である。
FIG. 6 is a sectional view of a semiconductor device having a BiCMOS structure.

【図7】エピタキシャル半導体基板の一例を示す断面図
である。
FIG. 7 is a cross-sectional view showing an example of an epitaxial semiconductor substrate.

【符号の説明】[Explanation of symbols]

30 半導体基板(P型基板) 31 素子形成領域 32 高不純物濃度の埋め込み層(N+ 埋め込み層) 33 素子形成領域外の領域(ダイシングラインとな
る領域) 34 エピタキシャル成長層
30 Semiconductor Substrate (P-type Substrate) 31 Element Forming Area 32 High Impurity Concentration Embedding Layer (N + Embedding Layer) 33 Area Outside Element Forming Area (Dicing Line Area) 34 Epitaxial Growth Layer

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】半導体基板上にエピタキシャル成長層を堆
積したエピタキシャル半導体基板において、該エピタキ
シャル半導体基板の素子形成領域外の領域に高不純物濃
度の埋め込み層を有し、該埋め込み層直上にエピタキシ
ャル成長層が形成されていることを特徴とするエピタキ
シャル半導体基板。
1. An epitaxial semiconductor substrate having an epitaxial growth layer deposited on a semiconductor substrate, which has a buried layer having a high impurity concentration in a region outside an element forming region of the epitaxial semiconductor substrate, and the epitaxial growth layer is formed directly on the buried layer. An epitaxial semiconductor substrate characterized in that
JP20041192A 1992-07-03 1992-07-03 Epitaxial semiconductor substrate Pending JPH0621360A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20041192A JPH0621360A (en) 1992-07-03 1992-07-03 Epitaxial semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20041192A JPH0621360A (en) 1992-07-03 1992-07-03 Epitaxial semiconductor substrate

Publications (1)

Publication Number Publication Date
JPH0621360A true JPH0621360A (en) 1994-01-28

Family

ID=16423874

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20041192A Pending JPH0621360A (en) 1992-07-03 1992-07-03 Epitaxial semiconductor substrate

Country Status (1)

Country Link
JP (1) JPH0621360A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5691585A (en) * 1995-03-28 1997-11-25 Mitsuba Electric Manufacturing Co., Ltd. Terminal connection for an electric motor with a speed reducer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5691585A (en) * 1995-03-28 1997-11-25 Mitsuba Electric Manufacturing Co., Ltd. Terminal connection for an electric motor with a speed reducer

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