JPH06209485A - Signal processing unit - Google Patents

Abstract

PURPOSE:To detect accurately a color frame with a simple configuration by comparing time data at two or more optional positions of a horizontal synchronizing signal and time data of a burst signal so as to detect a phase of the synchronizing signal. CONSTITUTION:A synchronizing signal extract means 2 extracts a synchronizing signal from a digital video signal and inputs a signal obtained by sampling two synchronizing signals and burst signals or over to a horizontal synchronizing signal phase detector 3 and a color burst phase detector 4 respectively. Then each address conversion means converts the signal into address data and position information at an optional point of a digital video signal stored in advance in a storage means is compared with position information of the synchronizing signal and the burst signal at a comparator means 5 based on the synchronizing signal extracted from the video signal. Thus, the SCH phase of the digital and analog composite video signals is detected with a simple configuration and a color frame is accurately detected to obtain a high quality picture without color slurring.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing apparatus suitable for application to, for example, equipment handling composite digital video signals.

[0002]

2. Description of the Related Art Conventionally, some devices that handle composite digital video signals, such as digital VTRs, include an A / D converter for converting an analog video signal into a composite digital video signal.

When converting an analog video signal into a composite digital video signal (sampling frequency is 4 fsc; fsc is frequency of color burst signal), SCH is used.
It is necessary to detect the phase, that is, the phase relationship between the subcarrier (SC) and the horizontal synchronization signal (H). Where SCH
Explaining the phase further, the SCH phase is the phase of the burst signal with reference to the falling 50% of the horizontal synchronizing signal waveform on a certain line. Color frame information is detected from the composite digital video signal based on the SCH phase.

This is because, in the case of decoding a color image by burst, in the NTSC system, it is necessary to decode as it is or to invert and decode, and the SCH phase output is used for the judgment at that time. Therefore,
If the SCH phase is not detected, the color frame information cannot be detected.

Conventionally, as a method of detecting the SCH phase, for example, slice processing is performed on the sync pattern of the analog composite video signal to obtain a time of 50% (level 1/2) of the fall, while the position of the burst ( For example, there is a method of detecting a so-called SCH in which a capacitor is charged for a time up to zero crossing) and the voltage is taken out to measure time.

As a result, even if the SCH of the input analog composite video signal is deviated, an erroneous color frame will not be detected.

[0007]

By the way, in the conventional digital VTR or the like, the SCH phase of the analog composite video signal is detected in an analog manner as described above, but the SCH of the composite digital video signal is detected. Since the phase detection is not performed, if the SCH of the composite digital video signal is out of phase, an incorrect color frame is detected or the system itself does not operate, and thus such a signal is accepted. There was an inconvenience that it was not possible.

Further, as to the analog composite video signal, since the SCH phase is detected in an analog manner as described above, the influence of the DC component fluctuation and the level fluctuation of the burst signal and the superimposed noise is caused. The detection accuracy is affected as it is, and variations in the characteristics of the components that make up the circuit, incorrect color frames are detected due to characteristic changes due to temperature, and the system itself does not operate, and it is not possible to accept signals. There was the inconvenience that the circuit had to be adjusted.

Further, if the color frame is not detected accurately, not only the image quality deterioration such as color shift but also the editing point cannot be grasped at the time of editing, so that accurate editing cannot be performed. In order to perform accurate editing, signal processing must be performed so that color frames are continuous, which is very troublesome.

The present invention has been made in view of the above points, and the SCH phase of a composite digital video signal and an analog composite video signal can be detected with a simple structure, and color misregistration can be achieved by accurately detecting a color frame. The present invention intends to propose a signal processing device capable of obtaining an excellent image quality without any error and performing accurate editing.

[0011]

According to the present invention, a temporal position of an arbitrary point of an input signal is obtained by using at least two data of sampling points near the arbitrary point.

Further, in the above-mentioned invention, the input signal is a synchronizing signal.

Further, in the above-mentioned invention, the input signal is a burst signal.

The present invention further comprises a sync signal extracting means 2 for extracting a sync signal from a digital video signal, and an address converting means 11 for converting data obtained by sampling the sync signal and burst signal of the digital video signal into address data. , 12, 13, 21, 22, 23 and the address data from the address conversion means 11, 12, 13, 21, 22, 23, the position information of an arbitrary point of the digital video signal stored in advance. Outputting means 16 and 26 for outputting the position information from the storing means 14 and 24, and synchronizing signals from the outputting means 16 and 26, based on the outputting means 16 and 24 and the synchronizing signal from the synchronizing signal extracting means 2. And a comparison means 5 for comparing the position information of the burst signals.

[0015]

According to the configuration of the present invention described above, the temporal position of an arbitrary point of the input signal is obtained by using at least two or more data of sampling points near the arbitrary point.

Further in the above, according to the configuration of the present invention,
The temporal position of an arbitrary point of the synchronization signal is obtained by using at least two or more sampling point data near the arbitrary point.

Further in the above, according to the configuration of the present invention,
The temporal position of an arbitrary point of the burst signal is obtained by using at least two or more sampling point data near the arbitrary point.

According to the structure of the present invention, the sync signal extraction means 2 extracts the sync signal from the digital video signal, and the data obtained by sampling the sync signal and the burst signal of the digital video signal are converted into the address conversion means 11, 12,
It is converted into address data at 13, 21, 22, and 23, and based on this data, the position information of any point of the digital video signal stored in advance is stored in the storage means 14, 24.
And outputs the position information from the storage means 14 and 24 on the basis of the synchronization signal from the synchronization signal extraction means 2.
6 and 26, and the comparison means 5 compares the position information of the synchronization signal and the burst signal from the output means 16 and 26.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the signal processing apparatus of the present invention will be described in detail below with reference to FIG.

In FIG. 1, reference numeral 1 denotes an input terminal to which a composite digital video signal including a sync signal and a burst signal is supplied. The composite digital video signal from the input terminal 1 is a sync separation / timing generation circuit 2 and a horizontal It is supplied to the synchronous phase detecting circuit 3 and the color burst phase detecting circuit 4, respectively.

The sync separation / timing generation circuit 2 separates a composite digital video signal supplied from another device (not shown), a circuit or the like via the input terminal 1 to obtain a sync signal, and based on this sync signal, a horizontal signal is generated. A synchronization timing signal and a burst timing signal are obtained, the horizontal synchronization timing signal is supplied to the horizontal synchronization phase detection circuit 3, and
The burst timing signal is supplied to the color burst phase detection circuit 4.

The horizontal sync phase detection circuit 3 will now be described with reference to FIG. 2. As shown in FIG. 2, the horizontal sync phase detection circuit 3 has an input terminal to which a composite digital video signal including a sync signal is supplied. 10 is connected to the address input terminal of the memory 14 and the input terminal of the delay circuit 11, respectively, and the output terminal of the delay circuit 11 is connected to the address input terminal of the memory 14 and the input terminal of the delay circuit 12, and the delay circuit 12 is connected.
Is connected to the address input terminal of the memory 14 and the input terminal of the delay circuit 13, the output terminal of the delay circuit 13 is connected to the address input terminal of the memory 14, and the output terminal of the memory 14 is connected to the flip-flop circuit 16. The input terminal 15 connected to the data input terminal D and supplied with the horizontal synchronizing timing signal from the horizontal synchronizing signal 3 shown in FIG. 1 is connected to the enable terminal EN of the flip-flop circuit 16, Non-inverting output terminal Q is output terminal 1
Configured by connecting to 7.

That is, in the horizontal sync phase detection circuit 3, the composite digital video signal supplied through the input terminal 10 is sequentially delayed by the delay circuits 11, 12 and 13 to obtain data at each sample point. ,
The data of these sample points is inputted to the memory 14 as an address signal, and the time data at the position of the corresponding falling 50% which is stored in advance in the memory 14 in the look-up table format is outputted.

This time data is supplied to the flip-flop circuit 16, and the time data is output in this flip-flop circuit 16 while the horizontal synchronization timing signal supplied via the input terminal 15 is active. It This horizontal synchronization timing signal is a 1-bit signal that is active (for example, high level "1") only during the period corresponding to the falling period of the horizontal synchronization signal. Since its position is known in advance, it is stored in the ROM or the like. There is something. For example, in the D2 format, the number of sample points is determined to be 4 at the falling edge of the horizontal synchronizing signal, and the code for that point is also determined.

The time at the position where the horizontal sync signal falls 50% (half the position from the sync tip to the pedestal level) shifts due to the horizontal, vertical, and tilt shifts of the horizontal sync signal. For example, in the digital VTR of the D2 system, the sampling points are 4 points during the falling edge of the horizontal synchronizing signal, and as described above, the data of the sampling points of the composite digital video signal are obtained and the data are addressed. Of the time data output from the memory 14 as
The time data when the horizontal sync timing signal indicating the fall of the horizontal sync signal becomes active is the time at the position of 50% of the fall.

Next, the color burst phase detection circuit 4 will be described with reference to FIG. 3. As shown in FIG. 3, the color burst phase detection circuit 4 has an input terminal to which a composite digital video signal including a burst signal is supplied. 20
Are connected to the address input terminal of the memory 24 and the input terminal of the delay circuit 21, respectively, and the output terminal of the delay circuit 21 is connected to the memory 24.
Address input terminal and the input terminal of the delay circuit 22, and the output terminal of the delay circuit 22 is connected to the address input terminal of the memory 24 and the input terminal of the delay circuit 23.
Is connected to the address input terminal of the memory 24, the output terminal of the memory 24 is connected to the data input terminal D of the flip-flop circuit 26, and the burst timing from the color burst phase detection circuit 4 shown in FIG. The supplied input terminal 25 is connected to the enable terminal EN of the flip-flop circuit 26, and the non-inverting output terminal Q of the flip-flop circuit 26 is connected to the output terminal 27.

That is, in the detection circuit 4, the composite digital video signal supplied through the input terminal 20 is sequentially delayed by the delay circuits 21, 22 and 23 to obtain the data at each sample point, and the sample points are sampled. The point data is input to the memory 24 as an address signal, and the time data (burst phase information) corresponding to the digital sample value of the corresponding color burst stored in advance in the memory 24 in the look-up table format is output.

This time data is supplied to the flip-flop circuit 26, and in the flip-flop circuit 26, the time data is output while the burst timing signal supplied via the input terminal 25 is active. . This burst timing signal is a 1-bit signal that becomes active (for example, high level "1") only during a period corresponding to one cycle of the color burst signal. Since its position is known in advance, it is stored in ROM or the like. is there.

Now, returning to FIG. 1, the operation of the signal processing apparatus of this embodiment will be described with reference to FIGS. 4 and 5.

As described above, the horizontal sync phase detection circuit 3
Then, the pre-stored time data is obtained by using the data of the sample point of the composite digital video signal including the sync signal from the sync separation / timing generation circuit 2 as an address, and the horizontal sync signal (see FIG.
(See FIG. 4A) Falling period t1 (see FIG. 4A).
It is obtained by the horizontal synchronization timing signal (see FIG. 4C) from the timing generation circuit 2.

The data at the sample point in the period before the falling period t1 of the horizontal synchronizing signal shown in FIG. 4A is made invalid data indicated by d1 in FIG. 4B by the horizontal synchronizing timing signal shown in FIG. The data at the sample points during the signal falling period t1 is shown in FIG.
The horizontal synchronization timing signal shown in FIG. 4C makes it valid data (a period corresponding to one system clock) indicated by d2 in FIG. 4B, and the sample point data in the period after the falling period t1 of the horizontal synchronization signal is shown in FIG. 4B, invalid data indicated by d3 in FIG. 4B is obtained.

That is, of the time data output from the memory 14 shown in FIG. 2, only the time data indicated by d2 in FIG. 4B is output by phase detection output as shown in FIG. 4D by the horizontal synchronization timing signal shown in FIG. 4C. It is output as df from the flip-flop circuit 16 (from the horizontal synchronization phase detection circuit 3 in FIG. 1).

On the other hand, in the color burst phase detection circuit 4, the burst point stored in advance is used as the address of the sample point data of the composite digital video signal including the burst signal (see FIG. 5A) from the sync separation / timing generation circuit 2. Of the color burst signal is obtained by the burst timing signal from the sync separation / timing generation circuit 2 (see FIG. 5C).

The data of the sample points in the period before the period t10 of one cycle of the burst signal shown in FIG. 5A is shown in FIG.
By the burst timing signal shown in C, invalid data indicated by d10 in FIG.
The data of the sample points in the period t20 of the cycle are shown in FIG. 5C.
5B by the burst timing signal shown in FIG. 5B as the valid data, and the data of the sampling point in the period after the period t10 of one cycle of the burst signal is d30 in FIG. 5B by the burst timing signal shown in FIG. 5C. Invalid data indicated by.

That is, of the time data output from the memory 24 shown in FIG. 3, only the time data indicated by d20 in FIG. 5B is the phase detection output df2 as shown in FIG. 5D by the burst timing signal shown in FIG. 5C. Is output from the flip-flop circuit 26 (from the color burst phase detection circuit 4 in FIG. 1).

Then, the falling edge 50 of the falling edge of the horizontal synchronizing signal from the horizontal synchronizing phase detecting circuit 3
The horizontal synchronization color burst phase comparison circuit 5 compares the time data at the percentage position with the time data of the period of the burst signal from the color burst phase detection circuit 4, and as a result of the comparison, a sync pattern (horizontal synchronization signal).
If the phase relationship of the burst based on the falling edge of is correct, for example, "0" is output, and if the phase relationship is not correct, values such as "+1" and "-1" are output. As a calculation for comparison, for example, subtraction is adopted.

Therefore, in various devices for processing a composite digital video signal such as a VTR in which the circuit shown in FIG. 1 is mounted, an accurate color is detected based on the detection output from the horizontal sync color burst phase comparison circuit 5. The frames can be detected and good signal processing can be performed, whereby the editing point can be grasped in editing and the like, and further, it is not necessary to perform extraordinary processing to make the frames continuous.

Further, in a device such as a digital VTR that receives an analog composite signal together with a digital composite video signal, there are many cases in which the SCH is detected only for the analog input signal. in this case,
Since the SCH is detected by the circuit that operates in an analog manner, the DC component fluctuation and level fluctuation of the burst signal,
The influence of the superimposed noise directly affects the detection accuracy,
It is unavoidable that the characteristics of the components that make up the circuit vary, the characteristics change due to temperature, and the adjustment of the circuit. However, when the signal processing device of this example is used, the analog signal is
Since the SCH phase can be detected after the conversion by the D converter, the conventional analog SCH phase detection becomes unnecessary and all the problems of the conventional SCH phase detection can be solved.

As described above, in this example, the time data at the position of 50% of the falling edge corresponding to the data of the sampling point of the falling edge of the horizontal synchronizing signal is obtained, and the data of the sample point of one cycle of the burst is obtained. Since the corresponding time data is obtained, these two time data are compared as phase information and the comparison result is output, the SCH phase of the composite digital video signal and the analog composite video signal can be detected with a simple configuration. At the same time, by accurately detecting the color frame, it is possible to obtain a good image quality without color shift and perform accurate editing.

When applying the above-mentioned signal processing device,
It is not necessary to input all the bits of the composite digital video signal into the memory, but the more bits are used, the higher the detection accuracy becomes.

As for the number of data samples to be input to the memory, phase detection is possible if at least two samples are used, but if more data is used as input to the memory, the influence of noise or the like can be easily eliminated. However, since the hardware scale (memory capacity) also increases in proportion to the number of bits / samples used, it is necessary to determine the number of samples and the number of bits to be input to the memory in consideration of the required detection accuracy. Become.

Further, in the above description, the horizontal synchronizing phase detecting circuit 3 and the color burst phase detecting circuit 4 are respectively provided with the delay circuits 11, 12, and 13, the memory 14, the flip-flop circuit 16, and the delay circuits 21, 22, 23, and the memory. Two
4. Although the example in which each of the flip-flop circuits 26 is configured has been described, the above-described processing can be performed by a program using a microcomputer including, for example, a CPU, a ROM, and a RAM. In this case, for example, if the video signal is the NTSC system, it can be realized if the clock frequency of the CPU is 14 MHz or higher. Also, SECAM
Also in the PAL system and the PAL system, it can be realized if the frequency is equal to or higher than four times the subcarrier frequency.

The above-described embodiment is an example of the present invention, and it goes without saying that various other configurations can be adopted without departing from the gist of the present invention.

[0044]

According to the present invention described above, the time position of an arbitrary point of the input signal is obtained by using at least two or more sampling point data in the vicinity of this arbitrary point. The time position information of the point can be easily and accurately obtained.

Further, according to the present invention described above, the time position of an arbitrary point of the synchronization signal and the data of sampling points near the arbitrary point are at least two.
In addition to the above effects,
It is possible to easily and accurately obtain information on the temporal position of an arbitrary point of the sync signal of the composite digital video signal and the analog composite video signal.

Further, according to the present invention described above, the temporal position of an arbitrary point of the burst signal is obtained by using at least two or more data of sampling points near the arbitrary point. In addition, it is possible to easily and accurately obtain information on the temporal position of an arbitrary point of the burst signal of the composite digital video signal and the analog composite video signal.

According to the present invention, the synchronizing signal extracting means extracts the synchronizing signal from the digital video signal, and the data obtained by sampling the synchronizing signal and the burst signal of the digital video signal is converted into the address data by the address converting means. Then, based on this data, the position information of any point of the digital video signal stored in advance is output by the storage means, and based on the synchronization signal from the synchronization signal extraction means, the position information output means from the storage means. Since the position information of the synchronizing signal and the burst signal from the output means is compared by the comparing means, the SCH phase of the composite digital video signal and the analog composite video signal can be detected with a simple configuration. By accurately detecting the color frame, good image quality without color shift can be obtained,
You can make accurate edits.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a signal processing device of the present invention.

FIG. 2 is a configuration diagram showing a main part of an embodiment of a signal processing device of the present invention.

FIG. 3 is a configuration diagram showing a main part of an embodiment of a signal processing device of the present invention.

FIG. 4 is a timing chart for explaining an embodiment of the signal processing device of the present invention.

FIG. 5 is a timing chart for explaining an embodiment of the signal processing device of the present invention.

[Explanation of symbols]

 2 sync separation / timing generation circuit 3 horizontal sync position detection circuit 4 color burst phase detection circuit 5 horizontal sync color burst phase comparison circuit 11, 12, 13, 21, 22 and 23 delay circuit 14, 24 memory 16, 26 flip-flop circuit

Claims (4)

[Claims] 1. A signal processing device, characterized in that the temporal position of an arbitrary point of an input signal is obtained by using at least two or more data of sampling points near the arbitrary point. 2. The signal processing device according to claim 1, wherein the input signal is a synchronization signal. 3. The signal processing device according to claim 1, wherein the input signal is a burst signal. 4. A sync signal extracting means for extracting a sync signal from a digital video signal, an address converting means for converting data obtained by sampling a sync signal and a burst signal of the digital video signal into address data, and the above address conversion. Based on the address data from the means,
Storage means for outputting position information of an arbitrary point of the digital video signal stored in advance; output means for outputting position information from the output means based on a synchronization signal from the synchronization signal extraction means; A signal processing apparatus comprising: a comparison unit that compares the position information of the synchronization signal and the burst signal from the output unit.