JPH0619720B2 - Information processing equipment - Google Patents

Description

The present invention relates to an information processing apparatus, and more particularly, to a specific event occurring in a software use area of a main storage device in a hardware system area under a multiprocessor environment. The present invention relates to an information processing apparatus that adopts a method of simulating by executing a pre-stored instruction sequence.

[Conventional technology]

The instruction execution method in the information processing apparatus is generally realized by executing a microprogram stored in a fixed hardware logic circuit or a control memory in the central processing unit. By the way, there are many kinds of instructions, and if such an instruction is executed by a fixed hardware logic circuit or a microprogram, the logic circuit becomes very complicated and the capacity of the control memory is increased due to the increase of the microprogram. It will be huge. As a method of solving this, for example, in Japanese Patent Publication No. 59-9937, the main storage device is divided into a software area of a hardware area, and a program that can be seen from an operating system is stored in the software area. The hardware area stores an instruction execution procedure for processing a specific compound instruction or an instruction execution procedure for processing that should be performed when a specific event occurs, and a specific compound instruction or a specific event is detected. When
A technique for executing an instruction execution procedure in the hardware area by an interrupt is shown.

[Problems to be solved by the invention]

According to the above-mentioned conventional technique, it is possible to easily execute an instruction that requires complicated and diversified processing or an instruction that is rarely used, without increasing the complexity of the logic circuit and increasing the microprogram. However, in this conventional technique, interrupts other than hardware machine check interrupts and program interrupts are prohibited during execution of the instruction execution procedure in the hardware area, and a multiprocessor environment requiring a highly flexible interrupt processing method is also required. The use below is not considered.

An object of the present invention is to eliminate the above-mentioned problems of the prior art and to efficiently simulate an event occurring in a software use area by an instruction execution procedure in a hardware system area under a multiprocessor environment. An object of the present invention is to provide an information processing device that has an interrupt processing method with a high degree of freedom and has improved reliability.

[Means for solving problems]

According to the present invention, a plurality of central processing units share a main storage device, and the main storage device is divided into a software use area used by normal software and a hardware system area used by hardware. In the information processing device having the function of executing the instruction execution procedure stored in advance in the hardware system area due to the event that occurs in the above, a function of accepting all interrupts during the processing of the instruction execution procedure in the hardware system area,
For unexpected interrupts, a function is provided to perform fault processing as a hardware malfunction.

[Work]

According to the present invention, in an information processing apparatus having a multiprocessor configuration, an event occurring in a software use area is efficiently linked to an instruction execution procedure stored in advance in a hardware system area to process the event. ,
By utilizing the free time of the hardware, it is possible to execute a program that tests the operation of the hardware logic, and free interruption is possible. Further, by performing failure processing as an erroneous operation of hardware for an unexpected interrupt, it is possible to improve reliability against an error due to erroneous operation of hardware or an instruction execution procedure.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a schematic block diagram of an embodiment of an information processing apparatus according to the present invention. In FIG. 1, a plurality of central processing units 10 share a main storage device 20. Main memory 20
Is divided into a software use area 21 (hereinafter abbreviated as SUA) in which a normal software program is stored and a hardware system area 22 (hereinafter abbreviated as HSA). Further, in the HSA, an area 30 (hereinafter, abbreviated as MCA) in which an instruction execution procedure (hereinafter, this instruction string is referred to as a macro code) is stored, a link information of the microprogram and the macrocode, and an area 40 for working the macrocode. (Hereinafter abbreviated as MPA). The MCA 30 exists in units of events that occur in the SUA, and stores instruction execution procedures that can be simultaneously executed by a plurality of instruction processing devices 10. The start addresses of the MCA 30 are stored in the HSA at the time of system startup and are stored in advance in the HSA. It is stored in a specific register (not shown) in the central processing unit. The MPA 40 is installed in each central processing unit, and its head address is based on the number of each central processing unit and is set in the register 11 in each processing unit.
It is stored in.

When a specific event is detected in SUA21, HSA2
The macro code stored in the MCA corresponding to the event in 2 is executed. At that time, the MPA peculiar to each central processing unit is used as a work area when the linkage of the microprogram and the macrocode and the macrocode is executed.
During execution of the macro code, the flip-flop 12 provided in each central processing unit (hereinafter, this flip-flop is referred to as macro mode) is set to "1".

FIG. 2 shows a table for interrupt processing in the MPA for one central processing unit, 43 to 44 are defined areas in the MPA, 43 is various interrupt control flags,
44 is a new PSW group for each interrupt.

FIG. 3 is a diagram showing a flow of interrupt processing. The process flow of FIG. 3 will be described below with reference to the table of FIG.

Corresponding to each central processing unit 10, a 1-bit interrupt control flag 43 is provided at a specific address in the corresponding MPA in the main storage device 20 for each type of interrupt. These interrupt control flags 43 are set to "0" when linking to the macro code of MCA. If the macro code assumes the occurrence of some kind of interrupt (process 20
1), the new PSW for the interrupt is stored in the specific address 44 in the MPA (process 202), and the interrupt control flag 43
The bit corresponding to the interrupt of is set to "1" (process 203). The control bit for an interrupt that is not expected to occur remains "0". During execution of the macro code (process 203), the flip-flop 12 in the central processing unit 10 is set to "1".

When an interrupt occurs, in the central processing unit 10, the microprogram for each interrupt process is started. However, in each interrupt routine, the macro mode is "1" (the flip-flop 12 is "1") Then, the interrupt control flag 43 in the MPA is read, and it is tested whether the bit for that interrupt is "0" or "1" (process 102). If the control flag is "1", the current PSW
Is stored as an old PSW in a specific address (not shown) in the MPA, the new PSW 44 stored in the MPA is read to be the current PSW, and the macro code is linked again (processes 103 and 105). When the control flag is "0", it is an unexpected interrupt in the macro code, which is considered to be a malfunction of the macro code or hardware, and is treated as a hardware failure (process 106). Further, an interrupt generated outside the macro code is processed as a normal interrupt (process 104).

Up to now, the processing of the microprogram has been described as the processing for supporting the macro code, but it is also possible to realize a part or all of the processing by a hardware logic circuit.

〔The invention's effect〕

As is clear from the above description, according to the present invention, a new process at the time of interrupt generation can be simplified in a multiprocessor environment without complicating a hardware logic circuit and without increasing a microprogram. And an event occurring in the software use area in the main memory can be efficiently simulated by the instruction execution procedure in the hardware system area. Further, at that time, it is possible to prevent the processing performance from being deteriorated due to unnecessary interrupt processing, and it is possible to enhance the reliability against the malfunction of the hardware.

For example, when simulating a specific instruction, if an underflow (reported as an interrupt) occurs in the processing unit during execution of the instruction execution procedure, the underflow occurrence is positively used in the instruction execution procedure, It is possible to transfer control to another instruction execution procedure and continue the processing. Further, since such underflow should not occur in the instruction execution procedure, it can be considered as a bug, and control can be transferred to failure processing as a hardware malfunction.

As a result, when simulating a specific instruction in the instruction execution procedure, the interrupt can be positively used in the instruction execution procedure even though it is stored in the hardware area. This has the effect of increasing the degree of freedom of.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of an embodiment of an information processing system of the present invention, FIG. 2 is an explanatory diagram of a table of a main memory used when an interrupt occurs, and FIG. 3 is a flow chart of processing when an interrupt occurs. . 10 ... Central processing unit, 11, 12 ... Register in the central processing unit, 20 ... Main storage device, 21 ... Software use area, 22 ... Hardware system area, 30-44 ... Hardware system area A defined area within.

Claims (1)

[Claims] 1. A main storage device is shared by a plurality of central processing units, and the main storage device is divided into a software use area used by normal software and a hardware system area used by hardware. In an information processing device having a function of executing an instruction execution procedure corresponding to the event, which is stored in advance in the hardware system area according to the event occurred in step 1, the hardware system area includes an instruction execution procedure corresponding to the interrupt. Furthermore, when starting the instruction execution procedure in the hardware system area, setting means for setting an interrupt that is expected to occur during execution of the instruction execution procedure, and the expected interrupt by referring to the setting means If so, a means for transferring control to the instruction execution procedure corresponding to the interrupt, and an unexpected interrupt The information processing apparatus is characterized by providing a means to transfer control to the fault processing as malfunction of Dowea.