JPH06195043A - Matrix type liquid crystal display device and its driving method - Google Patents

Abstract

(57) [Abstract] [Purpose] To obtain good contrast and gradation display with good display quality in a method of driving a STN liquid crystal of high speed response. [Structure] A data conversion means for reducing the bit width of input display data, a memory means for storing a plurality of lines of the converted display data, and a plurality of orthogonal functions are provided, and one is selected from these. Function generating means for driving the electrodes, calculating means for calculating the outputs of these means, column electrode driving means for driving the column electrodes according to the output of the calculating means, and row electrodes for driving the row electrodes according to the row electrode driving function It is composed of driving means. [Effect] It is possible to realize a new liquid crystal drive system which does not need to speed up the above-mentioned constitution means, maintains a high contrast, has less flicker, and can perform gradation display with good display quality.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal driving method and a display device thereof, and more particularly to an STN (Super T
The present invention relates to a driving method and a display device for performing high contrast display of a Wisted Nematic liquid crystal and enabling gradation display with good display quality.

[0002]

2. Description of the Related Art As a conventional method for driving a liquid crystal display device having a matrix structure, time division driving by a voltage averaging method is known. This is to display one screen by scanning the row electrodes of the liquid crystal one by one, driving the column electrodes according to the display information, and scanning all the row electrodes. In such a time-division driving method, it is pointed out that the display contrast is lowered when a high-speed STN liquid crystal is used. Therefore, a method for solving this is SID92 Digest "Ac
live Addressing Methodfor
High-Contrast Video-Rate
STN Display ”. (Hereinafter, this method is simply referred to as AA method.) This is to apply a voltage according to a function having orthogonality to the row electrodes, and to the column electrodes, the sum of products of all the display information of the column and the scanning side function. It is a method to give and display the voltage according to the function of. Details will be described below with reference to FIGS. 2 and 3. FIG. 2 is a diagram showing the structure of a matrix type liquid crystal display unit having N rows and M columns, and display dots are formed at the intersections of the row electrodes and the column electrodes. F (1), f (2), ..., f are respectively applied to the N row electrodes.
The voltage represented by the function of (N) is applied, and the voltage represented by the function of g (1), g (2), ..., G (M) is applied to the M column electrodes. U (i, j) indicates the voltage applied to the dot at the intersection of the i-th row and the j-th column, which is the difference voltage between f (i) and g (j). FIG. 3 shows an example of division = 8 in an orthogonal function called a Walsh function.
Now, when the Walsh function of division = T is used as the function of the row electrodes of the liquid crystal display unit of FIG. 2, N of T Walsh functions are selected and applied to f (i) (T ≧ N), and f (i ),
g (j) and effective voltage value Urm of dot U (i, j)
s (i, j) is given by equation (1), equation (2), and equation (3).

[0003]

[Equation 1]

Here, I (i, j) represents dot display information at the intersection of the i-th row and the j-th column, and is assumed to have a value of -1 when the display is on and +1 when the display is off. In addition, w (i, t) is a Walsh function and takes a value of 1 or −1, and F is a formula (4).
Is a constant indicated by.

[0005]

[Equation 2]

If g (j) in the equation (2) is transformed into the form shown in the equation (5),

[0007]

[Equation 3]

[0008] Here, D is I (i,
j) and the number of coincidences of the values of w (i, j) (I (i, j) is ±
1, w (i, j) has a value of ± 1).

Further, a pulse width modulation method (PWM method), which is also used in time-division driving, has been proposed as a method of displaying gradation in the AA method. This method is display 1
It is controlled by L-bit display information given to dots, and a period Δt (a period obtained by dividing one frame period into N equal parts) in which the Walsh function w (i, t) is determined is divided into L and the L division is performed. Gradation display is realized by the combination of the voltage effective values Urms (i, j) indicated by the display information of each bit in each of the periods. In addition, multi-gradation display is possible by weighting each divided period when dividing Δt into L.

[0010]

According to the above-mentioned conventional technique,
It can be expected that the following problems will occur in realizing the gradation display by the PWM method in the A method.

(1) Increase in the number of frame memories The number of frame memories is increased and the number of frame memories is increased as compared with the case of no gradation display (L = 1), leading to an increase in cost.

(2) Speed-up of control circuit When one frame period is fixed, speed-up by L times is required for control of the read-out circuit of the frame memory and the like as compared with the case without gradation. Further, when Δt is divided into L in order to realize a linear multi-gradation display, weighting control is performed in each divided period, so that higher speed is required and the control circuit becomes complicated.

As described above, an object of the present invention is to solve the above problems and to provide a new liquid crystal driving system which realizes gradation display without lowering the contrast even for STN liquid crystal having a high speed response. is there.

[0014]

In order to achieve the above object and to solve the first problem, a first invention is as follows: (1) Reducing the number of display information bits L frame display information is thinned out by a frame thinning method (FRC method). ), It is converted into 1-bit display information that changes for each frame with M frames as one cycle, and this 1-bit display information is loaded into the 1-bit display information frame memory. The following control is the same as the case without gradation. To do. This can reduce the number of frame memories.

As a second invention for solving the second problem, (2) reading from the frame memory, switching every Δt: display information of L bits is set to one M frame by the FRC method.
It is converted into 1-bit display information that changes for each frame as a cycle, and this 1-bit display information is switched to each frame and fetched into M frame memories, while reading is performed from M frame memories every Δt. Switch and perform.
Therefore, the display information can be read out from only one frame memory during the Δt period, and as a result, it is not necessary to increase the speed of the control circuit and control can be performed at the same speed as in the case of no gradation.

[0016]

In the first invention, the voltage effective value Urms of each frame period in one frame of M frame periods
Although (i, j) is different from Uon or Uoff, when converted in the M frame period, the desired voltage effective value is obtained by the combination of the voltage effective values, and the desired gradation display is realized. However, when the value of M becomes large, flicker may occur due to the voltage difference between Uon and Uoff.

In the second invention, the voltage effective value Urms in each frame period in one frame of M frame periods.
(I, j) is a desired voltage effective value located between Uon and Uoff, and a desired gradation display is realized. At this time, since there is no difference in the effective voltage value for each frame, no flickering occurs in the first invention.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to FIGS.
Will be explained. FIG. 1 is a block diagram of a liquid crystal display device according to an embodiment of the present invention. 1 is L-bit display data, and for each bit, display ON is logical 1 and display OFF is logical 0.
It is represented by. 2 is display data conversion means, 3 is conversion display data, 4 is column signal generation means, 5 is column data voltage, 6 is row function generation means, 7 is row function data, and column signal generation means 4 is conversion display. The column data 5 is generated by computing the data 3 and the row function data 7 output from the row function generating means 6. The detailed operations of the display data conversion means 2, the column signal generation means 4, and the row function generation means 6 will be described later. 8 is a column electrode driving means, 9 is a row electrode driving means, 10 is a liquid crystal panel, 11, 12 and 13 are column electrodes, 14, 15 and
Reference numeral 16 is a row electrode. The column electrode driving means 8 takes in the column data voltage 5 for one row and then outputs the data voltages for one row all at once to the liquid crystal panel 10 through the column electrodes 11, 12, 13 for one division time (Δt). . On the other hand, the row electrode driving means 9 fetches the function values of the row for one division time from the splashing function data 7, and then applies a voltage according to the function values all at once to the liquid crystal panel 10 via the row electrodes 13, 14, 15. Output for one divided time (Δt). The row function data 7 is also fetched within one divided time, and is synchronized with the fetch and output operations of the column electrode driving means 8.

FIG. 4 is a diagram showing the details of the column signal generating means 4. 20 is a writing means, 21 is a frame memory,
Reference numeral 22 is a reading means, 25 is data for one column, and the writing means 20 inputs the converted display data 3 and sequentially writes the converted display data 3 in the frame memory 21. Further, the reading means 22 performs an operation of reading the display data for one column from the frame memory 21 and outputting it as the data 25 for one column. 23 is a calculation means, 24 is a voltage conversion means, 26
Is the number of matches. The calculating means 23 calculates the data 25 for one column and the row function data 7, and outputs the number of matches 26.

FIG. 5 is a diagram showing a state of display data stored in the frame memory 21.

FIG. 6 is a diagram showing details of the calculating means 23. Reference numeral 31 is an EX-OR circuit group, 32 is a decoding means, and the EX-OR circuit group 31 performs an exclusive OR operation on the data 25 for one column and the row function data 7, respectively. The decoding means 32 counts the number of logic 0s as a result of the exclusive OR operation, and outputs the number as the coincidence number 26.

The row function generating means 6 outputs an orthogonal function called a Walsh function as row function data 7 for one row during one division time (Δt) as in the prior art.

FIG. 7 is a diagram showing the details of the display data conversion means 2. The display data converting means 2 changes the L-bit display data 1 into 1-bit converted display data 3, and is composed of a frame counter 34 and a data decoder means 33 as shown in FIG.
5 and the display data 1 are decoded to generate the converted display data 3. An example of this will be described with reference to FIG. Here, the value of L is 2, and each bit of the display data 1 is represented as display data 1a and 1b. Frame counter 34
Counts the frames as 1, 2, 3 and the conversion cycle of the display data is 3 frame cycles, the display data 1a,
When 1b is logical 0, the converted display data 3 becomes logical 0 in each frame, and when the display data 1a is logical 0 and the display data 1b is logical 1, the converted display data 3 is the first frame of logical 1, 2, 3 frames. Operates so as to be a logical 0.
The same applies to the case where the display data 1a is logical 1, the display data 1b is logical 0, and the display data 1a and 1b are both logical 1. Note that the frame referred to here is one division time (△
The unit of time is the product of t) and the number of divisions T.

The operation of one embodiment of the above configuration will be described below. The L-bit display data 1 is converted into 1-bit converted display data 3 by the display data conversion means 2 and sent to the column signal generation means 4. The column signal generating means 4 sequentially sends the converted display data 3 to the frame memory 21.
As shown in FIG. 5, U (1,1), U (1,2), U
(1,3), ..., U (1, M), U (2,1), U
(2,2), ..., U (2, M), ..., U (N,
1), U (N, 2), ..., U (N, M) and writing means 20 write. That is, since the converted display data 3 is so-called dot-sequentially transmitted serially, the converted display data 3 is sequentially written in the frame memory 21. next,
The reading means 22 collectively reads the display data written in the frame memory 21 for one column. That is, for the j-th column, U (1, j), U (2, j), ...
, U (N, j) N pieces of display data are read out at the same time to form one row of data 25. This one-column data 25 is input to the calculating means 23 shown in FIG. On the other hand, the row function data 7 is an orthogonal function called a Walsh function, which is N orthogonal functions φ (1), φ during one division time (Δt).
(2), ... φ (N) is generated by the row function generating means 6.
The orthogonal function system is not limited to the Walsh function, and may be any function system that satisfies orthogonality. Further, since the Walsh function has two values of +1 and −1, +1 is defined as a logical 0 and −1 is defined as a logical 1, which will be described below.

The row function data 7 thus generated,
The operation of the calculation means 23 for inputting the data 25 for one column and calculating the number of matches 26 will be described. The processing of the calculating means 23 calculates according to the equation (5). Here, the data 25 for one column of the jth column is U (1, j), U (2, j), ..., U
The row function data 4 is represented by (N, j), and φ (1, t), φ
(2, t), ..., φ (N, t), and by converting the symbol of equation (5),

[0026]

[Equation 4]

Can be expressed as The calculating means 23 calculates according to the equation (6). The calculation of Expression (6) is performed by counting the number of coincident logics between U (i, j) and φ (i, t), and expressing this by the coincidence number D. Details of the operation of the calculating means 23 for actually calculating the equation (6) will be described with reference to FIG. The data 25 for one column and the row function data 7 are input to the EX-OR circuit group 31, respectively. The EX-OR circuit group 31 performs an exclusive OR operation between U (i, j) and φ (i, t). In the exclusive OR operation, the result becomes logical 0 when the input logics match, and the result becomes logical 1 when the input logics do not match. Therefore, the next decoding means 32 counts the number of logic 0s indicating that the logics match from the output of the EX-OR circuit group 31, and outputs the number as the matching number 26.

Next, the matching number 26 is converted into the column data voltage 5 by the voltage converting means 24. The voltage conversion means 24 converts the coincidence number 26 into D according to the equation (6) to g (j) to obtain the column data voltage 5. Then, the column electrode driving means 8 shown in FIG. 1 fetches the column data voltage 5 for one row, and thereafter outputs the data for one row to the liquid crystal panel 10 via the column electrodes 11, 12, 13 all at once.

Next, the bit width L of the display data 1 is 2 (each bit data is 1a, 1b), the number N of display rows is 6,
The operation will be described with reference to FIGS. 9 to 15 by taking the case where the number T of divisions is 8 and driving a liquid crystal panel of 6 rows and M columns as an example. 9, FIG. 11, and FIG. 13 are diagrams showing the number of matches 26 of the calculation means 23 in the display example 1, the display example 2, and the display example 3, respectively, and FIG. 10, FIG. 12, and FIG. 14 are the display example 1 and the table, respectively. FIG. 16 is a diagram showing liquid crystal panel applied voltage waveforms in Display Example 2 and Display Example 3, and FIG. 15 is a diagram showing liquid crystal applied voltage effective values in Display Examples 1, 2, and 3. First, the off display (display example 1) when the display data 1a and 1b given to all the dots in one column (here, j = 1 in the description) is logic 0 will be described. In the display data converting means 2, since the display data 1a and 1b are both logical 0, the converted display data 3 is logical 0 in each frame. The converted display data 3 is written in and read out from the frame memory 21, and the one-column data 25 is input to the arithmetic means 23. Therefore, the data 25 for one column is U for each frame.
From (1,1) to U (6,1) are all 0 logic,
From this one-column data 25 and φ (1, t), φ (6, t)
The row function data 7 up to are calculated by the calculation circuit 23,
The number of matches 26 shown in FIG. 9 is output. This is converted into the column data voltage 5 by the voltage converting means 24 and taken into the column electrode driving means 8, and the liquid crystal panel 1 through the column electrodes 11, 12, and 13.
Output to 0. On the other hand, the row electrode driving means 9 fetches the row function data 7 and applies a voltage corresponding to the function value to the row electrodes 13 and 1.
It outputs to the liquid crystal panel 10 via 4, 15. FIG. 10 shows the waveforms of the row voltage, the column voltage, and the liquid crystal applied voltage that is the difference voltage between the row voltage and the column voltage. In FIG. 10A, i = 1.
The row voltages f (1) and (b) of the row are the column data voltages g (1) of the j = 1st column, and (c) is the waveform of the liquid crystal applied voltage of (i, j) = (1,1) dots. Is shown. Furthermore, FIG.
FIG. 10A is a diagram in which the waveform polarities of FIG. 10C are unified to be positive and the effective value is clarified. One column of data for each frame 2
Since 5 is the same, the average value of the number of coincidences 26 for each frame is the same value, the waveform of the liquid crystal applied voltage is the same waveform for each frame, and the effective value is also the same value, so that the off display is realized. .

Next, the ON display (display example 2) when the display data 1a and 1b given to all the dots are logic 1 will be described. In the display data converting means 2, since the display data 1a and 1b are both logical 1, the converted display data 3 is logical 1 in each frame. The converted display data 3 is written in and read out from the frame memory 21, and the one-column data 25 is input to the arithmetic means 23. Therefore, the data 25 for one column is logical 1 from U (1,1) to U (6,1) in each frame, and the data 25 for one column and φ (1, t) to φ (6, t) are generated. The row function data 7 is calculated by the calculation circuit 23, and the matching number 26 shown in FIG. 11 is output. This is converted into a column data voltage 5 by the voltage converting means 24, taken into the column electrode driving means 8, and outputted to the liquid crystal panel 10 via the column electrodes 11, 12, 13. On the other hand, the row electrode driving means 9 fetches the row function data 7 and outputs a voltage corresponding to the function value to the liquid crystal panel 10 via the row electrodes 13, 14, 15. FIG. 12 shows the waveforms of the row voltage, the column voltage, and the liquid crystal applied voltage that is the difference voltage between the row voltage and the column voltage. 12A shows a row voltage f (1) of i = 1 row, and FIG. 12B shows a column data voltage g of j = 1 column.
(1) and (c) show the waveforms of the liquid crystal applied voltage of (i, j) = (1,1) dots. Further, FIG. 15B is a diagram in which the waveform polarities of FIG. 12C are unified to be positive and the effective value is clarified. Since the data 25 for one column is the same in each frame, the average value of the number of coincidences 26 in each frame is the same value, the waveform of the liquid crystal applied voltage is the same waveform in each frame, and the effective value is also the same value. , ON display is realized.

Next, a certain dot (this is a dot (1,
The display data 1a given to (1) is logic 0, 1b is logic 1, and the display data 1a, 1b given to dots other than this one dot are all logic 0.
The case of gradation display of only one dot (display example 3) in the case of will be described. The display data conversion means 2 converts certain 1-dot display data 1a and 1b into different converted display data 3 for each frame as shown in FIG. That is, 1a is a logical 0,
Since 1b is logical 1, converted display data 3 is generated such that the first frame is logical 1, the second frame, and the third frame is logical 0. Further, since the display data 1a and 1b of dots other than a certain dot are both logical 0, the converted display data 3 is logical 0 in each frame. The converted display data 3 is written in and read out from the frame memory 21, and the one-column data 25 is input to the arithmetic means 23. Therefore, U (1,1) in the data 25 for one column is different for each frame, and the first frame is logical 1, the second frame, and the third frame is logical 0, from U (2,1) to U.
All the frames up to (6, 1) are logic 0.
From this one-column data 25 and φ (1, t), φ (6, t)
The row function data 7 up to are calculated by the calculation circuit 23,
The number of matches 26 shown in FIG. 13 is output. This is converted into the column data voltage 5 by the voltage converting means 24 and taken into the column electrode driving means 8 and the liquid crystal panel 1 via the column electrodes 11, 12 and 13.
Output to 0. On the other hand, the row electrode driving means 9 fetches the row function data 7 and applies a voltage corresponding to the function value to the row electrodes 13 and 1.
It outputs to the liquid crystal panel 10 via 4, 15. FIG. 14 shows the waveforms of the row voltage, the column voltage, and the liquid crystal applied voltage that is the difference voltage between the row voltage and the column voltage. In FIG. 14A, i = 1.
The row voltages f (1) and (b) of the row are the column data voltages g (1) of the j = 1st column, and (c) is the waveform of the liquid crystal applied voltage of (i, j) = (1,1) dots. Is shown. Furthermore, FIG.
FIG. 14C is a diagram in which the waveform polarities of FIG. 14C are unified to be positive and the effective value is clarified. The average value of the number of coincidences 23 for each frame is different between frames, but the average of the number of coincidences 23 in three frames is 3.17, which is between 2.50 during ON display and 3.50 during OFF display. The waveform of the liquid crystal applied voltage is different between the frames, but the liquid crystal applied voltage effective value in three frames is located between the effective voltage value of the on display and the effective voltage value of the off display. A gradation display between on and off is realized.

Although the number of display rows N has been described above as 6 in the above description, the number of display rows N actually becomes a considerably large value such as 240 and 480, and accordingly, one frame period for driving one screen is also long. Therefore, in the case of the gradation method, a difference occurs in the effective value of the liquid crystal applied voltage for each frame. As a result,
Flicker may occur in gradation display. A second embodiment will be described as a method for preventing this flicker.

A second embodiment of the present invention will be described below with reference to FIGS.
Will be explained. FIG. 16 is a block diagram of a liquid crystal display device according to the second embodiment of the present invention. 1 to 3 and 6 to 16 are shown in FIG.
The circuit is the same as that of FIG. 1, but the column signal generating means 40 and the column data voltage 41 are different from those in FIG. FIG. 17 shows the column signal generating means 40.
FIG. 3 is a detailed block diagram of, and will be described using this figure. Three
Is the converted display data converted from the L-bit display data 1 to 1 bit by the display data conversion means 2. Here, the display data converting means 2 takes the one shown in FIG. 8 as an example,
It is assumed that 2-bit display data 1 is converted into display data having a 3-frame period. The selection signal generation means 42 is a frame selection signal 4 for switching 3 frames for each frame.
A division time selection signal 44 for switching the division times 3 and 3 for each division time (Δt) is generated. Reference numeral 45 is a switching means for switching the converted display data 3 to three outputs according to the frame selection signal 43, 46, 47 and 48 are writing means, 49, 50 and 51 are frame memories, and 52, 53, and
Reference numeral 54 is a reading means, and reference numeral 55 is a reading means 52,
It is a selection means for outputting one kind of one-row data 58 from the three kinds of one-row data read from 53 and 54 in accordance with the division time selection signal 44. The calculation means 56 and the voltage conversion means 57 operate similarly to the calculation means 23 and the voltage conversion means 24 of the first embodiment. 59 is the number of matches and 7 is the row function data.

Next, the bit width L of the display data 1 is 2 (each bit data is 1a, 1b), the number N of display rows is 6,
The operation will be described with reference to FIGS. 18, 19 and 20, taking as an example the case where the number of divisions T is 8 and a liquid crystal panel of 6 rows and M columns is driven. FIG. 18 is a diagram showing the number of coincidences 59 of the calculation means 56,
FIG. 19 is a diagram showing a voltage waveform applied to the liquid crystal panel, and FIG. 20 is a diagram showing an effective value of the voltage applied to the liquid crystal panel. FIG. 18 shows that the display data 1a given to one dot (this is referred to as dot (1,1)) is logic 0 and 1b is logic 1, and the display data given to dots other than this one dot This is a case where gradation display is performed only for one dot in which 1a and 1b are all logic 0. The display data conversion means 2 converts certain 1-dot display data 1a and 1b into different converted display data 3 for each frame as shown in FIG. That is 1
Since a is a logical 0 and 1b is a logical 1, converted display data 3 is generated such that the first frame is logical 1, the second frame, and the third frame is logical 0. Further, since the display data 1a and 1b of dots other than a certain dot are both logical 0, the converted display data 3 is logical 0 in each frame. This converted display data 3 is written into the frame memories A49, B50, C51 for each frame by the writing means A46, B47, C48 via the switching means 45, while the one column data of each frame is read out by the reading means A5.
2, B53, C54. Selection means 55
The one-row data 58 is output from the read three-row (A, B, C) one-row data according to the division time selection signal 44, and is input to the computing means 56. For this reason, the data for one column 58 is different for each divided time with three divided times as one cycle. The one-column data 58 and the row function data 7 are calculated by the calculation circuit 56, and the coincidence number 59 shown in FIG. 18 is output. This is converted into the column data voltage 41 by the voltage converting means 57 and taken into the column electrode driving means 8 and the column electrodes 11, 12,
It outputs to the liquid crystal panel 10 via 13. On the other hand, the row electrode driving means 9 fetches the row function data 7 and applies a voltage corresponding to the function value to the liquid crystal panel 1 via the row electrodes 14, 15 and 16.
Output to 0. FIG. 19 shows the waveforms of the row voltage, the column voltage, and the liquid crystal applied voltage which is the difference voltage between the row voltage and the column voltage. FIG. 19A shows a row voltage f (1) of the i = 1st row,
(B) shows the column data voltage g (1) of the j = 1st column, and (c) shows the waveform of the liquid crystal applied voltage of (i, j) = (1,1) dots. Further, FIG. 20B is a diagram in which the waveform polarities of FIG. 19 are unified to be positive and the effective value is clarified. Incidentally, FIG.
0 (a) is a diagram showing the effective value of the liquid crystal applied voltage in the first embodiment. Although the number of coincidence 59 for each frame is different, the average of three frames is 3.17, which is 2.
It is located between 50 and 3.50 at the time of OFF display, and the waveform of the liquid crystal applied voltage is different between frames. However, when looking at the effective value of the liquid crystal applied voltage in three frames, the voltage effective value at the time of ON display and the OFF display are shown. Since it is located between the voltage effective values at the time, gradation display between ON and OFF is realized. Further, as compared with the case of the first embodiment, the difference in the number of coincidences for each frame is significantly smaller, and the effective value difference for each frame is also smaller as shown in FIG. To be realized.

As described above, the bit width L of the display data 1 is described as 2. However, the present invention is not limited to this value, and the case of 2 or more can be similarly considered. At this time, the control of the display data conversion means 2 is L = 2.
Since it is the power -1 frame period, in the case of the first embodiment, this period is likely to appear as flickering in the display.
The second embodiment, in which the difference in the number of coincidences between frames is small, is less flicker and more effective.

The second embodiment is a method of rearranging the liquid crystal applied voltage every one divided time within a certain fixed period, from a different viewpoint. This will be described with reference to FIGS. 14 and 19. FIG. 14 shows a liquid crystal applied voltage waveform for gradation display according to the first embodiment, which is not rearranged. In other words, A, B, and
Assuming that C, A-1, ...
24 voltages are sequentially applied in the order of 8, B-1, ..., B-8, C-1 ,. On the other hand, FIG. 19 shows a liquid crystal applied voltage waveform for gradation display according to the second embodiment, which is an example of rearrangement. That is, in the three frames (a total of 24 divided times) which is one cycle, the liquid crystal displays A-
24 types of voltages are sequentially applied such as 1, B-2, C-3, ..., A-6, B-7, C-8. The liquid crystal is driven according to the effective value of the applied voltage, and if the voltage effective values within a certain fixed period (here, 3 frames) are equal, display of equal brightness is performed. The rearrangement does not affect the display brightness. Further, although the Walsh function has been used as the row function, the row function is not limited to this and may be any function system satisfying the orthogonality. Therefore, the value of t shown in FIG. 19 can be arbitrarily rearranged.

[0037]

As described above, according to the present invention, it is not necessary to increase the speed of the control circuit, and it is possible to maintain the high contrast, which is an advantage of the AA method, with respect to the STN liquid crystal having a high-speed response, and the flicker occurs. It is possible to realize a new liquid crystal drive system that can display gradation with good display quality.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a liquid crystal display device of the present invention.

FIG. 2 is a liquid crystal display unit having a matrix structure of N rows and M columns.

FIG. 3 is a diagram showing an example of division = 8, which is an orthogonal function called a Walsh function.

FIG. 4 is a diagram showing details of a column signal generation means 4.

FIG. 5 is a diagram showing display data stored in a frame memory 22.

FIG. 6 is a diagram showing details of a calculation means 23.

FIG. 7 is a diagram showing details of a display data conversion unit 2.

FIG. 8 is a diagram showing details of a data decoding unit 33.

FIG. 9 is a diagram showing an example 1 of the number of matches 26 in the calculating means 23.

FIG. 10 is a diagram showing a first example of a liquid crystal applied voltage waveform.

FIG. 11 is a diagram showing an example 2 of the number of matches 26 in the calculating means 23.

FIG. 12 is a diagram showing a second example of a liquid crystal applied voltage waveform.

FIG. 13 is a diagram showing an example 3 of the number of matches 26 in the calculating means 23.

FIG. 14 is a diagram showing a third example of a liquid crystal applied voltage waveform.

FIG. 15 is a diagram showing an effective value of a liquid crystal applied voltage.

FIG. 16 is a block diagram of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 17 is a diagram showing details of the column signal generating means 40.

FIG. 18 is a diagram showing an example of the number of coincidences 59 in the calculating means 56.

FIG. 19 is a diagram showing a fourth example of a liquid crystal applied voltage waveform.

FIG. 20 is a diagram showing an effective value of a liquid crystal applied voltage.

[Explanation of symbols]

 1 ... Display data, 2 ... Display data converting means, 3 ... Conversion display data, 4 ... Column signal generating means, 5 ... Column data, 6 ... Row function generating means, 7 ... Row function data, 8 ... Column electrode driving means, 9 ... Row electrode driving means, 10 ... Liquid crystal panel, 11-13 ... Column electrodes, 14-16 ... Row electrodes, 20 ... Writing means, 21 ... Frame memory, 22 ... Readout means, 23 ... Arithmetic means, 24 ... Voltage Conversion means, 25 ... Data for one column, 26 ... Matching number, 31 ... EX-OR circuit group, 32 ... Decoding means, 33 ... Data decoding means, 34 ... Frame counter, 35 ... Frame count value, 40 ... Column signal generating circuit , 41 ... column data, 42 ... selection signal generation means, 43 ... frame selection signal, 44 ... division time selection signal, 45 ... switching means, 46, 47, 48 ... writing means, 4 9, 50, 51 ... Frame memory, 52, 53, 54 ... Read-out means, 55 ... Selection means, 56 ... Calculation means, 57 ... Voltage conversion means, 58 ... One column data, 59 ... Number of coincidences.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tatsuhiro Inuzuka 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Stock Company Hitachi Image Information Systems (72) Inventor Shigeyuki Nishitani 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Hitachi, Ltd. Microelectronics Device Development Laboratory (72) Inventor Yasuyuki Kudo 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Stock Company Hitachi Microelectronics Device Development Laboratory

Claims (8)

[Claims] 1. A matrix type liquid crystal panel comprising N row electrodes and M column electrodes, and the row electrodes applied to one frame at dots at intersections of the row electrodes and the column electrodes. And a method of driving a matrix type liquid crystal display device for determining a voltage effective value of luminance to be displayed by a voltage difference between the voltage of the column electrode and a display of the dot at one intersection with respect to the dot at one intersection in the one frame. Driving a matrix type liquid crystal display device characterized by having a plurality of selection periods for determining a voltage applied to the row electrodes and the column electrodes using information, and switching the plurality of selection periods in consecutive frames Method. 2. The display information according to claim 1, wherein display information of the one dot is divided into display ON and display OFF for each frame in the continuous frame, and gradation display is performed by the one dot. Driving method of matrix type liquid crystal display device. 3. A method for driving a matrix type liquid crystal display device according to claim 2, wherein the number of consecutive frames is 3 frames, and 4 gradations are displayed in 3 frames. 4. A method of driving a matrix type liquid crystal display device according to claim 2, wherein the number of consecutive frames is N frames, and (N + 1) gradation display is performed in N frames. 5. A matrix type liquid crystal panel comprising N row electrodes and M column electrodes, and row signal generating means for generating a row signal for determining a voltage applied to the row electrodes. A row electrode driving means for applying a voltage waveform according to the signal to the row electrode, a column signal generating means for generating a column signal for determining the voltage applied to the column electrode according to display data, and a voltage according to the column signal A column type driving means for applying a waveform to the column electrode, and further a display data rearranging means for rearranging the display data applied to the column signal generating means in successive frames. Liquid crystal display device. 6. A matrix type liquid crystal display device according to claim 5, further comprising display data conversion means for converting input display data having a plurality of bit widths into 1-bit display data. 7. The display data rearranging means according to claim 5 and claim 6, wherein a frame memory for a plurality of frames and a read switching means for switching the plurality of frame memories for each selected period and reading the display data are used. A matrix type liquid crystal display device characterized in that 8. A matrix type liquid crystal display device according to claim 6, wherein said row signal generating means, said display data converting means and said column signal generating means are a one-chip display controller. apparatus.