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JPH0619115A - Mask for stepper - Google Patents

Mask for stepper

Info

Publication number
JPH0619115A
JPH0619115A JP19598992A JP19598992A JPH0619115A JP H0619115 A JPH0619115 A JP H0619115A JP 19598992 A JP19598992 A JP 19598992A JP 19598992 A JP19598992 A JP 19598992A JP H0619115 A JPH0619115 A JP H0619115A
Authority
JP
Japan
Prior art keywords
mask
size
pattern
photoresist
dimension
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19598992A
Other languages
Japanese (ja)
Inventor
Keiichiro Tonai
圭一郎 東内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP19598992A priority Critical patent/JPH0619115A/en
Publication of JPH0619115A publication Critical patent/JPH0619115A/en
Pending legal-status Critical Current

Links

Landscapes

  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

PURPOSE:To lessen the dimensional change with the defocusing of a photoresist size stepped to a mask size, to widen a focusing allowance and to enable the formation of fine size patterns. CONSTITUTION:The size (mask size) of the mask patterns 1 for stepping to a photoresist is pet at the size obtd. by adding a mask bias size DELTAL set to minimize the change in the photoresist size by the defocusing at the time of exposure to the design pattern size L of a semiconductor device. For example, the mask bias size is set at an optimum value according to the wavelength of exposing light of the stepper, numerical aperture, coherent factor, and the pattern widths of the respective design patterns.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の製造に使用
されてパターン投影を行うための投影露光装置用マスク
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mask for a projection exposure apparatus used for manufacturing a semiconductor device and performing pattern projection.

【0002】[0002]

【従来の技術】従来、この種のマスクは、半導体装置に
形成するパターンと同一パターンをマスクパターンとし
て構成しており、このパターンを半導体装置に形成した
フォトレジストに露光し、フォトレジストを現像し、残
されたフォトレジストを用いてエッチング形成すること
で半導体装置に前記したパターンを形成している。或い
は、露光装置におけるパターン間の近接効果を考慮し
て、オンフォーカスでの光強度形状と、これにより形成
されるフォトレジスト形状のシミュレーション結果を用
いて得られた近接効果を補正したマスクパターンを用い
ている。
2. Description of the Related Art Conventionally, a mask of this type is constructed by using the same pattern as a pattern formed on a semiconductor device as a mask pattern. This pattern is exposed on a photoresist formed on the semiconductor device and the photoresist is developed. The pattern described above is formed on the semiconductor device by etching using the remaining photoresist. Alternatively, in consideration of the proximity effect between the patterns in the exposure apparatus, a mask pattern in which the proximity effect is corrected by using the light intensity shape in on-focus and the simulation result of the photoresist shape formed by this is used. ing.

【0003】図5はラインパターンがライン寸法と同一
間隔Lで並んでいる設計パターン通り設計したときのマ
スクパターンである。図6はこのマスクを用い、ネガ型
フォトレジストを形成したときの、フォトレジスト寸法
のデフォーカス依存性を示したものである。これから、
オンフォーカスのときとデフォーカスとでは設計寸法と
レジスト寸法との間に誤差が生じることが判る。又、こ
の誤差は露光量の変化によっても変化されることが判
る。通常では、露光量の設定は、オンフォーカスのとき
にフォトレジストの寸法がマスク通りに形成されるよう
に設定する。
FIG. 5 shows a mask pattern when designed according to a design pattern in which line patterns are arranged at the same interval L as the line size. FIG. 6 shows the defocus dependence of the photoresist size when a negative photoresist is formed using this mask. from now on,
It can be seen that an error occurs between the design dimension and the resist dimension when the focus is on and when the focus is defocus. It can also be seen that this error is changed by the change of the exposure amount. Normally, the exposure amount is set so that the dimensions of the photoresist are formed according to the mask when on-focus.

【0004】[0004]

【発明が解決しようとする課題】このように、従来のマ
スクは設計寸法と同一寸法に形成しても、露光装置のフ
ォーカスにずれが生じると、オンフォーカスでのパター
ンに対するパターンの変形が大きくなるという問題があ
る。この寸法変化は、パターン寸法が微細になる程大き
くなる傾向があり、この寸法変化が製造寸法許容幅を越
えると、製造される半導体装置が不良となるため、フォ
ーカス余裕度が狭いという問題がある。フォーカスがず
れる原因は露光装置の焦点合わせ精度や、半導体基板の
反り、半導体装置表面のパターンに起因する凹凸等であ
り、これらの余裕度を考慮して最小設計寸法を決定する
必要がある。本発明の目的は、デフォーカスに対する寸
法変化を低減し、フォーカス余裕度を拡大するととも
に、微細な寸法パターンの形成を可能にした投影露光装
置用マスクを提供することにある。
As described above, even if the conventional mask is formed in the same size as the designed size, if the focus of the exposure apparatus is deviated, the pattern is largely deformed in the on-focus pattern. There is a problem. This dimensional change tends to increase as the pattern size becomes finer. If this dimensional change exceeds the manufacturing size tolerance, the manufactured semiconductor device becomes defective, and there is a problem that the focus margin is narrow. . The cause of defocus is the focusing accuracy of the exposure apparatus, the warp of the semiconductor substrate, the unevenness due to the pattern on the surface of the semiconductor device, etc., and it is necessary to determine the minimum design dimension in consideration of these margins. An object of the present invention is to provide a mask for a projection exposure apparatus that reduces dimensional change due to defocus, expands focus margin, and enables formation of a fine dimensional pattern.

【0005】[0005]

【課題を解決するための手段】本発明は、露光時での焦
点ずれによるフォトレジスト寸法の変化が最小となるよ
うに設定したマスクバイアス寸法を、半導体装置の設計
パターン寸法に付加したマスク寸法に設定する。例え
ば、マスクバイアス寸法は、投影露光装置の露光光波
長,開口数,コヒーレント要因,各設計パターンのパタ
ーン幅に応じて最適値に設定される。
SUMMARY OF THE INVENTION According to the present invention, a mask bias dimension set so as to minimize a change in photoresist dimension due to defocus during exposure is added to a mask dimension added to a design pattern dimension of a semiconductor device. Set. For example, the mask bias dimension is set to an optimum value according to the exposure light wavelength of the projection exposure apparatus, the numerical aperture, the coherent factor, and the pattern width of each design pattern.

【0006】[0006]

【実施例】次に、本発明について図面を参照して説明す
る。図1は本発明のマスクパターンを示す図である。図
6に示したフォトレジスト寸法と設計寸法とのデフォー
カス依存性によれば、マスクと−ΔLpだけ寸法が異な
るピボタルポイントに露光量を設定すると、デフォーカ
スしたときの寸法変化が最小となることが判る。そこ
で、設計寸法にマスクバイアスを付加することによりフ
ォトレジストパターンが設計寸法でピボタルポイントに
なるようにする。図1のように、マスクパターン1のラ
イン寸法を設計値に対してバイアス寸法ΔLを付加す
る。一方、ライン1間の寸法はバイアス寸法ΔLを差し
引いている。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a mask pattern of the present invention. According to the defocus dependence between the photoresist size and the design size shown in FIG. 6, when the exposure amount is set to a pivotal point whose size is different from that of the mask by −ΔLp, the size change upon defocusing is minimized. I understand. Therefore, a mask bias is added to the design dimension so that the photoresist pattern becomes a pivotal point in the design dimension. As shown in FIG. 1, the bias dimension ΔL is added to the design value of the line dimension of the mask pattern 1. On the other hand, the dimension between the lines 1 is obtained by subtracting the bias dimension ΔL.

【0007】このようにして形成したマスクを用いたフ
ォトレジスト寸法の出フォーカス依存性を図2に示す。
この場合、レジスト寸法が設計寸法の場合、最もデフォ
ーカスによる寸法変化が少なくなるピボタルポイントと
なる。この最適マスクバイアス値は、露光装置の露光光
波長,コヒーレント因子,開口数,パターン寸法等によ
りことなる。
FIG. 2 shows the dependence of the photoresist dimension on the out-of-focus using the mask thus formed.
In this case, when the resist dimension is the design dimension, the pivotal point is where the dimension variation due to defocus is minimized. The optimum mask bias value depends on the exposure light wavelength of the exposure apparatus, the coherent factor, the numerical aperture, the pattern size, and the like.

【0008】図3は図1のマスクパターンを形成する際
の設計手順を示す図である。あらかじめ各露光装置,各
パターン寸法でのマスクバイアス値を求めておく。次
に、実際の半導体装置の設計パターンのパターン寸法に
合わせて求められたマスクバイアス値を選択し、これを
付加してマスクパターンのパターン寸法とする。
FIG. 3 is a diagram showing a design procedure for forming the mask pattern of FIG. The mask bias value for each exposure device and each pattern dimension is obtained in advance. Next, the mask bias value obtained in accordance with the pattern dimension of the actual design pattern of the semiconductor device is selected and added to obtain the pattern dimension of the mask pattern.

【0009】ここで、図4に示すようなマスクパターン
設計手順としてもよい。即ち、設計パターンをマスクパ
ターンとしてデフォーカスによるフォトレジストパター
ンの寸法変化をサンプル3次元シミュレータ等により求
める。これから各パターン端におけるマスクバイアス値
としてマスクパターンを補正し、再度シミュレーション
する。この手順を1乃至数回繰り返して最適マスクパタ
ーンを求める。この方法では、数回のレジストパターン
シミュレーションが必要なため、前記実施例に比べてコ
ンピュータによる長時間の計算が必要となるが、実際の
設計パターンに基づいて計算するため、より正確に最適
マスクバイアス値を求めることができるという利点があ
る。特に、設計ルールが厳しく、高い寸法精度が必要な
パターンのマスクに適している。
Here, the mask pattern design procedure as shown in FIG. 4 may be adopted. That is, using the design pattern as a mask pattern, the dimensional change of the photoresist pattern due to defocus is obtained by a sample three-dimensional simulator or the like. Then, the mask pattern is corrected as the mask bias value at each pattern end, and the simulation is performed again. This procedure is repeated one to several times to find the optimum mask pattern. Since this method requires several times of resist pattern simulation, it requires a long time calculation by a computer as compared with the above-mentioned embodiment, but since it is calculated based on an actual design pattern, it is more accurate in optimal mask bias. There is an advantage that the value can be obtained. In particular, it is suitable for a mask of a pattern that has strict design rules and requires high dimensional accuracy.

【0010】[0010]

【発明の効果】以上説明したように本発明は、露光時で
の焦点ずれによるフォトレジスト寸法の変化が最小とな
るように設定したマスクバイアス寸法を、半導体装置の
設計パターン寸法に付加したマスク寸法に設定している
ので、デフォーカスの依存性はデフォーカスに対して最
も寸法変化が少ないピボタルポイントとなり、フォーカ
ス余裕度を各段に拡大することができる。これにより、
製造マージンの拡大や、より微細な寸法パターンの使用
が可能になる等の効果がある。
As described above, according to the present invention, the mask bias dimension set to minimize the change in the photoresist dimension due to the defocus during the exposure is added to the design pattern dimension of the semiconductor device. Since the defocus dependency is the pivotal point with the smallest dimensional change with respect to the defocus, the focus margin can be further expanded. This allows
There are effects such as expansion of the manufacturing margin and use of a finer dimension pattern.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明のマスクのパターン例を示すマスクパタ
ーン図である。
FIG. 1 is a mask pattern diagram showing a pattern example of a mask of the present invention.

【図2】図1のマスクパターンによるフォトレジスト寸
法のデフォーカス依存性を示す図である。
FIG. 2 is a diagram showing the defocus dependence of the photoresist dimension by the mask pattern of FIG.

【図3】図1のマスクパターンの設計手順を示す図であ
る。
FIG. 3 is a diagram showing a procedure for designing the mask pattern of FIG.

【図4】設計手順の他の例を示す図である。FIG. 4 is a diagram showing another example of a design procedure.

【図5】従来のマスクのパターン例を示すマスクパター
ン図である。
FIG. 5 is a mask pattern diagram showing an example of a conventional mask pattern.

【図6】従来のマスクパターンによるフォトレジスト寸
法のデフォーカス依存性を示す図である。
FIG. 6 is a diagram showing a defocus dependence of a photoresist dimension by a conventional mask pattern.

【符号の説明】[Explanation of symbols]

1 ライン(マスクパターン) L ライン幅 ΔL マスクバイアス寸法 1 line (mask pattern) L line width ΔL Mask bias dimension

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体装置に設けられたフォトレジスト
に対して投影露光を行うためのマスクにおいて、露光時
での焦点ずれによるフォトレジスト寸法の変化が最小と
なるように設定したマスクバイアス寸法を、半導体装置
の設計パターン寸法に付加したマスク寸法に設定したこ
とを特徴とする投影露光装置用マスク。
1. A mask bias dimension set in a mask for performing projection exposure on a photoresist provided in a semiconductor device, wherein a mask bias dimension set so as to minimize a change in photoresist dimension due to defocus during exposure. A mask for a projection exposure apparatus, which is set to a mask size added to a design pattern size of a semiconductor device.
【請求項2】 マスクバイアス寸法は、投影露光装置の
露光光波長,開口数,コヒーレント要因,各設計パター
ンのパターン幅に応じて最適値に設定される請求項1の
投影露光装置用マスク。
2. The mask for a projection exposure apparatus according to claim 1, wherein the mask bias dimension is set to an optimum value according to the exposure light wavelength of the projection exposure apparatus, the numerical aperture, the coherent factor, and the pattern width of each design pattern.
JP19598992A 1992-06-30 1992-06-30 Mask for stepper Pending JPH0619115A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19598992A JPH0619115A (en) 1992-06-30 1992-06-30 Mask for stepper

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19598992A JPH0619115A (en) 1992-06-30 1992-06-30 Mask for stepper

Publications (1)

Publication Number Publication Date
JPH0619115A true JPH0619115A (en) 1994-01-28

Family

ID=16350370

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19598992A Pending JPH0619115A (en) 1992-06-30 1992-06-30 Mask for stepper

Country Status (1)

Country Link
JP (1) JPH0619115A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002093259A1 (en) * 2001-05-10 2002-11-21 Sony Corporation Rule base opc evaluating method, and simulation base opc model evaluating method
US6557163B1 (en) 2001-11-30 2003-04-29 International Business Machines Corporation Method of photolithographic critical dimension control by using reticle measurements in a control algorithm
US6656646B2 (en) 2001-08-31 2003-12-02 Hitachi, Ltd. Fabrication method of semiconductor integrated circuit device
WO2004072735A1 (en) * 2003-02-17 2004-08-26 Sony Corporation Mask correcting method
US6811900B2 (en) 2001-05-29 2004-11-02 Jfe Steel Corporation Unidirectional silicon steel sheet of ultra-low iron loss and method for production thereof
KR100423917B1 (en) * 1995-03-13 2005-02-02 소니 가부시끼 가이샤 Correction method and correction device for mask pattern

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100423917B1 (en) * 1995-03-13 2005-02-02 소니 가부시끼 가이샤 Correction method and correction device for mask pattern
WO2002093259A1 (en) * 2001-05-10 2002-11-21 Sony Corporation Rule base opc evaluating method, and simulation base opc model evaluating method
US6928636B2 (en) 2001-05-10 2005-08-09 Sony Corporation Rule based OPC evaluating method and simulation-based OPC model evaluating method
US6811900B2 (en) 2001-05-29 2004-11-02 Jfe Steel Corporation Unidirectional silicon steel sheet of ultra-low iron loss and method for production thereof
US6656646B2 (en) 2001-08-31 2003-12-02 Hitachi, Ltd. Fabrication method of semiconductor integrated circuit device
US6557163B1 (en) 2001-11-30 2003-04-29 International Business Machines Corporation Method of photolithographic critical dimension control by using reticle measurements in a control algorithm
WO2004072735A1 (en) * 2003-02-17 2004-08-26 Sony Corporation Mask correcting method
US7438996B2 (en) 2003-02-17 2008-10-21 Sony Corporation Mask correcting method

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