JPH06188867A - Digital signal communication system - Google Patents

Abstract

PURPOSE:To provide a high quality economical digital signal communication system by preventing signal omission due to same code continuation in an STM digital network. CONSTITUTION:A transmitter 10 is provided with means (11 to 15) for inputting the parallel input signals 1 of 8n {(n) is a natural number} bytes, turning them to the signals of (8n+1) columns for which one bit of auxiliary codes 1a or the mark signals 4 of an 'H' level is added and further outputting transmission signals 2 for which the signals are time division multiplexed on 1 channel. A receiver 20 is provided with the means (21 to 31) for separating the received transmission signals 2 to the signals of (8n+1) columns, further detecting the auxiliary codes 1a or the mark signals 4 added at the transmitter 10, supplying cyclic permutation to a signal system so that the bit is outputted to the position of the channel added at the transmitter 10 and outputting the desired output signals 9 of 8n columns and the means (32) for protecting synchronization.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in a digital signal communication system, and in particular, in a transmitter, a predetermined logic is applied to a signal sequence of an input terminal so that the same code does not continue in a code transmitted to a transmission line. The present invention relates to a digital signal communication system using a communication signal conversion method in which a code conversion is performed and transmitted to a transmission line, and a reception device performs inverse conversion of the predetermined logic on a signal sequence received from the transmission line to obtain a reception output.

[0002]

2. Description of the Related Art Not only in the optical fiber communication system but also in the data communication system, if the code of the same signal continues in the code of the transmission signal sequence, the receiving point cannot detect the change point of the code and the signal cannot be synchronized correctly. There is. In order to solve this, there is known a technique in which a transmitter performs code conversion on a signal by a predetermined logic to change a code of a transmission signal sequence, and a receiving device performs an inverse conversion to reproduce an original signal sequence. Has been. In such a system, there are some logics for performing code conversion on the transmission signal. One of them is mB1C (m binary with
1 complement insertion), and the other one is DmB1M (differential).
ial m binary with 1 mark
insertion).

The synchronization of communication networks is progressing according to the recommendation by CCITT (International Telegraph and Telephone Consultative Committee) regarding digital synchronization networks. There, a method of time division multiplexing (byte multiplexing) in units of bytes is adopted instead of the time division multiplexing method (bit multiplexing) in units of bits that has been applied to the conventional large capacity transmission line in an asynchronous network.

[0004]

However, the above-described countermeasures for suppressing homo-code continuity are only digital scrambling, which is not sufficient. The scrambler is intended to randomize the code sequence. For example, as shown in FIG.
In b / s, 50-bit homo-coded sequences occur once a day. To endure this, the requirements for low-frequency cutoff and timing retention of the equalization amplification system in the 3R repeater become strict, so a high-performance repeater analog circuit is required, and a high-quality transmission line is economically provided. There was a flaw that I could not do.

It is an object of the present invention to provide a byte demultiplexer that is becoming popular in synchronous networks with mB1C or Dm1B1.
An object of the present invention is to provide a digital signal communication system capable of constructing a high-quality and economical transmission line by applying the M code conversion to prevent signal loss due to the same code continuation in the transmission line forming the synchronous network.

[0006]

The present invention provides a digital communication signal system comprising means for synchronously transmitting a digital signal from a transmitter to a receiver via a transmission line,
The transmitting device inputs a plurality of m columns of input signals in parallel, and converts the signal speed to (m + 1) / m times, and a 1-bit complementary code of the input signal to the speed-converted m columns of signals. And a means for generating a signal of the (m + 1) -th column by adding the above signal and a means for time-division-multiplexing the generated signal of the (m + 1) -th column into one channel and outputting the signal as a transmission signal to the transmission path. The received transmission signal by (m +
1) means for time-division separation into a signal of a column, means for detecting the complementary code added by the transmission device from the separated signal sequence, and this bit is output to the channel position added by the transmission device As described above, the signal system is provided with means for applying cyclic permutation to output a desired m-column output signal, and means for protecting synchronization.

Further, the present invention is a digital signal communication system comprising means for synchronously transmitting a digital signal from a transmitting device to a receiving device via a transmission path, wherein the transmitting device inputs a plurality of m columns in parallel. Input the signal (m + 1)
/ M times the signal speed conversion means, a means for adding a "high" level mark signal to the speed-converted input signal of the m-th column to make a signal of the (m + 1) -th column, Means for time-division-multiplexing signals into one channel, further summing them, and outputting to the transmission path as a transmission signal, wherein the receiving device takes the difference between the received transmission signals and converts it into a (m + 1) -channel signal. Time division means, means for detecting the mark signal added on the transmission side from the separated signal sequence, and cyclic permutation in the signal system so that this bit is output to the channel position added by the transmission device. It is characterized in that it is provided with means for outputting an output signal of the desired m columns and means for protecting the synchronization.

Further, the present invention is a digital signal communication system comprising means for synchronously transmitting a digital signal from a transmitting device to a receiving device via a transmission path, wherein the transmitting device is provided with inputs of a plurality of m columns arranged in parallel. Input the signal (m + 1)
/ M times the signal speed conversion means, and 1 of the input signal according to the mode switching signal to the signal of the m column which is speed conversion
Means for adding either the bit complement sign or the "high" level mark signal to generate the (m + 1) column signal;
The received signal is received by the receiving device, comprising means for time-division-multiplexing the generated (m + 1) -th column signal into one channel and outputting the signal as it is or as a transmission signal to the transmission path according to the mode switching signal. According to the mode switching signal, the transmission signal may be used as it is or by taking a difference (m +
1) means for time-division separation into column signals, means for detecting the complementary code or the mark signal added by the transmission device according to the mode switching signal from the separated signal sequence, and this bit is for the transmission device It is characterized in that it is provided with means for applying cyclic permutation to the signal system so as to be output to the added channel position and outputting a desired m-column output signal as an output signal, and means for protecting synchronization.

In the present invention, m = 8n (n is a natural number)
Is preferred.

[0010]

The present invention relates to an STM (synchronous system) digital network,
The mB1C or DmB1M code conversion method is applied. Then, 8 or an integer multiple thereof is selected as the m value, and additional bits are given for each individual or a plurality of bytes as a unit.

Therefore, as the essence of these code conversion methods, it is possible to prevent signal loss due to the same code continuation, and
The compatibility with the byte multiplexing system can be improved, and as a result, the encoding / decoding device can be simplified and simplified, and a high-quality and economical transmission path can be constructed.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the first embodiment of the present invention.

The first embodiment is a digital signal communication system provided with means for synchronously transmitting a digital signal from the transmission device 10 to the reception device 20 via the transmission line 40, which is a feature of the present invention. The transmission device 10 inputs a byte-by-byte input signal 1 of a plurality of parallel 8n (n is a natural number) columns, and a speed conversion circuit (SC) 11 as means for converting the signal speed to (8n + 1) / 8n times. According to the mode switching signal 3, either the 1-bit complementary code 1a of the input signal or the "high" level mark signal 4 is added to the speed-converted (8n + 1) -column signal to generate the (8n + 1) -column signal. Mode switching circuit (MC) 1 as means
2 and (8n + 1): 1 as a means for time-division-multiplexing the generated (8n + 1) -column signals into one channel and directly or summing them according to the mode switching signal 3 and outputting them as the transmission signal 2 to the transmission line 40: Multiplexing circuit (MUX)
13, summation circuit (AC) 14 and selector (SL) 1
5, the receiving device 20 includes a difference circuit (DC) as means for time-division separating the received transmission signal 2 into the mode switching signal 3 as it is or according to the same mode switching signal 6 or by taking the difference. ) 21, selector (S
L) 22 and 1: (8n + 1) separation circuit (DMU)
X) 23 and the complementary signal 1a or mark signal 4 added by the transmitter 10 according to the mode switching signal 6 from the separated signal sequence, and this bit is output to the channel position added by the transmitter 10. Of the bit shift circuit (BS) 24 and the reception mode switching circuit (RM) as means for giving cyclic substitution to the signal system and outputting the 8n-column output signal 9.
C) 25, fall detection circuit (FD) 26, encoder (ECD) 27, isolation detection circuit (ID) 28, pseudo sync pulse generation circuit (DSP) 29, channel shift pulse generation circuit (CSP) 30, and erasure detection Circuit (AN
D) 31 and a synchronization protection circuit (SP) 32 as a means for protecting synchronization. Reference numeral 33 is a code error detection circuit (MMC).

Next, the operation of the first embodiment will be described.

An input signal 1 which is an n-channel byte parallel signal (total of 8n bits) is input to the speed conversion circuit (SC) 11 through the input terminal of the transmission device 10. The multiplexing circuit (MUX) 13 receives the input signal 1 of the 8n-bit channel.
, And a 1-bit surplus code is added, and time-division multiplexing is performed on a signal of 1 channel. In the case of mB1C conversion, this surplus code is the complementary code 1a of the 1-bit signal of the 8n-bit input signal, and in the case of DmB1M conversion, it is always the mark signal 4 of "1". M
C) Switch with 12. FIG. 1 shows a configuration in which a complementary code 1a for the bits at the ends of the aligned bit string is added.

The multiplexed signal is branched into two, one of which is input as it is, and the other of which is input to a 2: 1 selector (SL) 15 through a summing circuit (AC) 14 for performing Japanese sentence conversion. mB
In the case of 1C conversion, the combination of the complementary code 1a and no conversion,
In the case of DmB1M conversion, the mode switching circuit (MC) 12 and the selector (S
L) 15 is controlled by the mode switching signal 3 from the mode switching terminal. When fixing the transmission path code to mB1C, the complementary code 1a is always wired so as to be input to the multiplexing circuit (MUX) 13, and the mode switching circuit (MC) 12 and the summing circuit (A
C) 14 and selector (SL) 15 can be omitted. Similarly, when the DmB1M code is fixed, the mark signal 4 is always wired so as to be input to the multiplexing circuit (MUX) 13, and its output is always output through the summing circuit (AC) 14. .

In the receiver 20, the received signal 5 which is a multiplexed signal is branched into two, one of which is unprocessed and the other of which is passed through a differential circuit (DC) 21 and a 2: 1 selector (SL) 22.
Entered in. Mode switching signal 6 from the mode switching terminal
Is wired so as to select an unprocessed signal in the case of mB1C and a differentially converted signal in the case of DmB1M code. The signal from the selector (SL) 22 becomes a parallel signal in the 1: (8n + 1) separation circuit (DMUX) 23, and the speed is reduced.
The parallelized signal is input to the bit shift circuit (BS) 24. This circuit is an encoder (ECD) 2 described later.
A cyclic permutation of up to 8n bits is given according to the signal from 7.

The output of the bit shift circuit (BS) 24 is then input to the reception mode switching circuit (RMC) 25.
The reception mode switching circuit (RMC) 25 takes the exclusive OR of adjacent bits for the mB1C code and outputs the same number as the input, and outputs the input as it is for the DmB1M code. Switch by.

The output from the reception mode switching circuit (RMC) 25 is an 8n + 1-bit falling detection circuit (FD) 2
Enter in 6. The fall detection circuit (FD) 26 has means for fixing the output to the “L” level if the input signal has a fall even once after resetting. For example, an edge trigger type set / reset flip-flop is 8n + 1.
It can be realized by arranging them individually. Looking at the output from the fall detection circuit (FD) 26, only the bits added by the transmission device 10 maintain the “H” level, and the other bits are “L” stochastically generated due to the randomness of the signal.
The output is fixed to the "L" level by the fall to the level.

The output of the fall detection circuit (FD) 26 is branched into three, and an encoder (ECD) 27, an isolation detection circuit (ID) 28, and an annihilation detection circuit (AN) are respectively provided.
D) Input to 31. The encoder (ECD) 27 generates a binary number indicating the channel position of the additional bit, and the isolation detection circuit (ID) 28 keeps only one of the 8n + 1-bit channels at "H" level and the other channels at "L" level. It detects whether it is at the level. The annihilation detection circuit (AND) 31 is not always necessary, but the additional bit channels include a falling edge due to a code error, which causes the output of the falling edge detection circuit (FD) 26 to become the “L” level for all channels. To prepare for the case. In that case, the fall detection circuit (FD)
Issue a pulse to reset 26.

Of the output of the fall detection circuit (FD) 26, the channel (8 in the example of FIG. 1) in which the additional bit should appear.
The (n + 1) th signal is branched and further input to the pseudo synchronization pulse generation circuit (PSP) 29 and the channel shift pulse generation circuit (CSP) 30. These two circuits include
Further, a signal from the isolation detection circuit (ID) 28 is also input, and the operation is performed at a position where the position of the additional bit channel is identified at any position. That is, the channel shift pulse generation circuit (CSP) 30 generates a pulse when the additional bit does not appear in the 8n + 1th bit channel, even though only one channel is at the “H” level, and this pulse is encoded. The bit shift circuit (BS) 24 is reset based on the output of the (ECD) 27, and the fall detection circuit (FD) 26 is reset again.

By this operation, the additional bit channel is 8n.
It will appear at the + 1st position, and all other information bits will be aligned in the same manner as the input array at the transmitter 10. 8n + 1 from the fall detection circuit (FD) 26
If the th bit channel always outputs "1" level, the pseudo sync pulse generation circuit (PSP) 29 sends 1 to the sync protection circuit (SP) 32 for each transmission path code frame.
Keeps generating one pulse. Sync protection circuit (SP) 32
Is the same as in a general synchronization circuit, the synchronization is maintained by keeping the state so that synchronization may not be lost due to a code error, or the same signal as an accidental code string may be mistaken for a transmission line code frame and other circuits may not operate. The detection signal 8 is output.

The external reset signal 7 initializes the entire circuit when the operation is started up. The information sequence received in the correct array is obtained as the output signal 9 from the output terminal of the bit shift circuit (BS) 24 which outputs 8n bits.

FIG. 2 is a block diagram showing the second embodiment of the present invention.

The second embodiment shows the main part of the encoding / demultiplexing circuit when the present invention is realized by the 8B1C code.

In FIG. 2, the transmitting side has a scrambler 5
1, a speed conversion circuit (SC) 52, a 9: 1 multiplexing circuit (MUX) 53, and a receiving side includes a 1: 9 separation circuit (DMUX) 61, a channel shift circuit 62, and a frame synchronization circuit 63. Contains. Then, the multiplexing circuit (MUX) 53 is 3: because of the feasibility as an integrated circuit.
It is composed of four multiplexing circuits of 1.

Next, the operation of the second embodiment will be described. The 8-byte input signal input through the scrambler circuit 51 is sent to the speed conversion circuit (SC) 52 and has a speed of 9
One of the 8 bits that make up the byte and are converted to 8 times
The 8B1C code is generated by extracting and adding the bit complementary code # 8I (# 8I represents the inverted code of # 8) and performing 9: 1 multiplexing by the multiplexing circuit (MUX) 53.

On the receiving side, the separation circuit (DMUX) 61 performs 1: 9 separation and inputs it to the channel shift circuit 62. The channel shift circuit 62 performs bit shift to detect a complementary code (# 8I), thereby aligning bytes and outputting an output signal via the frame synchronization circuit 63.

Normally, when the STM frame sync signal is byte-parallelized, it is necessary to specially perform byte alignment, but in the second embodiment, the byte alignment can be performed by detecting the complementary code. it can.

Note that the D8B1M code instead of the 8B1C can be similarly implemented by providing the mark signal, the summing circuit on the transmitting side and the difference circuit on the receiving side in the circuit of FIG.

As explained above, 8B1C and D8
The use of the B1M code has an advantage that the circuit configuration is simplified and a digital signal communication system using a synchronous network STM frame without the continuation of the same code can be realized more easily.

FIG. 3 is a schematic diagram of a 3: 1 multiplexing circuit prototyped using GaAs MESFETs in the second embodiment.
It shows an output waveform at 0 GHz. FIG. 3 shows the clock CK, the positive phase waveform QT, and the negative phase waveform QC from the top.
In this case, the input is fixed to "100".

[0034]

As described above, according to the present invention,
By performing code conversion with good compatibility on a synchronous network STM frame that does not have an absolute homo-code continuity suppressing function, a transmission line that is not deteriorated by homo-code continuity can be obtained even with relatively low-performance circuit components. Further, the transmission line error detection means by monitoring the additional bits, and the byte alignment means which is indispensable when performing signal processing such as frame synchronization at a speed lower than the transmission line clock rate are substituted. A means for aligning the separated byte signals at the receiving end can also be obtained, and a high-quality and economical transmission line can be provided, and its effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram showing the first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a characteristic diagram showing an example of its operation characteristics.

FIG. 4 is a diagram showing an example of homo-code consecutive occurrence frequencies in a conventional digital signal communication system.

[Explanation of symbols]

 1 Input signal 1a Complementary code 2 Transmission signal 3, 6 Mode switching signal 4 Mark signal 5 Reception signal 7 External reset signal 8 Synch detection signal 9 Output signal 10 Transmission device 11, 52 Speed conversion circuit (SC) 12 Mode switching circuit (MC ) 13, 53 Multiplexing circuit (MUX) 14 Summing circuit (AC) 15, 22 Selector (SL) 20 Receiver 21 Difference circuit (DC) 23, 61 Separation circuit (DMUX) 24 Bit shift circuit (BS) 25 Reception Mode switching circuit (RMC) 26 Fall detection circuit (FD) 27 Encoder (ECD) 28 Isolation detection circuit (ID) 29 Pseudo sync pulse generation circuit (PSP) 30 Channel shift pulse generation circuit (CSP) 31 Complete deletion detection circuit (AND ) 32 synchronization protection circuit (SP) 33 code error detection circuit (MMC) 51 scrambling 62 channel shift circuit 63 the frame synchronization circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kiyoji Nakagawa 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation

Claims (4)

[Claims] 1. A digital communication signal system comprising means for synchronously transmitting a digital signal from a transmitting device to a receiving device via a transmission path, wherein the transmitting device receives input signals of a plurality of m columns in parallel. Means for converting the signal speed to (m + 1) / m times, means for adding a 1-bit complementary sign of the input signal to the speed-converted signal of the m-th column to generate a signal of the (m + 1) -th column, Means for time-division-multiplexing the generated (m + 1) -th column signal into one channel and outputting it as a transmission signal to the transmission path, wherein the receiving device temporally converts the received transmission signal into a (m + 1) -th column signal. Means for dividing and separating, means for detecting the complementary code added by the transmitter from the separated signal sequence, and cyclic permutation in the signal system so that this bit is output to the channel position added by the transmitter. Give And means for outputting an output signal of a desired m column, a digital signal communication method, comprising the means for protecting the synchronization. 2. A digital signal communication system comprising means for synchronously transmitting a digital signal from a transmitting device to a receiving device via a transmission line, wherein the transmitting device inputs input signals of a plurality of m columns in parallel. Means for converting the signal speed to (m + 1) / m times, means for adding a "high" level mark signal to the speed-converted input signal of the m-th column to make the signal of the (m + 1) -th column,
Means for time-division-multiplexing the signals of the (+1) th column into one channel, summing the signals, and outputting the sum as a transmission signal to the transmission path, wherein the receiving device obtains the difference between the received transmission signals and further (m + 1) Means for time division into channel signals, means for detecting the mark signal added on the transmission side from the separated signal sequence, and a signal system for outputting this bit to the channel position added by the transmitter. A digital signal communication system, characterized in that it is provided with means for applying a cyclic permutation to, and outputting a desired m-column output signal, and means for protecting synchronization. 3. A digital signal communication system comprising means for synchronously transmitting a digital signal from a transmitting device to a receiving device via a transmission line, wherein the transmitting device receives input signals of a plurality of m columns in parallel. A means for converting the signal speed to (m + 1) / m times, and a 1-bit complementary code of the input signal or a "high" level mark signal is added to the speed-converted m-column signal according to the mode switching signal. In addition, means for generating a signal of the (m + 1) th column, and the generated signal of the (m + 1) th column are time-division-multiplexed into one channel, and the sum is obtained as it is or in accordance with the mode switching signal and is transmitted to the transmission line as a transmission signal. And a means for outputting the received transmission signal as it is according to the mode switching signal or by taking a difference and time-division-separating the signal into the (m + 1) -th column. When the means for detecting the auxiliary code or the mark signal added by the transmitting apparatus in accordance with the mode switching signal from the separated signal sequence,
A means for applying a cyclic permutation to the signal system so that this bit is output to the channel position added by the transmitter and outputting a desired m-column output signal as an output signal, and means for protecting synchronization are provided. Digital signal communication system characterized by. 4. The method according to claim 1, wherein m = 8n (n is a natural number).
Alternatively, the digital signal communication system according to claim 2 or claim 3.