JPH06188267A - Manufacture of thin film transistor array - Google Patents
Manufacture of thin film transistor arrayInfo
- Publication number
- JPH06188267A JPH06188267A JP33877092A JP33877092A JPH06188267A JP H06188267 A JPH06188267 A JP H06188267A JP 33877092 A JP33877092 A JP 33877092A JP 33877092 A JP33877092 A JP 33877092A JP H06188267 A JPH06188267 A JP H06188267A
- Authority
- JP
- Japan
- Prior art keywords
- film
- glass substrate
- metal
- metal film
- tft
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
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- 239000010409 thin film Substances 0.000 title claims description 11
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- 239000002184 metal Substances 0.000 claims abstract description 64
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 108010025899 gelatin film Proteins 0.000 claims abstract description 33
- 239000000463 material Substances 0.000 claims abstract description 29
- 238000000034 method Methods 0.000 claims abstract description 21
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- 238000007747 plating Methods 0.000 claims description 7
- 238000009833 condensation Methods 0.000 claims description 4
- 230000005494 condensation Effects 0.000 claims description 4
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- 238000009413 insulation Methods 0.000 claims description 3
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- 238000009713 electroplating Methods 0.000 abstract description 4
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- 239000004431 polycarbonate resin Substances 0.000 abstract description 3
- 239000013078 crystal Substances 0.000 abstract description 2
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- 229910052715 tantalum Inorganic materials 0.000 description 4
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
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- 230000007423 decrease Effects 0.000 description 2
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Landscapes
- Liquid Crystal (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、液晶ディスプレイやイ
メージセンサなどに使われる薄膜トランジスタアレイの
性能向上に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improving the performance of thin film transistor arrays used in liquid crystal displays, image sensors and the like.
【0002】[0002]
【従来の技術】アクティブマトリックス駆動液晶ディス
プレイは、表示品位が高いことから液晶ディスプレイの
本流となりつつある。しかしながら、従来の液晶駆動デ
ィスプレイにおいては、大面積かつ大容量の表示を行う
ためにさまざまな問題があった。2. Description of the Related Art Active matrix drive liquid crystal displays are becoming the mainstream of liquid crystal displays because of their high display quality. However, the conventional liquid crystal drive display has various problems in order to display a large area and a large capacity.
【0003】図5に、従来の液晶ディスプレイに使用さ
れる薄膜トランジスタ(TFT)の断面構造を示す。同
図において、1はガラス基板、41はゲート電極、42
はゲート絶縁膜、43は画素電極そして44は非晶質シ
リコン層である。また、45は画素電極43に接続され
るドレイン電極であり、46は非晶質シリコン層44と
ドレイン電極45とのオーミック接触を取るためのn型
非晶質シリコン層である。さらに、47は外部から画像
信号を送り込むソース電極であり、n型非晶質シリコン
層48を介して非晶質シリコン層44に接続される。ま
た、ソース電極47は電極49に接続される。この電極
49は、各画素のTFTへ画像信号を給電する配線であ
る。FIG. 5 shows a sectional structure of a thin film transistor (TFT) used in a conventional liquid crystal display. In the figure, 1 is a glass substrate, 41 is a gate electrode, and 42.
Is a gate insulating film, 43 is a pixel electrode, and 44 is an amorphous silicon layer. Further, 45 is a drain electrode connected to the pixel electrode 43, and 46 is an n-type amorphous silicon layer for making an ohmic contact between the amorphous silicon layer 44 and the drain electrode 45. Further, 47 is a source electrode for sending an image signal from the outside, which is connected to the amorphous silicon layer 44 through the n-type amorphous silicon layer 48. Further, the source electrode 47 is connected to the electrode 49. The electrode 49 is a wiring for supplying an image signal to the TFT of each pixel.
【0004】図6にTFTアレイの平面図を示す。同図
において、51はゲート選択線である。前記ゲート選択
線51は、図5のゲート電極41と電気的に接続されて
おり、該ゲート電極41とゲート選択線51は同一材料
からなる金属薄膜で形成されている。なお、50はTF
Tを示している。FIG. 6 shows a plan view of the TFT array. In the figure, 51 is a gate selection line. The gate selection line 51 is electrically connected to the gate electrode 41 of FIG. 5, and the gate electrode 41 and the gate selection line 51 are formed of a metal thin film made of the same material. 50 is TF
T is shown.
【0005】また、図6のTFTアレイを動作させるに
は、ゲート選択線51に選択電圧を印加し、この印加に
より一本のゲート選択線51に接続された全てのTFT
50がオン状態となる。このタイミングで電極49に画
素信号電圧を印加すると、電圧が画素電極43に書き込
まれる。次のタイミングにて隣接するゲート選択線51
に選択電圧が印加されると、同様に画像信号電圧がTF
Tに接続された画素電極43に書き込まれる。これらを
繰り返すことにより、TFTアレイの上に形成された液
晶の配向を制御して画像の表示ができる。In order to operate the TFT array of FIG. 6, a selection voltage is applied to the gate selection line 51, and by this application, all the TFTs connected to one gate selection line 51.
50 is turned on. When the pixel signal voltage is applied to the electrode 49 at this timing, the voltage is written in the pixel electrode 43. Adjacent gate selection line 51 at the next timing
When the selection voltage is applied to the
It is written in the pixel electrode 43 connected to T. By repeating these, the orientation of the liquid crystal formed on the TFT array can be controlled to display an image.
【0006】[0006]
【発明が解決しようとする課題】しかしながら、液晶デ
ィスプレイの表示容量が大きくなるにつれてさまざまな
問題が発生してきた。これら問題は以下に要約される。However, various problems have occurred as the display capacity of liquid crystal displays has increased. These issues are summarized below.
【0007】(1)すなわち、表示容量が大きくなると
必然的に一画素に割り当てられる面積が小さくなる。こ
れに対し、TFT50、ゲート選択線51、画像給電線
の占める面積は余り小さくできないことから、開口率
(全体の面積に占める表示可能な面積の割合)が小さく
なる。従って、照明光の利用効率が減少し、表示画像が
暗くなってしまう。(1) That is, as the display capacity increases, the area allocated to one pixel inevitably decreases. On the other hand, since the area occupied by the TFT 50, the gate selection line 51, and the image power supply line cannot be made very small, the aperture ratio (the ratio of the displayable area to the entire area) becomes small. Therefore, the utilization efficiency of the illumination light is reduced, and the displayed image becomes dark.
【0008】(2)また、開口率向上のためゲート選択
線51の幅を狭くすると、ゲート選択線51の抵抗値が
上昇し、寄生容量との関係からゲート選択線51の応答
速度が低下してしまう。従って、TFT50のゲートに
かかる電圧が不十分となり、画像信号の画素電極書き込
みが不十分となる。この現象は、大面積大容量表示で特
に問題となる。この問題を解決するための方法として、
配線薄膜の膜厚を厚くすることが考えられる。しかしな
がら、膜厚を厚くすると図5に示すゲート電極41の膜
厚が厚くなり段差が大きくなってしまう。このため、段
差部で短絡を誘発しTFTの製造工程上問題となる。(2) If the width of the gate selection line 51 is narrowed to improve the aperture ratio, the resistance value of the gate selection line 51 increases, and the response speed of the gate selection line 51 decreases in relation to the parasitic capacitance. Will end up. Therefore, the voltage applied to the gate of the TFT 50 becomes insufficient, and the pixel electrode writing of the image signal becomes insufficient. This phenomenon becomes a particular problem in a large area and large capacity display. As a method to solve this problem,
It is conceivable to increase the thickness of the wiring thin film. However, if the film thickness is made thick, the film thickness of the gate electrode 41 shown in FIG. 5 becomes thick and the step becomes large. For this reason, a short circuit is induced in the step portion, which becomes a problem in the manufacturing process of the TFT.
【0009】ところで、従来のTFTアレイにおいて、
ゲート電極41としてTa金属材料を用いた場合、その
膜厚は通常0.3μm、幅10μm程度である。また、
Ta自体の電気抵抗率は12μΩ/cm、すなわち0.
4Ω/□であるから、配線抵抗は40Ω/mm程度であ
る。By the way, in the conventional TFT array,
When a Ta metal material is used for the gate electrode 41, its film thickness is usually 0.3 μm and its width is about 10 μm. Also,
The electric resistivity of Ta itself is 12 μΩ / cm, that is, 0.
Since it is 4Ω / □, the wiring resistance is about 40Ω / mm.
【0010】従来の一辺30cm程度の大型液晶ディス
プレイにおいて、基板終端までの抵抗値は12kΩ程度
である。この抵抗値で1000pFの寄生容量を駆動す
ることを考えた場合、RC時定数は12μsである。従
って、RC時定数のみで立ち上がり、立ち下がりを含め
て24μsを必要とする。一方、テレビジョン方式から
1ライン当たり30μs以下で書き込みを終了させねば
ならない。画像データの完全な書き込みには、少なくと
もRC時定数の2〜3倍以上の時間、即ち75μs程度
の時間が必要である。従って、ゲート選択線51の給電
点の近傍では十分なデータ書き込みが可能であっても、
ゲート選択線51の終端近傍においてはデータ書き込み
が不十分となり、この結果、画像品質を低下させてい
た。In a conventional large-sized liquid crystal display having a side length of about 30 cm, the resistance value up to the end of the substrate is about 12 kΩ. When considering driving a parasitic capacitance of 1000 pF with this resistance value, the RC time constant is 12 μs. Therefore, it takes 24 μs including the rise and fall only with the RC time constant. On the other hand, from the television system, writing must be completed in 30 μs or less per line. Complete writing of image data requires at least 2-3 times the RC time constant, that is, about 75 μs. Therefore, even if sufficient data can be written near the feeding point of the gate selection line 51,
In the vicinity of the end of the gate selection line 51, data writing becomes insufficient, resulting in deterioration of image quality.
【0011】本発明は、かかる従来の問題点を解決する
ためになされたものであって、製造工程及び大面積化が
容易であり、大面積大容量表示が可能でしかも段差の無
いTFTアレイの製造方法を提供することを目的とす
る。The present invention has been made in order to solve the above-mentioned conventional problems, and a manufacturing process and a large area can be easily performed, a large area and a large capacity display can be performed, and a stepless TFT array. It is intended to provide a manufacturing method.
【0012】[0012]
【課題を解決するための手段】すなわち本発明の第1の
製造方法は、絶縁基板表面に、加水分解・縮合により絶
縁物を形成する特性のゲル膜を塗布した後、少なくとも
凸部の先端部分に金属膜を有する型材の凸部側をゲル膜
表面に押し当て、この状態のままゲル膜を乾燥・熱処理
して前記絶縁基板上の表面に凹部及び凹部の底面に金属
膜を有する絶縁膜を形成し、続いて凹部の金属膜上にめ
っき法を用いて別の金属膜を絶縁膜表面と略面一に形成
し、さらに前記絶縁基板上にTFTを形成することによ
り達成される。[Means for Solving the Problems] That is, according to a first manufacturing method of the present invention, after a gel film having a property of forming an insulator by hydrolysis / condensation is applied to the surface of an insulating substrate, at least the tip portion of the convex portion is applied. The convex side of the mold material having the metal film is pressed against the gel film surface, and in this state, the gel film is dried and heat-treated to form a concave part on the surface of the insulating substrate and an insulating film having a metal film on the bottom surface of the concave part. This is accomplished by forming another metal film on the metal film of the recess by using a plating method so as to be substantially flush with the surface of the insulation film, and then forming a TFT on the insulation substrate.
【0013】また、本発明の第2の製造方法は、絶縁基
板表面に、加水分解・縮合により絶縁物を形成する特性
のゲル膜を塗布した後、ゲル膜表面に金属膜からなる凸
部を有する型材の凸部側を押し当て、この状態のままゲ
ル膜を乾燥・熱処理して前記絶縁基板上に絶縁膜を形成
し、続いて型材を絶縁膜から除去することにより金属膜
を絶縁膜に残存させ、さらに前記絶縁基板上にTFTを
形成することにより達成される。In the second manufacturing method of the present invention, a gel film having a property of forming an insulator by hydrolysis / condensation is applied to the surface of an insulating substrate, and then a convex portion made of a metal film is formed on the surface of the gel film. The convex side of the mold material is pressed, the gel film is dried and heat-treated in this state to form an insulating film on the insulating substrate, and then the mold material is removed from the insulating film to transform the metal film into an insulating film. This is achieved by leaving the TFT and forming a TFT on the insulating substrate.
【0014】図1は、本発明の製造方法により作成され
たTFTアレイの要部断面図である。同図において、1
は絶縁基板の一例としてのガラス基板であって、2はガ
ラス基板1上においてその表面部分が絶縁膜3と面一に
形成された金属配線である。また、前記金属配線2及び
絶縁膜3表面に形成されるTFT12の構造は、従来の
TFTの構造とほぼ同様である。すなわち、金属配線2
及び絶縁膜3上にゲート絶縁膜4が形成され、該ゲート
絶縁膜4上の一部に画素電極5及び非晶質シリコン層6
が形成され、該非晶質シリコン層6上には該非晶質シリ
コン層6とドレイン電極9とのオーミック接触を取るた
めのn型非晶質シリコン層7が形成されている。また、
10は外部から画素信号を送り込むソース電極であり、
n型非晶質シリコン層8を介して非晶質シリコン層6に
接続されている。なお、11は保護層である。FIG. 1 is a cross-sectional view of a main part of a TFT array manufactured by the manufacturing method of the present invention. In the figure, 1
Is a glass substrate as an example of an insulating substrate, and 2 is a metal wiring whose surface portion is formed flush with the insulating film 3 on the glass substrate 1. The structure of the TFT 12 formed on the surfaces of the metal wiring 2 and the insulating film 3 is almost the same as the structure of the conventional TFT. That is, the metal wiring 2
And the gate insulating film 4 is formed on the insulating film 3, and the pixel electrode 5 and the amorphous silicon layer 6 are formed on a part of the gate insulating film 4.
And an n-type amorphous silicon layer 7 for making ohmic contact between the amorphous silicon layer 6 and the drain electrode 9 is formed on the amorphous silicon layer 6. Also,
Reference numeral 10 is a source electrode for sending a pixel signal from the outside,
It is connected to the amorphous silicon layer 6 through the n-type amorphous silicon layer 8. In addition, 11 is a protective layer.
【0015】前記ガラス基板1としては、ソーダライム
ガラス、石英ガラス、ほう珪酸ガラス等を用いることが
できる。金属配線2としては、Ta、Al、Crまたは
Cu等の低抵抗率の金属材料を用いることができる。As the glass substrate 1, soda lime glass, quartz glass, borosilicate glass or the like can be used. As the metal wiring 2, a low-resistivity metal material such as Ta, Al, Cr, or Cu can be used.
【0016】次に、図2、図3及び図4を参照しながら
本発明の製造方法について説明する。図2は、本発明の
第1の方法による製造工程を示す一部断面図、また図3
及び図4は本発明の第2の方法による製造工程を示す一
部断面図である。Next, the manufacturing method of the present invention will be described with reference to FIGS. 2, 3 and 4. 2 is a partial cross-sectional view showing a manufacturing process according to the first method of the present invention, and FIG.
4 and FIG. 4 are partial cross-sectional views showing the manufacturing process according to the second method of the present invention.
【0017】第1の製造方法について説明すると、まず
ガラス基板1上にゲル膜20を塗布しておく(図3
a)。一方、凸部22を有する型材(スタンパー)21
を金属材料を含有するペースト状物23に接触させて
(同図b)、前記型材21の凸部22の先端部分に前記
ペースト状物23を付着させる(同図c)。次に、前記
型材21の凸部22を前記ゲル膜20表面に押し当てる
(同図d)。この状態のまま、前記ガラス基板1を30
〜80℃で15〜30分程度、予備的な熱処理を行い、
ゲル膜20表面に凹部24を形成すると共に該凹部24
の底面に金属膜23を形成する。The first manufacturing method will be described. First, the gel film 20 is applied on the glass substrate 1 (see FIG. 3).
a). On the other hand, a mold material (stamper) 21 having a convex portion 22
Is brought into contact with a paste-like material 23 containing a metal material (FIG. 2B), and the paste-like material 23 is attached to the tip end portion of the convex portion 22 of the mold material 21 (FIG. 2C). Next, the convex portion 22 of the mold material 21 is pressed against the surface of the gel film 20 (FIG. 8D). In this state, the glass substrate 1 is
Perform preliminary heat treatment at ~ 80 ° C for about 15-30 minutes,
The recess 24 is formed on the surface of the gel film 20 and the recess 24 is formed.
A metal film 23 is formed on the bottom surface of the.
【0018】前記ゲル膜20としては、例えばアルコキ
シル基を含有する有機金属化合物を含む原料溶液を加水
分解、縮合によりゲル化させたものを用いることができ
る。また、前記型材21の形状は、前記ゲル膜20に所
望の凹部24を形成できる凸部22を有するものであれ
ば形状や材質等は限定されず、例えばニッケル製あるい
はポリカーボネート樹脂製の型材21を用いることがで
きる。As the gel film 20, for example, a gel film obtained by hydrolyzing and condensing a raw material solution containing an organometallic compound containing an alkoxyl group can be used. The shape of the mold material 21 is not limited as long as it has a convex portion 22 capable of forming a desired concave portion 24 on the gel film 20, and for example, a mold material 21 made of nickel or polycarbonate resin is used. Can be used.
【0019】また、前記ゲル膜20表面に凹部24を形
成するに際し、前記型材21における型深さ(凸部22
の高さ)を、前記ゲル膜20の厚みに比較して同一深さ
とするか、あるいはそれよりも浅くすることが好まし
い。When forming the concave portion 24 on the surface of the gel film 20, the mold depth of the mold material 21 (the convex portion 22) is formed.
It is preferable that the height of the gel film 20 is equal to or smaller than the thickness of the gel film 20.
【0020】また、前記ペースト状物23を形成する金
属材料は特に限定されず、例えば前述のTa、Al、C
rまたはCu等を用いることができる。前記金属材料を
ペースト状物23中に安定的に均一な分散状態に保つた
めの結着材(バインダー)は、例えばポリエステル樹
脂、エポキシ樹脂、フェノール樹脂、オレフィン、ゴ
ム、アクリル樹脂、ウレタン樹脂またはこれらの2種以
上の組成物等が挙げられる。溶剤についても特に限定さ
れず、使用する樹脂を溶解するものであれば良く、例え
ば炭化水素系溶媒またはハロゲン化炭化水素系溶媒(好
ましくは沸点が50〜200℃のもの、例えばトルエ
ン、シクロヘキサン、酢酸エステル、キシレン等)が挙
げられる。The metallic material forming the paste 23 is not particularly limited, and may be, for example, Ta, Al, C described above.
r or Cu can be used. The binder (binder) for maintaining the metal material in the paste-like material 23 in a stable and uniform dispersion state is, for example, polyester resin, epoxy resin, phenol resin, olefin, rubber, acrylic resin, urethane resin or these. 2 or more types of compositions and the like. The solvent is also not particularly limited as long as it dissolves the resin to be used, for example, a hydrocarbon solvent or a halogenated hydrocarbon solvent (preferably having a boiling point of 50 to 200 ° C., such as toluene, cyclohexane, acetic acid. Ester, xylene, etc.).
【0021】前記各成分を適宜の比率で混合分散し、金
属材料を結着材の官能基と反応させてペースト状物23
を作成する。なお、前記ペースト状物23の粘性は、4
0〜120ポアズ程度が好適である。The above components are mixed and dispersed at an appropriate ratio, and the metallic material is reacted with the functional groups of the binder to form a paste 23.
To create. The viscosity of the paste 23 is 4
About 0 to 120 poise is preferable.
【0022】続いて、前記ゲル膜20から型材21を抜
脱し、さらに前記ガラス基板1を300〜400℃で
0.5〜24時間程度熱処理することにより、該ガラス
基板1上に凹部24を有するガラス体25を得る(同図
e)。Subsequently, the mold material 21 is removed from the gel film 20, and the glass substrate 1 is heat-treated at 300 to 400 ° C. for 0.5 to 24 hours, so that the recess 24 is formed on the glass substrate 1. A glass body 25 is obtained (e in the figure).
【0023】この後、前記凹部24の金属膜23上に金
属膜26を成膜する。成膜法として、高速で成膜できる
めっき法が採用される。前記めっき法であれば、電解め
っき法でも無電解めっき法でも構わない。また、成膜さ
れる金属膜26としてTa、Al、Cr、Cu等の金属
材料を用いることが可能であるが、前記金属膜23との
密着性の良好な金属材料を用いることが望ましい。After that, a metal film 26 is formed on the metal film 23 in the recess 24. As a film forming method, a plating method capable of forming a film at high speed is adopted. The plating method may be either electrolytic plating method or electroless plating method. Moreover, although a metal material such as Ta, Al, Cr, or Cu can be used as the metal film 26 to be formed, it is preferable to use a metal material having good adhesion to the metal film 23.
【0024】なお、前記工程の順序に代えて、前記凹部
24の金属膜23上に金属膜26を成膜した後、前記ガ
ラス基板1を熱処理してガラス体25を得ることもでき
る。Instead of the order of the steps, it is possible to form the metal film 26 on the metal film 23 of the recess 24 and then heat the glass substrate 1 to obtain the glass body 25.
【0025】そしてこの後、金属配線となる前記金属膜
26を形成したガラス体25上にTFTを従来周知の方
法により形成させる。After that, a TFT is formed on the glass body 25 on which the metal film 26 to be the metal wiring is formed by a conventionally known method.
【0026】次に、図3及び図4を参照しながら第2の
製造方法について説明する。Next, the second manufacturing method will be described with reference to FIGS.
【0027】前記第1の製造方法の場合と同様に、まず
ガラス基板1上にゲル膜20を塗布する(図3a、図4
a)。一方、型材21は、ガラス板27、樹脂層28、
及び金属膜29を積層させ(図3b)、フォトリソグラ
フィー法により前記金属膜29を選択的に除去してパタ
ーン化させ、これを凸部としたものを用いることができ
る(図3c)。または、前記樹脂層28上に金属材料を
含有するペースト状物23をパターン状に印刷し(図4
b)、さらにめっき法により前記ペースト状物23を核
として金属膜29からなる凸部を形成したものを用いる
こともできる(図4c)。Similar to the case of the first manufacturing method, first, the gel film 20 is applied on the glass substrate 1 (FIGS. 3a and 4).
a). On the other hand, the mold material 21 includes a glass plate 27, a resin layer 28,
Alternatively, a metal film 29 may be laminated (FIG. 3b), and the metal film 29 may be selectively removed by photolithography to form a pattern, which is used as a protrusion (FIG. 3c). Alternatively, a paste-like material 23 containing a metal material is printed in a pattern on the resin layer 28 (see FIG. 4).
b) In addition, it is also possible to use the one in which the convex portion made of the metal film 29 is formed with the paste-like material 23 as the nucleus by the plating method (FIG. 4c).
【0028】前記樹脂層28は、有機系溶剤(例えばア
セトン、酢酸エチル、塩化エチレン、ギ酸、トルエン
等)に対して溶解可能な樹脂が用いられ、この点でPM
MA(ポリメチルメタアクリレート樹脂)は好適な材料
である。また、前記金属膜29としては、例えば前述の
Ta、Al、CrまたはCu等を用いることができる。The resin layer 28 is made of a resin that is soluble in an organic solvent (eg acetone, ethyl acetate, ethylene chloride, formic acid, toluene, etc.).
MA (polymethylmethacrylate resin) is a suitable material. Further, as the metal film 29, for example, the above-mentioned Ta, Al, Cr or Cu can be used.
【0029】前記型材21の金属膜29側を前記ゲル膜
20表面に押し当て(図3d、図4d)、30〜80℃
で15分程度予備的な熱処理を行う。続いて、ガラス基
板1を有機系溶剤中に浸漬して、型材21の樹脂層28
を溶解させる。そして、ガラス基板1から前記ガラス板
27を除去して、ガラス体25に金属膜29を残存させ
る(図3e、図4e)。この状態で熱処理を行い、ガラ
ス基板1上にガラス体25を得る。熱処理時間及び温度
は、前記第1製造方法の場合と同様の範囲である。な
お、前記型材21においては、ガラス板27を省略して
樹脂層28及び金属膜29の二層とすることも可能であ
る。The metal film 29 side of the mold material 21 is pressed against the surface of the gel film 20 (FIGS. 3d and 4d), 30 to 80 ° C.
Then, preliminary heat treatment is performed for about 15 minutes. Then, the glass substrate 1 is immersed in an organic solvent to form the resin layer 28 of the mold material 21.
Dissolve. Then, the glass plate 27 is removed from the glass substrate 1 to leave the metal film 29 on the glass body 25 (FIGS. 3e and 4e). Heat treatment is performed in this state to obtain the glass body 25 on the glass substrate 1. The heat treatment time and temperature are in the same range as in the case of the first manufacturing method. In the mold material 21, the glass plate 27 may be omitted and the resin layer 28 and the metal film 29 may be formed into two layers.
【0030】また、金属膜29表面が前記ガラス体25
表面に比較して凹んだ状態で形成された場合は、さらに
前記金属膜29表面にめっき法により金属膜29を成膜
してガラス体25表面とを平滑化させることができる。
あるいは、金属膜29表面が前記ガラス体25表面に比
較して突出して形成された場合は、前記金属膜29表面
を研磨して、金属膜29表面とガラス体25表面を平滑
化させることもできる。The surface of the metal film 29 is the glass body 25.
When it is formed in a recessed state as compared with the surface, a metal film 29 can be further formed on the surface of the metal film 29 by a plating method to smooth the surface of the glass body 25.
Alternatively, when the surface of the metal film 29 is formed so as to project from the surface of the glass body 25, the surface of the metal film 29 may be polished to smooth the surface of the metal film 29 and the surface of the glass body 25. .
【0031】そしてこの後、金属配線となる前記金属膜
を形成したガラス体上にTFTを従来周知の方法により
形成させる。After that, a TFT is formed on the glass body on which the metal film to be the metal wiring is formed by a conventionally known method.
【0032】[0032]
【作用】本発明は、TFTに電極接触を取るための金属
配線となる金属膜が絶縁基板表面に埋設されており段差
が無いため、金属配線に短絡を生じることがなく、また
金属配線の断面積を大きく取ることができる。従って、
金属配線の抵抗値を大きく低減させることが可能とな
り、金属配線の内部寄生抵抗により発生するゲート線伝
播遅延の問題を解決できる。また、絶縁基板表面が平滑
であるため、絶縁基板へのTFT形成及び結合効率が向
上する。According to the present invention, since the metal film serving as the metal wiring for making electrode contact with the TFT is embedded in the surface of the insulating substrate and there is no step, the metal wiring is not short-circuited and the metal wiring is disconnected. A large area can be taken. Therefore,
It is possible to greatly reduce the resistance value of the metal wiring, and it is possible to solve the problem of gate line propagation delay caused by the internal parasitic resistance of the metal wiring. Further, since the surface of the insulating substrate is smooth, the TFT formation and the coupling efficiency on the insulating substrate are improved.
【0033】さらに、金属配線の抵抗値を一定として幅
を変化させた金属配線を形成させることもでき、開口率
の向上に寄与できる。Furthermore, it is also possible to form metal wirings having different widths while keeping the resistance value of the metal wiring constant, which can contribute to the improvement of the aperture ratio.
【0034】[0034]
【実施例】(実施例1)まず、ポリカーボネート樹脂製
のスタンパー21の凸部22をTaを含有するペースト
状物23に接触させ、前記凸部22の先端部分にペース
ト状物23を約5μm厚さに付着させた。一方、ソーダ
ライムガラス基板1の表面にゾル−ゲル法により形成し
たゲル膜20を塗布した。Example 1 First, the convex portion 22 of a stamper 21 made of a polycarbonate resin was brought into contact with a paste-like material 23 containing Ta, and the paste-like material 23 was formed on the tip portion of the convex portion 22 to a thickness of about 5 μm. Made to adhere to On the other hand, the gel film 20 formed by the sol-gel method was applied to the surface of the soda lime glass substrate 1.
【0035】スタンパー21の凸部22側をゲル膜20
表面に押し当て、この状態でガラス基板1を60℃で3
0分間熱処理した。この後、スタンパー21を抜脱した
ところ、ゲル膜20表面に凹部24が形成されており、
この凹部24の底面にはTa膜23が形成されていた。
さらに、このガラス基板1を350℃で15分間熱処理
して、ガラス基板1上にガラス体25を形成させた。The protrusion 22 side of the stamper 21 is attached to the gel film 20.
Press on the surface, and in this state the glass substrate 1 at 60 ° C for 3
Heat treatment was performed for 0 minutes. After that, when the stamper 21 was removed, a recess 24 was formed on the surface of the gel film 20,
The Ta film 23 was formed on the bottom surface of the recess 24.
Further, this glass substrate 1 was heat-treated at 350 ° C. for 15 minutes to form a glass body 25 on the glass substrate 1.
【0036】次に、電解めっき法を用いて前記凹部24
にTa膜26を結晶成長させた。さらに、前記結晶成長
させたTa膜26表面を研磨して、該ガラス体25表面
とTa膜26表面を平滑化させた。そして、前記ガラス
基板1上にTFTを形成し、前記Ta膜26をゲート配
線及びゲート電極として機能させた。Next, the recess 24 is formed by using an electroplating method.
Then, the Ta film 26 was crystal-grown. Further, the surface of the Ta film 26 on which the crystal was grown was polished to smooth the surface of the glass body 25 and the surface of the Ta film 26. Then, a TFT was formed on the glass substrate 1 and the Ta film 26 was made to function as a gate wiring and a gate electrode.
【0037】(実施例2)まず、ガラス板27上にPM
MA樹脂層28をスピンコートにより2μm厚さに成膜
し、このPMMA樹脂層28上に真空蒸着法を用いてA
l膜29を5μm厚さに成膜した。次いで、フォトリソ
グラフィー法により前記Al膜29を選択的に除去し、
これをスタンパー21の凸部とした。他方、ソーダライ
ムガラス基板1の表面にゾル−ゲル法により形成したゲ
ル膜20を塗布した。Example 2 First, PM is placed on the glass plate 27.
The MA resin layer 28 was formed into a film having a thickness of 2 μm by spin coating, and A was formed on the PMMA resin layer 28 by vacuum deposition.
1 film 29 was formed to a thickness of 5 μm. Then, the Al film 29 is selectively removed by a photolithography method,
This was used as the convex portion of the stamper 21. On the other hand, the gel film 20 formed by the sol-gel method was applied to the surface of the soda lime glass substrate 1.
【0038】前記スタンパー21の凸部側をゲル膜20
表面に押し当て、この状態でガラス基板1を80℃で1
5分間予備的な熱処理をした後、前記ガラス基板1を酢
酸エチル溶液中に浸漬し、この状態で30分間保持する
ことによりPMMA樹脂層28を溶解させた。さらに、
350℃で15分間の熱処理を行い、ガラス化させた。The convex side of the stamper 21 is attached to the gel film 20.
Press on the surface, and in this state, glass substrate 1 at 80 ° C for 1
After performing a preliminary heat treatment for 5 minutes, the glass substrate 1 was immersed in an ethyl acetate solution and kept in this state for 30 minutes to dissolve the PMMA resin layer 28. further,
Heat treatment was performed at 350 ° C. for 15 minutes to vitrify.
【0039】前記ガラス体25には、Al膜29がその
表面をガラス体25表面と略面一に形成されていた。そ
して、前記ガラス基板1上にTFTを形成し、前記Al
膜29をゲート配線及びゲート電極として機能させた。An Al film 29 was formed on the glass body 25 so that its surface was substantially flush with the surface of the glass body 25. Then, a TFT is formed on the glass substrate 1 and the Al
The film 29 was made to function as a gate wiring and a gate electrode.
【0040】(実施例3)まず、2μm厚さのPMMA
樹脂層28上にシルクスクリーン印刷法により、Crを
含有するペースト状物をパターン状に印刷した。次い
で、この印刷パターンを核として、電解めっき法により
印刷パターン上に5μ厚さのCr膜29を成膜した。一
方、ソーダライムガラス基板1の表面にゾル−ゲル法に
より形成したゲル膜20を塗布した。Example 3 First, PMMA having a thickness of 2 μm
A paste-like material containing Cr was printed in a pattern on the resin layer 28 by a silk screen printing method. Next, using this printed pattern as a core, a 5 μm thick Cr film 29 was formed on the printed pattern by electrolytic plating. On the other hand, the gel film 20 formed by the sol-gel method was applied to the surface of the soda lime glass substrate 1.
【0041】前記スタンパー21のCr膜29側をゲル
膜20表面に押し当て、この状態でガラス基板1を80
℃で15分間熱処理した。The Cr film 29 side of the stamper 21 is pressed against the surface of the gel film 20. In this state, the glass substrate 1
Heat treatment was performed at 15 ° C for 15 minutes.
【0042】この後、前記ガラス基板1をアセトン溶液
中に浸漬し、この状態で25分間保持することにより、
PMMA樹脂層28を溶解させた。さらに、350℃で
15分間の熱処理によりガラス化させた。Thereafter, the glass substrate 1 is dipped in an acetone solution and kept in this state for 25 minutes,
The PMMA resin layer 28 was dissolved. Further, it was vitrified by heat treatment at 350 ° C. for 15 minutes.
【0043】前記ガラス体25には、Cr膜29がその
表面をガラス体25表面と略面一に形成されていた。そ
して、前記ガラス基板1上にTFTを形成し、前記Cr
膜29をゲート配線及びゲート電極として機能させた。A Cr film 29 was formed on the glass body 25 so that its surface was substantially flush with the surface of the glass body 25. Then, a TFT is formed on the glass substrate 1 and the Cr
The film 29 was made to function as a gate wiring and a gate electrode.
【0044】[0044]
【発明の効果】以上説明したように、本発明のTFTア
レイにおいては、簡易な製造工程により金属配線となる
金属膜を埋設した絶縁基板を得ることができる。As described above, in the TFT array of the present invention, it is possible to obtain an insulating substrate in which a metal film to be a metal wiring is buried by a simple manufacturing process.
【0045】また、金属配線が絶縁基板表面に埋設され
ているため、金属配線の抵抗を大きく低減させることが
できるとともに段差によるTFTの短絡故障を無くすこ
とができ、大容量、大面積のディスプレイに適用した場
合も金属配線の伝播遅延を低減し、画質劣化を防止でき
る。さらに、縦横比の大きな金属配線を形成することに
より金属配線幅を狭くすることができ、開口率を大きく
とることが可能である。Further, since the metal wiring is embedded in the surface of the insulating substrate, the resistance of the metal wiring can be greatly reduced, and the short circuit failure of the TFT due to the step can be eliminated, so that a large-capacity, large-area display can be obtained. Even when applied, the propagation delay of the metal wiring can be reduced and the image quality deterioration can be prevented. Furthermore, by forming a metal wiring having a large aspect ratio, the width of the metal wiring can be narrowed and the aperture ratio can be increased.
【図1】本発明のTFTの断面構造図FIG. 1 is a sectional structural view of a TFT of the present invention.
【図2】本発明の第1の方法による製造工程を示す一部
断面図FIG. 2 is a partial cross-sectional view showing a manufacturing process according to the first method of the present invention.
【図3】本発明の第2の方法による製造工程を示す一部
断面図FIG. 3 is a partial cross-sectional view showing a manufacturing process according to a second method of the present invention.
【図4】図3の別の実施例を示す一部断面図FIG. 4 is a partial sectional view showing another embodiment of FIG.
【図5】従来のTFTアレイの断面構造図FIG. 5 is a sectional structural view of a conventional TFT array.
【図6】従来のTFTアレイの平面図FIG. 6 is a plan view of a conventional TFT array.
1 ガラス基板 2 金属配線 3 絶縁膜 4 ゲート絶縁膜 5 画素電極 6 非晶質シリコン層 7 n型非晶質シリコン層 8 n型非晶質シリコン層 9 ドレイン電極 10 ソース電極 11 保護膜 12 TFT 1 glass substrate 2 metal wiring 3 insulating film 4 gate insulating film 5 pixel electrode 6 amorphous silicon layer 7 n-type amorphous silicon layer 8 n-type amorphous silicon layer 9 drain electrode 10 source electrode 11 protective film 12 TFT
フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 H01L 21/3205 Continuation of front page (51) Int.Cl. 5 Identification number Office reference number FI technical display area H01L 21/3205
Claims (4)
薄膜トランジスタの製造方法: (A)絶縁基板の表面に、加水分解・縮合により絶縁物
を形成する特性のゲル膜を塗布する工程、 (B)少なくとも凸部の先端部分に金属膜を有する型材
の該凸部側を前記ゲル膜表面に押し当てた後、この状態
で該ゲル膜を乾燥・熱処理して前記絶縁基板上の表面に
凹部及び該凹部の底面に前記金属膜を有する絶縁膜を形
成する工程、 (C)前記凹部底面の金属膜上に、別の金属膜をめっき
法により前記絶縁膜表面と略面一に成膜する工程、 (D)前記(C)工程で得られた絶縁基板上に薄膜トラ
ンジスタを形成する工程。1. A method of manufacturing a thin film transistor, which comprises the following steps: (A) a step of applying a gel film having a property of forming an insulator by hydrolysis and condensation on the surface of an insulating substrate; B) After pressing the convex side of a mold material having a metal film on at least the tip of the convex part against the gel film surface, the gel film is dried and heat-treated in this state to form a concave part on the surface on the insulating substrate. And a step of forming an insulating film having the metal film on the bottom surface of the recess, (C) forming another metal film on the metal film on the bottom surface of the recess by a plating method so as to be substantially flush with the surface of the insulation film. Step (D) A step of forming a thin film transistor on the insulating substrate obtained in the step (C).
薄膜トランジスタの製造方法: (A)絶縁基板の表面に、加水分解・縮合により絶縁物
を形成する特性のゲル膜を塗布する工程、 (B)金属膜からなる凸部を有する型材の該凸部側を前
記ゲル膜表面に押し当てた後、この状態で該ゲル膜を乾
燥・熱処理して前記絶縁基板上に絶縁膜を形成する工
程、 (C)前記型材を前記絶縁膜から除去することにより、
前記金属膜を該絶縁膜に残存させる工程、 (D)前記(C)工程で得られた絶縁基板上に薄膜トラ
ンジスタを形成する工程。2. A method of manufacturing a thin film transistor, which comprises the following steps: (A) a step of applying a gel film having a characteristic of forming an insulator by hydrolysis and condensation on the surface of an insulating substrate; B) A step of forming an insulating film on the insulating substrate by pressing the convex side of a mold material having a convex part made of a metal film against the surface of the gel film and then drying and heat treating the gel film in this state. (C) By removing the mold material from the insulating film,
A step of leaving the metal film on the insulating film; (D) a step of forming a thin film transistor on the insulating substrate obtained in the step (C).
により前記絶縁膜表面と略面一に形成する工程、 を具備してなる請求項2に記載の薄膜トランジスタの製
造方法。3. After the step (C), (C ′) a step of forming another metal film on the metal film so as to be substantially flush with the surface of the insulating film by a plating method. The method of manufacturing a thin film transistor according to claim 2.
記絶縁膜表面と略面一に形成する工程、 を具備してなる請求項2に記載の薄膜トランジスタの製
造方法。4. The step (C) after the step (C), the step of: (C ′) polishing the insulative film surface to form the metal film surface substantially flush with the insulating film surface. Item 3. A method of manufacturing a thin film transistor according to Item 2.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP33877092A JPH06188267A (en) | 1992-12-18 | 1992-12-18 | Manufacture of thin film transistor array |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP33877092A JPH06188267A (en) | 1992-12-18 | 1992-12-18 | Manufacture of thin film transistor array |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH06188267A true JPH06188267A (en) | 1994-07-08 |
Family
ID=18321307
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP33877092A Pending JPH06188267A (en) | 1992-12-18 | 1992-12-18 | Manufacture of thin film transistor array |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH06188267A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100758822B1 (en) * | 2006-04-19 | 2007-09-14 | (재)대구경북과학기술연구원 | High sensitivity field effect transistor type biosensor and manufacturing method thereof |
US20150206767A1 (en) * | 2014-01-21 | 2015-07-23 | Renesas Electronics Corporation | Method of manufacturing semiconductor device |
-
1992
- 1992-12-18 JP JP33877092A patent/JPH06188267A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100758822B1 (en) * | 2006-04-19 | 2007-09-14 | (재)대구경북과학기술연구원 | High sensitivity field effect transistor type biosensor and manufacturing method thereof |
US20150206767A1 (en) * | 2014-01-21 | 2015-07-23 | Renesas Electronics Corporation | Method of manufacturing semiconductor device |
US9735017B2 (en) * | 2014-01-21 | 2017-08-15 | Renesas Electronics Corporation | Method of manufacturing semiconductor device |
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