JPH0618618A - Method for detecting deformed part of waveform in integrated circuit - Google Patents

Abstract

PURPOSE:To recognize a logic element based on the mask pattern of a designed integrated circuit and to make it possible to judge whether the connecting relationship satisfies the characteristic conditions and is carried out properly or not. CONSTITUTION:In the method for detecting the deformed part of the waveform in an integrated circuit, circuit characteristic information, which is determined in association with the size and the connecting relationship of each constituent element of a circuit, is extracted from the designed mask pattern of the integrated circuit. The adequacy with respect to the characteristic allowance value in design is detected. Each element is recognized based on the mask pattern of the integrated circuit, and the element information and the element connecting information are extracted. The circuit characteristic information of each constituent element of the circuit is extracted based on the process constant in manufacturing. Logic-element connecting information is extracted S7 based on the element information and the element connecting information. Whether the connecting relationship of the logic elements is correctly carried out in characteristics or not is detected by collating with the characteristic allowance value in design based on the circuit characteristic information and the logic-element connecting information. Thus, the part, where the unnecessary deformation and delay of the signal waveform occur, is detected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of verifying an integrated circuit mask pattern, and more particularly, to detecting a blunt spot based on a characteristic condition set when designing a mask pattern in consideration of rounding and delay of a signal waveform. The present invention relates to an integrated circuit waveform rounding point detection method.

[0002]

2. Description of the Related Art When designing an integrated circuit, logic / circuit simulation is repeated until the circuit characteristics intended by the designer are obtained, and the function is confirmed to optimize the circuit. For circuit simulation, the designed circuit is R, C
It is represented by an equivalent circuit such as, and is cut at time steps to solve a differential equation. However, the characteristic parameters such as R, L, and C of the element determined at that time are not always guaranteed even after the mask pattern design. For example, it is not guaranteed whether the line width of the Al wiring, the diameter of the contact hole, the margin around the hole, and the like that affect the resistance value comply with the design rules.

Therefore, it is necessary to calculate the characteristic parameter for controlling the circuit operation from the actually designed mask pattern data and verify the characteristic. As the characteristic verification, the circuit element is recognized at the transistor level, and then the connection information between each element is extracted. As a method of extracting connection information,
A method is known in which a graphic operation is performed on graphic information represented by digital data to recognize each element and the phase relationship of its terminal graphic. Next, process constants such as the thickness of the insulating film, the conductivity of the wiring, and the diffusion depth,
A method is known in which a characteristic parameter is calculated from the area and size of each element extracted from a mask pattern, and then converted into circuit simulation input data to perform circuit simulation.

[0004]

In general, a signal propagating through each circuit constituting a mask pattern causes rounding or delay of a signal waveform due to the characteristic of the circuit or a parasitic effect. Therefore, the signal should be designed in consideration of them. There is a need to do. For example,
The circuit that supplies the clock signal to each circuit in the integrated circuit is
It is often realized by a tree-structured circuit with an inverter as a component, but in order to reduce signal delay due to load on the clock signal line, fanout, etc., conditions may be set and designed for them. Many. However, if the characteristics are verified by circuit simulation, LS
With I, the number of elements is enormous, so it is impossible to perform them all at once, and it is unavoidable to perform them partially in sequence, which requires a great deal of time.

The present invention is to solve the above-mentioned problems, and recognizes a logic element from a designed mask pattern,
It is an object of the present invention to provide an integrated circuit waveform rounding point detection method capable of easily determining whether or not the connection relationship of the logic elements satisfies a characteristic condition and is correctly performed.

[0006]

The present invention extracts circuit characteristic information determined from the designed integrated circuit mask pattern in association with the size of each constituent element of the circuit and the connection relationship thereof, and permits the design characteristics. In an integrated circuit waveform rounding detection method for detecting suitability for a value, a step of recognizing each element from the integrated circuit mask pattern to extract element information and element connection information, the element information and element connection information, and manufacturing Extracting circuit characteristic information of each component of the circuit based on the process constant of time, extracting logic element connection information based on the element information and element connection information, the circuit characteristic information and the logic From the element connection information, a step of detecting whether or not the connection relationship of the logic element is characteristically correct, and detecting by checking with the characteristic allowable value in the design. The features.

[0007]

According to the present invention, the circuit characteristic parameter determined in relation to the size of each constituent element of the circuit and its connection relationship is extracted from the integrated circuit mask pattern, and the extracted characteristic parameter is used for rounding or delaying the signal waveform. It is designed to collate with the design characteristic conditions that are set, and to efficiently detect the error location by comparison and collation, and to detect the location where unwanted signal waveform distortion or delay occurs. It becomes possible.

[0008]

EXAMPLES The present invention will be described in detail below based on examples.
FIG. 1 is a diagram for explaining the procedure of an integrated circuit mask pattern verification method according to one embodiment of the present invention, FIG. 2 is a circuit diagram for explaining the present invention, and FIG. 3 is an example of characteristic conditions in design. FIG. 4, FIG. 4 is a diagram for explaining the capture of the mask pattern as digital data, FIG. 5 is a diagram for explaining the element recognition, FIG. 6 is a diagram for explaining the recognition of the phase relationship of each node, and FIG. 7 is a characteristic parameter. FIG. 8 is a diagram illustrating an example, FIG. 8 is a diagram illustrating a method of calculating characteristic parameters, FIG. 9 is a diagram illustrating extraction of logic element connection information, FIG. 10 is a diagram illustrating an example of logic element connection information, and FIG. 11 is FIG. It is a figure which modified the circuit diagram of into consideration the circuit characteristic. First, the circuit is designed in step S1,
An original circuit diagram is created. At this time, in order to obtain the intended circuit characteristics, circuit simulation is performed in step S2 to optimize the circuit. At this time, characteristic conditions for designing the circuit are determined. For example, the signal input from the node a in FIG. 2 becomes the waveform 10 as shown above in the inverter G1. When the signal of this waveform reaches the next-stage inverter G2, the waveform becomes blunt, and the waveform 11 shown above is obtained. The degree of this rounding depends on the characteristics of the drive element in the preceding stage, the wiring length in the subsequent stage, and the fanout.

These conditions are set by the driving capacity depending on the logic element size (gate size), the load capacity attached to the output terminal, the fan-out allowable range, and the like. here,
Taking the case of designing a logic circuit as shown in FIG. 2 as an example, the following description will be made assuming that the characteristic conditions thereof are set as shown in FIG.

In the fan-out shown in FIG. 3, the gate size of the inverter INV1 is used as a reference, and it is defined as an index 1. The gate size is a value that determines the switching speed of the MOS transistor, and is defined by the ratio of the gate length / gate width of the PMOS transistor to the gate length / gate width of the NMOS transistor. Normally, the gate width is constant, so the gate length ratio Is defined by For example, the inverter INV1 shows that the gate size is 20/10 (μmP / N), the output load capacitance is 0.6 to 0.8 pf, and that one or two inverters INV1 can be connected in the subsequent stage. The inverter INV2 has a gate size of 40/2.
0 (μmP / N), output load capacity 0.8 to 1.0 pf,
It is shown that 2 to 4 inverters INV1 can be connected in the subsequent stage. The 2 NAND has a gate size of 20/10 (μmP / N) and an output load capacity of 0.6 to
0.8 pf, 1 or 2 inverters INV1 in the latter stage
Indicates that the connection is possible.

Next, in step S3, a mask pattern is designed based on this original circuit diagram and the characteristic conditions described in FIG. Next, in step S4, the mask pattern is digitized. This is an operation for loading the designed mask pattern into a computer as digital data, and the contour of the pattern is held as vector data for each layer. For example, the mask pattern is shown in FIG.
If it is as shown in FIG. 4A, each pattern is recognized as an aluminum layer 13, a polysilicon layer 14, a diffusion layer 15, a contact hole 16, and a well layer 17 as shown in FIG. 4B. And import.

Next, in step 5, element recognition is performed based on this digital data, and circuit element information and connection information between the circuit elements are extracted. This is performed by performing a graphic operation on the graphic information represented by digital data to recognize each element and the phase relationship of each node (node).

In order to recognize each element, for example, a region consisting of only a specific diffusion layer is recognized as a resistance element,
As shown in FIG. 5A, a region in which a polysilicon layer overlaps a specific diffusion layer is a MOS transistor as shown in FIG. 5B, and an element as shown in FIG. recognize. The phase relationship is recognized by observing the positional relationship between the areas 21, 22, and 23 with respect to the area 20, as shown in FIG. Contained, area 2
2 is not contained, areas 23 intersect
Recognize as (meet).

Then, in step S6, step S
Areas and dimensions of each element and wiring are extracted from the circuit element information extracted in 5 and the connection information between the circuit elements, and the characteristic parameter of each element is calculated in consideration of the process constant. The area / dimension calculation method of the elements and wirings can be calculated by expressing the extracted figure for each circuit element or each wiring obtained by the figure calculation in step S5 as vector data. As a method of calculating the characteristic parameter, for example, the load capacitance of the output terminal can be calculated by the area of the wiring figure to which the terminal is connected, the area of the gate figure of all transistors connected, and the process constant.

FIG. 7 shows an example of calculating the load capacitances at the nodes a to e of the circuit of FIG. FIG. 8A shows a method of calculating the characteristic parameter of the transistor,
The polysilicon layer 31 overlaps the specific diffusion layer 30 and is recognized as a transistor, and the area S of the gate portion 32, the gate peripheral length R, the gate length L = MIN (L1, L2), the gate width W = R- (L1 + L2), and the gate capacitance C = S × (unit capacity value)

FIG. 8 (b) shows a method for calculating the characteristic parameter of the capacitor, which includes the diffusion layer 33 and the polysilicon layer 3.
4 intersect to form the gate portion 35, and the area S of the gate portion 35, the gate peripheral length R, the gate capacitance C = S × (unit capacitance value) is obtained.

FIG. 8C shows a method of calculating characteristic parameters relating to resistance. Both ends of the resistance element 36 are connected to the wiring 37, and the resistance portion area S is the resistance width W = (W1 + W2) / 2 The resistance length L = S / W resistance value R = L / W × (specific resistance)

FIG. 8D shows a method of calculating the characteristic parameter relating to the node parasitic capacitance.
Is formed through the oxide film 40, a capacitance is formed between the wiring pattern and the substrate, and the area S of the wiring pattern is the perimeter of the wiring pattern L Node parasitic capacitance C = S × (unit capacitance / area) + L × (unit Capacity / perimeter)

Then, in step S7, step S
The logic element connection information is extracted based on the element information and the element connection information obtained in 5. As a method of recognizing a logic element from each transistor, a node (PN node) connecting the P-transistor and the N-transistor is used as an output terminal of the logic element, and a transistor group from the node to the power supply VDD and the ground is selected. It is the basis of logic extraction. In FIG. 8A, four transistors from the node connecting the transistor N1 and the transistors P1 and P2 to VDD and GND are recognized as one group.
Next, the combinations of the gate input signals of the transistors on the P side and the N side of the one transistor group are compared with each other, and the transistor groups in which only the same transistors are extracted are set as transistors forming one logic element. A combination of gate input signals of P-type a and N-type b of FIG. 8A (A,
Since B) is the same, P1, P2, N1 and N2 are extracted as a transistor group forming one logic element.

Then, the connection relationship between the P side and the N side is checked to identify the type of logic element. In FIG. 8A, it is assumed that P1 and P2 are connected in parallel, their input signals have an OR (A, B) relationship, N1 and N2 are connected in series, and their input signals are AND. If there is a relationship of (A, B), in the case of CMOS logic, the P type and the N type have a complementary relationship, and in this case, the condition is satisfied,
This corresponds to a NAND gate. The circuit shown in FIG. 8A is represented on the circuit diagram as a symbol as shown in FIG.

The logic element connection information is extracted by checking the connection relationship of the logic elements recognized in this way. At this time, information on the element size (gate size) of the transistor forming one logic element is added. As a result, the conformity with the conditions set as shown in FIG. 3 is examined.
FIG. 10 shows an example of the logic element connection information obtained from the circuit of FIG. 2 by such a method.

Then, in step S8, step S
Based on the characteristic parameter information obtained in step S6, the connection relationship between the logic elements obtained in step S7 is
It is verified whether or not the characteristic condition set in 2 as shown in FIG. 3 is satisfied. This will be described with reference to FIGS. 10 and 11. Each node a, b, c, d, e, f, g of FIG.
h, i, j load capacitances C1, C2, C3, C4, C5,
C6, C7, C8, C9, and C10 are calculated as shown in FIG. 7 in step S6. Then, the gate size of each logic element is judged and it is verified whether or not the condition regarding the driving capability as shown in FIG. 2 in step S2 is satisfied. For example, the inverter G1 has a gate size of 40.
Since it is / 20, it can be seen from FIG. 3 that it is INV2. Since G2 and G6 connected to the subsequent stage have a gate size of 20/10, INV1 and G7 correspond to 2 NAND. Therefore, the fan-out of G1 is 4, which satisfies the condition of FIG. Further, since the load capacitance C3 at the node c, which is the output terminal of G1, also satisfies the condition of FIG. 3, it can be seen that G1 is properly designed.

On the other hand, since the inverter G2 has a gate size of 20/10, it can be seen from FIG. 3 that it is INV1, and G3, G4, and G5 connected to the subsequent stage have a gate size of 20/10. It corresponds to INV1.
Therefore, the fan-out of G2 is 3, which does not satisfy the condition of FIG. Further, the load capacitance C4 at the node d, which is the output terminal of G2, does not satisfy the condition of FIG.
Turns out to be erroneously designed. Thereafter, similarly, it is checked whether or not the connection relation of each logic element satisfies the condition of FIG.

Although the method for verifying the integrated circuit mask pattern according to the present invention has been described above with reference to the embodiment, the present invention is not limited to the method according to this embodiment and can be carried out in various modes other than this. Is.

[0025]

As described above, according to the present invention, the characteristic parameters of the circuit extracted from the integrated circuit mask pattern are collated with the characteristic design conditions set with respect to the waveform rounding and delay of the signal, and The error location can be detected.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a procedure of an integrated circuit mask pattern verification method according to an embodiment of the present invention.

FIG. 2 is a circuit diagram for explaining the present invention.

FIG. 3 is a diagram illustrating an example of a characteristic condition in design.

FIG. 4 is a diagram illustrating the capture of a mask pattern as digital data.

FIG. 5 is a diagram illustrating element recognition.

FIG. 6 is a diagram illustrating recognition of a phase relationship between nodes.

FIG. 7 is a diagram showing an example of characteristic parameters.

FIG. 8 is a diagram illustrating a method of calculating a characteristic parameter.

FIG. 9 is a diagram illustrating extraction of logic element connection information.

FIG. 10 is a diagram showing an example of logic element connection information.

FIG. 11 is a diagram in which the circuit diagram of FIG. 2 is modified in consideration of circuit characteristics.

[Explanation of symbols]

G1 to G8 ... Logic elements, 10, 11 ... Waveform, 13 ... Aluminum layer, 14 ... Polysilicon layer, 15 ... Diffusion layer, 16 ... Contact hole, 17 ... Well layer.

Claims (1)

[Claims] 1. An integrated circuit which extracts circuit characteristic information determined from the designed integrated circuit mask pattern in relation to the size of each constituent element of the circuit and its connection relationship, and detects suitability with respect to a designed characteristic allowable value. In the waveform rounding point detection method, a step of recognizing each element from the integrated circuit mask pattern to extract element information and element connection information, the element information and element connection information, and based on a process constant during manufacturing, Extracting circuit characteristic information of each constituent element of the circuit, extracting logic element connection information based on the element information and element connection information, and the logic element from the circuit characteristic information and the logic element connection information Whether the connection relation of is done correctly characteristically,
A method of detecting a rounded portion of a waveform of an integrated circuit, which comprises a step of detecting the value by comparing with a design allowable value.