JPH061800B2 - Lead frame - Google Patents
Lead frameInfo
- Publication number
- JPH061800B2 JPH061800B2 JP59059455A JP5945584A JPH061800B2 JP H061800 B2 JPH061800 B2 JP H061800B2 JP 59059455 A JP59059455 A JP 59059455A JP 5945584 A JP5945584 A JP 5945584A JP H061800 B2 JPH061800 B2 JP H061800B2
- Authority
- JP
- Japan
- Prior art keywords
- alloy
- lead frame
- precipitation hardening
- clad
- plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】 ［発明の技術分野］ 本発明は半導体用のリードフレームに関する。Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a lead frame for semiconductors.
［発明の技術的背景とその問題点］ 従来から、半導体のリードフレームとしては、４２アロ
イ（４２％Ｎｉ−Ｆｅ合金）のようなＦｅ−Ｎｉ系合金
で形成されたものが知られている。[Technical Background of the Invention and Problems Thereof] Conventionally, as a semiconductor lead frame, there has been known a lead frame formed of a Fe—Ni alloy such as 42 alloy (42% Ni—Fe alloy).
しかしながら、このようなリードフレームは、硬度が高
く折曲げ性に優れてい半面、半導体の高集積化に伴って
要求されてきている熱放散性が充分でなく、また材料価
格が高いという欠点があった。However, such a lead frame has high hardness and excellent bendability, but on the other hand, it has the drawbacks that it does not have sufficient heat dissipation properties required for high integration of semiconductors and that the material cost is high. It was
近年、このようなＦｅ−Ｎｉ系合金に代って値段の安価
なＣｕ合金でリードフレームを形成することが検討され
ているが、Ａｕ線とのボディング性、硬化、折曲げ性、
耐酸化性等のリードフレームに要求されるすべての特性
を満足させるものは得られていない。In recent years, it has been studied to form a lead frame with an inexpensive Cu alloy in place of such an Fe-Ni alloy, but the bonding property with Au wire, hardening, bending property,
No one has been obtained that satisfies all the properties required for a lead frame, such as oxidation resistance.
［発明の目的］ 本発明者らはこのような点に対処して鋭意研究を進めた
結果、従来のＦｅ−Ｎｉ系合金に析出硬化形のＣｕ合金
をクラッドすることにより前述の特性をすべて満足させ
るリードフレームが得れることを見出した。[Purpose of the Invention] As a result of intensive studies conducted by the present inventors in view of such a point, the above-mentioned characteristics are satisfied by clad a conventional Fe-Ni alloy with a precipitation hardening Cu alloy. It has been found that a lead frame can be obtained.
本発明はこのような知見に基づいてなされたもので、Ａ
ｕ線のボンディング性、硬度、折曲げ性、耐酸化性およ
び半田付け性に優れ、熱放散性の高いリードフレームを
提供することを目的とする。The present invention has been made based on these findings.
It is an object of the present invention to provide a lead frame having excellent u-wire bonding property, hardness, bending property, oxidation resistance and solderability, and high heat dissipation property.
［発明の概要］ すなわち本発明は、Ｆｅ−Ｎｉ系合金からなる板状体の
両面に、析出硬化形Ｃｕ合金からなる薄板をクラッドし
てなるクラッド材で形成したことを特徴とするリードフ
レームである。[Summary of the Invention] That is, the present invention is a lead frame characterized in that it is formed of a clad material obtained by clad a thin plate made of a precipitation hardening type Cu alloy on both sides of a plate made of an Fe-Ni alloy. is there.
本発明に用いるクラッド材の一例を第１図に示す。同図
において符号１はＦｅ−Ｎｉ系合金からなる板状体、符
号２はその両面にクラッドされた析出硬化形Ｃｕ合金か
らなる薄板を示す。An example of the clad material used in the present invention is shown in FIG. In the figure, reference numeral 1 denotes a plate-like body made of an Fe-Ni alloy, and reference numeral 2 denotes a thin plate made of a precipitation hardening type Cu alloy clad on both sides thereof.
ここで板状体１を構成するＦｅ−Ｎｉ系合金としては、
例えば４２アロイやコバール（Ｆｅ−Ｎｉ−Ｃｏ合金）
を使用することができる。また、これらの板状体の両面
にクラッドする薄板２は、２０μｍ以上の厚さのものを
使用するのが望ましく、特に析出硬化形のＣｕ合金で構
成した薄板を使用するのが望ましい。Here, as the Fe-Ni-based alloy forming the plate-shaped body 1,
For example, 42 alloy or Kovar (Fe-Ni-Co alloy)
Can be used. Further, it is desirable to use a thin plate 2 having a thickness of 20 μm or more, which is clad on both sides of these plate-like bodies, and it is particularly preferable to use a thin plate composed of a precipitation hardening type Cu alloy.
このような析出硬化形Ｃｕ合金は、Ｃｒ、Ｚｒのような
析出硬化成分元素とＣuを高温で溶解し、連続鋳造法に
より鋳造し、さらに熱間圧延、冷間圧延し、溶体化熱処
理を行なった後、冷間加工を施し、次いで析出硬化処理
を行なうことにより得ることができる。In such a precipitation hardening Cu alloy, precipitation hardening constituent elements such as Cr and Zr and Cu are melted at a high temperature, cast by a continuous casting method, further hot rolled, cold rolled, and solution heat treated. After that, it can be obtained by performing cold working and then performing precipitation hardening treatment.
特にＣｒ０．１〜１重量％とＺｒ０．０５〜０．５重量
％を含むＣｕ合金を４００〜５００℃の温度で析出硬化
処理し、１０００〜１００００個／mm2の密度で０．５
〜５０μｍの析出物を析出させたＣｕ合金は、硬度、折
曲げ性、耐熱性、導電性に優れているので使用すること
が望ましい。In particular, a Cu alloy containing 0.1 to 1% by weight of Cr and 0.05 to 0.5% by weight of Zr is subjected to a precipitation hardening treatment at a temperature of 400 to 500 ° C. and a density of 1,000 to 10,000 pieces / mm 2 and a density of 0.5.
It is desirable to use a Cu alloy in which a precipitate of ˜50 μm is deposited because it has excellent hardness, bendability, heat resistance, and conductivity.
また、上記割合のＣｒ、Ｚｒ以外にＭｇ、Ｓｉ、Ｓｎ、
Ｎｉ、Ｚｎ、Ｍｎ、Ｐ、Ａｇから選ばれた１種または２
種以上の元素を合計量で１重量％以下含有させ、同様に
析出硬化処理を施したＣu合金を用いることもできる。In addition to Cr and Zr in the above proportions, Mg, Si, Sn,
One or two selected from Ni, Zn, Mn, P and Ag
It is also possible to use a Cu alloy that contains not less than 1% by weight of the total of one or more elements and is similarly precipitation hardened.
本発明のリードフレームは、このような析出硬化形Ｃu
合金からなる薄板２を、前述のＦｅ合金からなる板状体
１の両面に全体の厚さが０．１５〜０．２５mmになるよ
うに常法により冷間でクラッドしてなるクラッド材料を
４００〜５００℃の温度で析出硬化処理した後、打抜き
加工等の方法で所定形状に成形することにより得られ、
折曲げ性を始めとする種々の特性に極めて優れている。The lead frame of the present invention is such a precipitation hardening type Cu.
A clad material is prepared by cold-cladding a thin plate 2 made of an alloy on both sides of the plate body 1 made of the Fe alloy by a conventional method so that the total thickness is 0.15-0.25 mm. After precipitation hardening treatment at a temperature of up to 500 ° C, it is obtained by forming into a predetermined shape by a method such as punching,
It has excellent properties such as bendability.
［発明の実施例］ 以下本発明の実施例について記載する。[Examples of the Invention] Examples of the present invention will be described below.
次表に示す組成のＣｕ合金を連続鋳情し、熱間圧延後、
溶体化熱処理を行なった。次いで冷間圧延により厚さ
０．２mmの板状に仕上げた。A Cu alloy having the composition shown in the following table was continuously cast, and after hot rolling,
Solution heat treatment was performed. Then, it was finished by cold rolling into a plate having a thickness of 0.2 mm.
こうして得られた薄板を、４２アロイからなる厚さ０．
１１mmの板状体の両面に常法によりクラッドし、４５０
℃で析出硬化処理を施し、これを打抜き加工し、第２図
に示す形状のリードフレーム３を製造した。The thin plate thus obtained was made of 42 alloy and had a thickness of 0.
Clad on both sides of 11 mm plate by the conventional method,
Precipitation hardening treatment was performed at 0 ° C. and punching processing was performed to manufacture a lead frame 3 having a shape shown in FIG.
次に得られたリードフレームの折曲げ性、表面硬度およ
びＡｕ線とのボンディング性を試験した。結果は同表に
示す通りであった。なお、同表中ボンディング性は第３
図に示すように、実施例のリードフレーム３のチップ搭
載部３ａにダイ接着剤４を介してシリコンウェハー５を
接着し、さらにその上にＡｕ蒸着膜６を形成した後、こ
のＡｕ蒸着膜６とこれに対応するリードフレームの接続
部３ｂをＡｇめっきを施すことなく、Ａｕ線７で直接接
続したときＡｕ線７のＡ部で破断したものを○印とし
た。符号８は樹脂モールド部を示す。なお、Ｂ部で破断
したものはなかった。Next, the bendability, surface hardness and bondability with the Au wire of the obtained lead frame were tested. The results are as shown in the table. The bonding property in the table is third
As shown in the figure, a silicon wafer 5 is adhered to the chip mounting portion 3a of the lead frame 3 of the embodiment via a die adhesive 4, and an Au vapor deposition film 6 is formed on the silicon wafer 5, and then the Au vapor deposition film 6 is formed. And the connection portion 3b of the lead frame corresponding thereto was directly connected by the Au wire 7 without Ag plating, and the broken portion at the A portion of the Au wire 7 was marked with a circle. Reference numeral 8 indicates a resin mold portion. Note that none of the fractures occurred at B part.
［発明の効果］ 以上の説明から明らかなように本発明のリードフレーム
は、Ａｕ線とのボンディング性、表面硬度、折曲げ性に
優れ、しかも耐酸化性、半田付け性および熱放散性が良
好で安価である。 [Advantages of the Invention] As is clear from the above description, the lead frame of the present invention is excellent in the bonding property with the Au wire, the surface hardness, and the bending property, and is also excellent in the oxidation resistance, the solderability and the heat dissipation property. It is cheap.
また、クラッドされたＦｅ−Ｎｉ系合金からなる板状体
を析出硬化形Ｃｕ合金の薄板とは完全な金属結合により
接合されており剥離することがない。In addition, the clad plate-like body made of the Fe-Ni alloy is bonded to the thin plate of the precipitation hardening type Cu alloy by perfect metal bonding and is not peeled off.
第１図は本発明に用いるクラッド材の一例を示す横断面
図、第２図は本発明の一実施例のリードフレームの平面
図、第３図は実施例のリードフレームのＡｕ線とのボン
ディング性の試験方法を示す拡大断面図である。 １…………Ｆｅ−Ｎｉ系合金からなる板状体 ２…………析出硬化形Ｃｕ合金からなる薄板 ３…………リードフレーム ４…………ダイ接着剤 ５…………シリコンウエハー ６…………Ａｕ蒸着膜 ７…………Ａｕ線FIG. 1 is a cross-sectional view showing an example of a clad material used in the present invention, FIG. 2 is a plan view of a lead frame of an embodiment of the present invention, and FIG. 3 is bonding with an Au wire of a lead frame of the embodiment. It is an expanded sectional view which shows the test method of the sex. 1 ………… Plate-like body made of Fe-Ni alloy 2 ………… Thin plate made of precipitation hardening Cu alloy 3 ………… Lead frame 4 ………… Die adhesive 5 ………… Silicon wafer 6 ………… Au evaporated film 7 ………… Au wire
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭56−20135（ＪＰ，Ａ) 特開 昭58−169947（ＪＰ，Ａ) 特開 昭58−141544（ＪＰ，Ａ) 特開 昭54−100257（ＪＰ，Ａ) 実開 昭56−49154（ＪＰ，Ｕ) 特公 昭53−42390（ＪＰ，Ｂ２) ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-56-20135 (JP, A) JP-A-58-169947 (JP, A) JP-A-58-141544 (JP, A) JP-A-54- 100257 (JP, A) Actual development Sho 56-49154 (JP, U) Japanese Patent Sho 53-42390 (JP, B2)
Claims (4)
に、析出硬化形Ｃｕ合金からなる薄板をクラッドしてな
るクラッド材で形成したことを特徴とするリードフレー
ム。1. A lead frame comprising a plate material made of an Fe--Ni alloy and a clad material having a thin plate made of a precipitation hardening type Cu alloy clad on both sides.
てＣｒとＺｒを含有するＣｕ合金である特許請求の範囲
第１項記載のリードフレーム。2. The lead frame according to claim 1, wherein the precipitation hardening Cu alloy is a Cu alloy containing Cr and Zr as precipitation effect elements.
％とＺｒ0.05〜0.5重量％とを含有したものである特許
請求の範囲第２項記載のリードフレーム。3. The lead frame according to claim 2, wherein the precipitation hardening Cu alloy contains 0.1 to 1% by weight of Cr and 0.05 to 0.5% by weight of Zr.
化処理がなされたものである特許請求の範囲第１項乃至
第３項いずれかに記載のリードフレーム。4. The lead frame according to any one of claims 1 to 3, wherein the clad material has been subjected to a precipitation hardening treatment at a temperature of 400 to 500 ° C.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59059455A JPH061800B2 (en) | 1984-03-29 | 1984-03-29 | Lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59059455A JPH061800B2 (en) | 1984-03-29 | 1984-03-29 | Lead frame |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60206053A JPS60206053A (en) | 1985-10-17 |
| JPH061800B2 true JPH061800B2 (en) | 1994-01-05 |
Family
ID=13113791
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59059455A Expired - Lifetime JPH061800B2 (en) | 1984-03-29 | 1984-03-29 | Lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH061800B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2643396B2 (en) * | 1988-12-15 | 1997-08-20 | 日立電線株式会社 | Plate-shaped lead wire soldered to a ceramic capacitor |
| KR0145128B1 (en) * | 1995-04-24 | 1998-08-17 | 김광호 | A innerr lead bonding apparatus having a heat emission pin and inner lead bonding method |
| US9748164B2 (en) * | 2013-03-05 | 2017-08-29 | Nichia Corporation | Semiconductor device |
| JP6499387B2 (en) * | 2013-03-05 | 2019-04-10 | 日亜化学工業株式会社 | Lead frame and light emitting device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5342390B2 (en) | 2009-09-25 | 2013-11-13 | 株式会社岩田レーベル | How to use IC tag |
-
1984
- 1984-03-29 JP JP59059455A patent/JPH061800B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5342390B2 (en) | 2009-09-25 | 2013-11-13 | 株式会社岩田レーベル | How to use IC tag |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60206053A (en) | 1985-10-17 |
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