JPH06177928A - Detector - Google Patents

Abstract

PURPOSE:To obtain a detector with less characteristic deterioration even against distortion in fluctuation with a fast period by generating a replica signal subjected to delay detection so as to generate a differential signal from each difference and discriminating the signal by means of the Viterbi algorithm based on the differential signal. CONSTITUTION:A polyphase modulation signal is inputted to delay detection circuits DD1, DD2 of a detector DET and two multiplexed delay detection signals including the amplitude component and one to 2-symbol delay are outputted. Differential signal detection circuits ER1, ER2 generate a differential signal from the difference between the output of the circuits DD1, DD2 and the two replica signals. The absolute value of the error is squared by square circuits SQ1, SQ2 and a Viterbi algorithm estimate circuit VA executes Viterbi algorithm estimate based thereon and the result of estimate is output as a detection signal. On the other hand, the differential code object series of the circuit VA is branched and inputted to signal conversion circuits CNV1, CNV2, in which the signal series are converted into two synthesis code series and they are inputted to signal estimate circuits EST1, EST2, where replica signals are generated and they are fed to the circuits ER1, ER2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is used in digital wireless communication. The present invention is used for differential detection in polyphase shift modulation. Particularly, the present invention relates to an adaptive equalization technique for a differential detection signal in a variable distortion transmission line. The present invention is suitable for use in mobile communication.

[0002]

2. Description of the Related Art In wireless communication, a transmission path is often a multipath transmission path, and its radio wave propagation is often unstable. Due to the variation of the multipath transmission line characteristic, the level and phase of the carrier component of the received wave greatly change. In mobile communication, in particular, since carrier fluctuations associated with the movement of wireless devices are fast, the signal processing of reception may not be able to follow the changes, and the signal transmission characteristics may be greatly deteriorated. In order to perform highly reliable signal transmission on such a transmission line, a differential detection system is often used as a demodulator.

A conventional example will be described with reference to FIG. FIG. 9 is a block diagram of a conventional circuit. As shown in FIG. 9A, the carrier phase modulated wave input from the input terminal I is amplified by the limiter amplifier LIM-AMP and detected by the delay detector DD. The detected signal is output from the output terminal O. With such a configuration, it is possible to perform highly reliable signal detection even if the phase-modulated wave is randomly phase-modulated due to fluctuations in the transmission path.

[0004]

However, when the transmission speed of the digital signal becomes high, the propagation path difference between the paths in the multipath propagation becomes large, and the direct wave and the delayed wave are superposed, so that the waveform distortion of the received wave occurs. Occurs. Such a transmission line is known as a frequency selective fading transmission line. It is known that in such a distorted transmission line, the delay detection method has a larger deterioration in transmission characteristics than the synchronous detection method. This is because synchronous detection performs detection based on a reference signal that does not include distortion, whereas delayed detection uses a distorted received wave as a reference signal. In addition, FIG.
There is also known a method of equalizing a waveform by adding an equalizer to the output of the differential detector as shown in (a). This method is effective when the linearly superimposed distortion in front of the limiter amplifier is small.

However, when the distortion becomes large, the limiter amplifier makes the amplitude constant and the output of the delay detector is output as it is. Therefore, the delay detection output is also made constant amplitude, and the information about the amplitude component of the distortion is lost. . Therefore, there is a drawback that the equalization performance becomes insufficient.

Therefore, conventionally, a detection method as shown in FIG. 9B has been used in a distorted transmission line. In FIG. 9B, first, the signal from the input terminal I is amplified by the amplifier AGC-AMP with automatic gain adjustment (AGC). The in-phase quadrature quasi-synchronous detector IQD detects a reference signal whose frequency is synchronized but whose phase is not synchronized, and the equalizer EQ is used to suppress deterioration due to distortion of the output. The equalized output is output from the output terminal O. In such an equalization system, the detection is basically based on the synchronous detection, and there is a drawback that the carrier synchronization action cannot follow the phase variation under the fading condition where the variation is fast, and the equalization action becomes insufficient.

The present invention has been made against such a background, and an object of the present invention is to provide a detector which causes less characteristic deterioration even with respect to distortion which fluctuates in a fast cycle.

[0008]

The present invention is a detector,
A feature of the present invention is to provide a delay detection circuit that inputs a multi-phase phase displacement modulation radio signal and outputs N multiple delay detection signals including amplitude components from 1 to N symbol delay in parallel. , N outputs of this differential detection circuit and N
Error signal detection circuit that generates an error signal from the respective differences with the replica signals, and the N output absolute values of the error signal detection circuit are squared and combined to generate one branch metric. , The Viterbi algorithm estimation based on this, outputs the estimation result as a detection signal, and outputs a differential code candidate sequence, and a branch input of the differential code candidate sequence of this Viterbi algorithm estimation circuit. A signal conversion circuit for converting into N composite code sequences, and a signal which is an inner product operation of the N composite code sequence vectors converted by the signal conversion circuit and N variable coefficient vectors to obtain the replica signal. The estimating circuit, the N outputs of the error signal detecting circuit, and the N composite code sequences of the signal converting circuit are branched and input, and the variable coefficient vector is input. It is in place and a coefficient adjusting circuit for controlling the coefficients.

[0009]

The differential code candidate sequence output from the Viterbi algorithm estimation circuit is subjected to signal conversion by the signal estimation circuit to become a synthetic code sequence. By calculating the inner product of the vector of this composite code sequence and the variable coefficient vector, a signal that can be said to be a replica of the transmitted signal can be generated.
An error signal is generated by taking the difference between this replica signal and the multiple delay detection signal output from the detection circuit. A branch metric is generated based on this error signal, Viterbi algorithm estimation is performed, the estimation result is output as a detection signal, and a differential code candidate sequence is output. By taking the difference between the replica signal and the multiple differential detection signal, it is possible to suppress the characteristic deterioration due to the varying distortion in the differential detection.

The variable coefficient vector required to generate the replica signal is controlled by the coefficient adjusting circuit with the error signal and the synthetic code sequence as inputs.

According to the present invention, although the differential detection is performed, an amplitude component is taken into consideration, and a synthetic code sequence is created from a differential code candidate sequence,
It has a function of generating a replica signal and having a function of following a fluctuation of a transmission line, performing a multi-delay detection, performing a soft decision on a multi-delay detection output, and calculating a branch metric to perform a Viterbi algorithm estimation. Is the difference.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of the first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram of the circuit of the first embodiment of the present invention. Here, N of the multiple differential detection is set to 2.

The present invention is a detector. The feature of the present invention is that two multi-delayed detection signals from 1 to 2 symbol delay including an amplitude component by inputting a radio signal of polyphase phase displacement modulation. Differential detection circuit D that outputs each in parallel
D1 and DD2 and the differential detection circuits DD1 and D
Error signal detection circuits ER1 and ER2 that generate error signals from the respective differences between the two outputs of D2 and the two replica signals, and the error signal detection circuits ER1 and ER2.
Of the two output absolute values are combined to generate one branch metric, the Viterbi algorithm is estimated based on this, and the estimation result is output as a detection signal. The output Viterbi algorithm estimation circuit VA, the signal conversion circuits CNV1 and CNV2 that branch-input the differential code candidate sequence of the Viterbi algorithm estimation circuit VA and convert it into two combined code sequences, and the signal conversion circuits CNV1 and CNV2. The signal estimation circuits EST1 and EST2 that perform the inner product operation of the two combined code sequence vectors and the two variable coefficient vectors that have been converted by the above, to obtain the replica signal, and the error signal detection circuit ER.
Two output and signal conversion circuits CNV of 1 and ER2
It is provided with coefficient adjusting circuits ADJ1 and ADJ2 for branching and inputting two composite code sequences of 1 and CNV2 to control the coefficient of the variable coefficient vector.

FIG. 2 is a block diagram showing the configuration of the circuit of the first embodiment of the present invention divided into two parts. The received wave in which the modulated wave and the noise are superimposed is input to the input terminal I. The differential detection signal holding the amplitude component is output from the detector DET to the synchronous quadrature baseband terminals IQ1 and IQ2. A 1-symbol delayed detection signal is output to IQ1, and a 2-symbol delayed detection signal is output to IQ2. Since the differential detection output has a distortion component due to channel distortion, equalization processing is performed by the baseband equalizer BEQ. The equalized detection signal is output to the output terminal O. The linear distortion due to the delayed wave added in the propagation path appears as amplitude distortion and phase distortion in the received signal. When this received signal is amplified by limiter amplification so that the amplitude component is constant, the amplitude distortion is removed, but the phase distortion remains.
Phase distortion is generally nonlinear distortion, and it is difficult to remove it. On the other hand, if both the amplitude component and the distortion component are maintained and amplified, it is easy to remove the distortion by the equalizer included in the first embodiment circuit of the present invention.

With reference to FIG. 3, a detector DET for performing differential detection while maintaining an amplitude component will be described before explaining the equalization operation. FIG. 3 is a diagram showing the configuration of the detector. Three
A specific configuration example of types will be described. In FIG. 3A, the received signal is linearly amplified by the automatic gain adjustment amplifier AGC-AMP and is designated as r _X (t). Center angular frequency is ω
_When r (t) of ₀ is complex-displayed,

[0016]

[Equation 1] Becomes However, Re [] represents a real part. Also, R
(T) is a complex envelope. The amplified signal r (t) is applied to the analog type complex delay detector ADD. The differential detection signal output from the analog complex differential detector ADD is represented by z ₁ (t) = r (t) r ^* (t + T) in the case of 1-symbol differential detection, and is output to the synchronous quadrature baseband terminal IQ1. To be done. Here, * is a complex conjugate, and T is a delay time of the symbol time. z ₁ (t) becomes z ₁ (t) = R (t) R ^* (t + T) (2). However, ω ₀ T is set so that T becomes an integral multiple of 2π.
Is finely adjusted. z ₁ (t) is a complex differential detection signal, the real part of which represents the differential detection in-phase component, and the imaginary part thereof represents the differential detection quadrature component. The same applies to the 2-symbol delay detection signal z ₂ (t). However, in this case, T in the above equation is replaced with 2T.

Other methods will be described below for the detection method of 1-symbol delay detection, but the same method can be applied to 2-symbol delay detection. In FIG.
The amplified r (t) as in (a) is first detected by the in-phase quadrature quasi-synchronous detector IQD, and the complex envelope R (t) is output. Baseband delay detector B using R (t)
In DD, the arithmetic processing represented by equation (2) is performed in the baseband. In FIG. 3C, the limiter amplifier LIM-
The AMP amplifies the received signal r (t) to a constant amplitude. When the amplitude of the amplified signal is 1 and R (t) is represented by R (t) = a (t) exp [jθ (t)], the output of the limiter amplifier is exp [jω ₀ t + jθ (t)]. . When this signal is input to the differential detector DD, the output is expj [θ (t) −θ (t + T)]. On the other hand, since a signal obtained by logarithmically converting the input level is output from the normal limiter amplifier, the amplitude signal a (t) obtained by further logarithmically processing the input level is output as the limiter amplifier LI.
It is assumed that it is output from M-AMP. Amplitude signal a
(T) is used to output the output of the delay detector DD to the amplitude compensator AC
When compensated by, a (t) a (t + T) expj [θ (t) −θ (t + T)] = R (t) R ^* (t + T). This is the same complex differential detection signal Z ₁ (t) as in FIGS. 3 (a) and 3 (b). The first embodiment circuit of the present invention performs equalization processing on the differential detection signals Z ₁ (t) and Z ₂ (t) including the amplitude component of the received wave obtained by such a method.

Next, returning to FIG. 1, an embodiment of the present invention will be described in detail. The differential detection circuits DD1 and DD of FIG.
Reference numeral 2 denotes a delay detector having a 1-symbol delay and a 2-symbol delay, which forms the detector DET of FIG. The 1-symbol delay detector is formed as shown in FIG. Output signal z
₁ (t). The same applies to the 2-symbol delay detector, but the delay time is 2T, and the output is obtained by changing T in the equation (2) to 2T. That is, if the output signal is Z ₂ (t), then Z ₂ (t) = R (t) R ^* (t + 2T). The error signal detection circuits ER1 and ER2 are error signal detection means for outputting an error signal obtained by subtracting a replica signal, which will be described later, from a soft decision of the differential detection signals Z _{1, n} and Z _{2, n} . The error signal is squared in the squaring circuits SQ1 and SQ2 and then combined to obtain 1
Number of branch metrics. The Viterbi algorithm estimation circuit VA estimates the differential code sequence using the branch metric, and the estimation result is output from the output terminal O as a detection signal. This Viterbi algorithm estimation circuit V
The differential code candidate sequence generated in A is converted by the signal conversion circuits CNV1 and CNV2, and a combined code sequence is obtained. The composite code sequence vector obtained from this composite signal sequence is the signal estimation circuit EST in the signal estimation means.
1 and EST2 perform variable product and inner product operation,
Two replica signals are generated by each calculation.

First, the differential detection signal z ₁ (t) is input from the synchronous quadrature baseband terminal IQ1. However, z ₁
(T) is sampled every nT. The timing adjustment of nT is performed by another timing circuit. At this time, when the sampled value is represented by Z _{1, n} = Z ₁ (nT), Z _{1, n} = R _n R ^* _n-1 (3). For R _n = R (nT), one transmission code b _n of the transmission code sequence {b _n } is used in a transmission line without distortion.
It is included. The absolute value of the transmission code b _n is 1. That is, | b _n | ² = 1. When there is a delay distortion, symbols other than b _n are included in R _n. Here, in order to simplify the problem, a transmission code b _n sent by a direct wave and a transmission code b _n-1 sent by a delayed wave received with a delay of one symbol are superimposed on R _n. It has been done. At this time, b _n-1 and b _n-2 are similarly superimposed on R _n-1 . Therefore, Z _{1, n} is obtained by multiplying by the equation (3): a _{1, n} = b _n b ^* _n-1 , a _{2, n} = b _n-1 b ^* _n-2 , a
_{3, n} = b _n b ^* _n-2 , a _{4, n} = b _n-1 b ^* _n-1 (= 1). Therefore, _assuming that the differential code sequence is m _n = b _n b ^* _n-1 , Z _{1, n} = W ^H _{1, n} A _n + ε _{1, n} (4) W ^H _{1, n} = (α _{1, n} α _{2, n} α _{3, n} α _{4, n} ) (5) A ^H _n = (a ^* _{1, n} a ^* _{2, n} a ^* _{3, n} a ^* _{4, n} ) (6) a _{1 , n = m n, a 2} , n = m n-1, a 3, n = m n m n-1, a 4, n = 1 ... a (7). However, α _{1, n} ... α _{4, n} are respectively a _{1, n} ...
It is a coefficient of a4 _{, n} , and is an unknown coefficient that changes depending on the transmission impulse response function of the propagation path. A vector having these elements as an unknown coefficient vector W _{1, n} . A
_n is a composite code sequence vector whose elements are composite code sequences of a _{1, n} ... A _{4, n} . Ε _{1, n in the} equation (4) is an error component other than W _{1, n} ^H A _n in Z _{1, n} . ε _{1, n} becomes an uncorrelated random sequence. In FIG. 1, the differential code candidate sequence {m ′ output from the Viterbi algorithm estimation circuit VA is used.
_n } to the signal conversion circuit CNV using the relational expression (7).
1 generates a ′ _{1, n} ... a ′ _{4, n} , and these are (6)
By substituting it into the equation, the composite code sequence vector _A'n is generated. A variable coefficient vector W ′ _{1, n} consisting of this composite code sequence vector A ′ _n and an unknown variable prepared in the equalizer.
Inner product of the calculated replica signal ^{_{W '1, n H A'}} n in signal estimation circuit EST1. W ′ _{1, n} is estimated by an adaptive algorithm described later so as to have a value close to W _{1, n} .
The error signal e _{1, n} obtained by subtracting the replica signal from the differential detection signal z _{1, n} is output from the error detector ER1.

Next, the 2-symbol differential detection, although the R _n b _n and b _n-1 is the same as is 1 symbol differential detection superimposed, R _n-2 in b _n-2 and b _n-3 Are superimposed. Therefore, Z _{2, n} is C _{1, n} = b _n b ^* _n-2 , C _{2, n} = b _n-1 b ^* _n-3 , C
The sum of the terms _{3, n} = b _n b ^* _n-3 and C _{4, n} = b _n-1 b ^* _n-2 . Therefore, Z _{2, n} = ^WH _{2, n} C _n + ε _{2, n} (8) ^WH _{2, n} = (β _{1, n} β _{2, n} β _{3, n} β _{4, n} ) (9) C _n = (C ^* _{1, n} C ^* _{2, n} C ^* _{3, n} C ^* _{4, n} ) (10) C _{1, n} = m _n m _n-1 , C _{2, n} = m _n-1 m _n-2 , C _{3, n} = m _n m _n-1 m _n-2 , C _{4, n} = m _n-1 (11) However, C _n is a composite code sequence. Therefore, similarly to the 1-symbol differential detection, a replica of the 2-symbol differential detection output can be generated.

Referring to FIG. 4, a signal estimation circuit EST in the signal estimation means for 1-symbol delay and 2-symbol delay.
1 and EST2 will be described. FIG. 4 is a block diagram of the multiple delay detection replica signal generating means of the circuit of the first embodiment of the present invention. These specifically show the equations (7) and (11), respectively.

In the Viterbi algorithm estimating circuit VA, first, the errors e _{1, n} and e _{2, n} are squared of their absolute values | e _{1, n} |
² and | e _{2, n} | ² are calculated by the squaring circuits SQ1 and SQ2. Further, those values are combined and used as a branch metric in the Viterbi algorithm estimation circuit VA. In the Viterbi algorithm estimation circuit VA, some states corresponding to the differential code are defined, and the state transition occurs every time the time point n advances. The state of this transition is called a state trellis. Differential encoding candidate m _'n, m' along the state trellis from the Viterbi algorithm estimation circuit VA corresponding to this transition _n-1 and m _'n-2 is signal conversion circuit CNV
1 and sent to CNV2. Further, the differential code candidate corresponding to the state trellis having the smallest cumulative value of the square of the absolute value of the error is output to the output terminal O as a detection signal.

FIG. 5 shows a trellis diagram of the Viterbi algorithm when the 4-phase PSK is used. FIG. 5 is a diagram showing a trellis diagram of the Viterbi algorithm when 4-phase PSK is used. The state of FIG. 5 is generated by a combination of (m _n-1 , m _n-2 ). m _n-1 and m
_{Since n-2} consists of 4 different differential codes, 4
A trellis of x4 = 16 states is formed. Further, since m _n corresponds to each branch, the Viterbi algorithm selects (m ′ _n , m ′ _n−1 , m ′) as a differential code sequence candidate.
A combination of 3 symbols ( _n-2 ) is output.

When a state transition occurs along this trellis, in the method of performing N = 2 multiple delay detection, an error correction function is provided so that the two delay detection results match within the observation time in the Viterbi algorithm estimation circuit VA. To work. Therefore, it is expected that the characteristics will be improved by the two actions of the simple removal of intersymbol interference by subtracting the replica signal and the error correction in the Viterbi algorithm circuit VA.

The trellis transition of four-phase PSK will be further described. As the transmission line distortion, let us consider the condition that a 1-symbol delayed wave is superimposed on a direct wave. At this time, since the differential detection signals z _{1, n} and Z _{2, n} are defined by m _n , m _n-1 and m _n-2 , the Viterbi algorithm at the time n, the time (n
The differential codes m _n-1 and m _n-2 in -1) may be treated as states. Since each differential code takes four values in QPSK, the number of states is 16. Let these states be S _i , where i = 1 to 1
It is represented by 6. The trellis diagram when the time point shifts from (n-1) to n is as shown in FIG. S at time n
_{At 0} , four transitions from the states S ₀ , S ₁ , S ₂ , S ₃ at time n−1 occur. Let these be branches. Each branch point (n-1) differential encoding candidate m _'n corresponding to the S ₀ in the differential encoding candidate m' _n-1 and m _'n-2 and the time n corresponding to the state of the corresponding Therefore, different differential code candidate sequences {m ' _n-2 ,
_{m 'n-1, m'} n} corresponds. When these are sent to the signal conversion circuits CVN1 and CVN2, a replica signal is generated, the corresponding errors e _{1, n} and e _{2, n} are calculated, and the branch metrics | e _{1, n} | ^{2 of} each branch are calculated.
+ | E _{2, n} | ² is obtained. The sign of this branch metric is inverted and added to the path metric (Accumulat
e: A) to obtain the path metric for the path from. The path metrics are compared (Compare: C) and the largest branch is selected as the surviving path (Select: S).
This selection constrains the four branch candidates to S ₀ at time n. The ACS processing described above is performed for other states at time n. Further, these operations are similarly continued at the time point (n + 1).

In the block diagram of FIG. 1, the error signal e
_{1, n} and composite code sequence _{a '1, n ... a'} 4, by using the _n coefficient adjusting circuit ADJ1 the error | updates the variable coefficient vector A _'n so ² becomes small | e _{1, n} There is. The same applies to e _{2, n} . The adjustment algorithm is LM
S (Least Mean Square), RLS (Recursive Least Squ)
are) and various adaptive algorithms based on the method of least squares are conceivable. For example, in LMS, the product signal e
Α _{1, n} is updated based on _{1, n} a _{1, n} .

[0027] In multiple differential detection as described above, the number of parameters to be estimated, that is, the variable coefficient sequence is the elements of the variable coefficient vector A _'n and C' _n 8
Become individual. If there are many variables to specify, the amount of processing will increase,
Requires a sophisticated processor.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 6 is a block diagram of the circuit of the second embodiment of the present invention. Elements of two vectors, eg α _{1, n} and β
_{1, n} is the preceding wave of R _n , respectively, R _n-1 or R _n-2
Is the product of the delayed wave and the sample time only. These corresponding elements are almost identical if the fluctuations are gradual. Therefore, a method of substituting A _n for C _n is conceivable. In FIG. 6, the signal estimation circuits EST1 and EST2 are provided by one coefficient adjustment circuit ADJ.
The variable coefficient vector of is adjusted. The other parts are the same as those of the first embodiment circuit of the present invention. As a modification of the second embodiment of the present invention, a method of substituting C _n for A _n , 2
A method of updating A _n with the average value of two errors and substituting C _n with A _n can be considered.

In the multiple delay detection, the number of states to be estimated is 16 even at N = 2 as described above, which is considerably large. Therefore, a simplified method will be described as a third embodiment of the present invention. As described above, the differential code candidate sequence (m
_In order to determine the set of _n , m _n-1 , m _n-2 ), the state is set using the past code set (m _n-1 , m _n-2 ), so that there are 16 states. There is. To reduce this situation, m
A method is conceivable in which the state is set by using only the code of _n-1 and four states are set. The trellis diagram at this time is shown in FIG. FIG. 7 is a trellis diagram of the Viterbi algorithm according to the third embodiment of the present invention. 7 ~
5 has the same meaning as in the case of FIG. In this method, since the past history of each state is stored in the path memory for m _n-2 , that value is used.

A computer simulation was conducted to clarify the effects of the second and third embodiments of the present invention. The characteristics specifically obtained by computer simulation are shown in FIG. FIG. 8 is a diagram showing the effects of the second and third embodiments of the present invention. In the two-wave model in which the direct wave and the delayed wave are delayed by one symbol, each component has the maximum Doppler frequency f _D = 0 Hz, 4
This is the E _b / N ₀ characteristic of the average bit error rate (BER) when the Rayleigh variation is 0 Hz and 80 Hz. Here, E _b is the energy per bit and N ₀ is the noise power spectral density. In FIG. 8, the characteristic without an equalizer is shown by a broken line. As shown here, f _D ≤80H
It can be seen that in z, the effect of the equalizer according to the circuit of the third embodiment of the present invention is remarkable. In this simulation, the second embodiment of the present invention and the third embodiment of the present invention, which require a relatively small amount of calculation, were performed. In FIG. 8, the coefficient simplification method is RC
(Recluced Coefficients), and the method in which the number of states is further reduced is shown as PF (Path Feedback).

In the first to third embodiments of the present invention, N of the multiple delay detection has been described as 2. However, N may be 3 or more.

[0032]

As described above, according to the present invention, the characteristic deterioration due to the fluctuating distortion in the differential detection can be greatly suppressed, so that the present invention can be applied to the wireless transmission system such as mobile communication in which the transmission line fluctuates greatly due to fading. This improves the error rate of the received signal.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a circuit according to a first embodiment of the present invention.

FIG. 2 is a block configuration diagram in which the configuration of the circuit of the first embodiment of the present invention is divided into two parts.

FIG. 3 is a diagram showing a configuration of a detector.

FIG. 4 is a configuration diagram of a multiple delay wave replica signal generating means of the circuit according to the first embodiment of the present invention.

FIG. 5 is a diagram showing a trellis diagram of the Viterbi algorithm when four-phase PSK is used.

FIG. 6 is a block configuration diagram of a circuit according to a second embodiment of the present invention.

FIG. 7 is a diagram showing a trellis diagram of the Viterbi algorithm according to the third embodiment of the present invention.

FIG. 8 is a diagram showing effects of the second and third embodiments of the present invention.

FIG. 9 is a block diagram of a conventional circuit.

[Explanation of symbols]

 AC amplitude compensator ADD analog type complex delay detector ADJ, ADJ1, ADJ2 coefficient adjustment circuit AGC-AMP automatic gain adjustment amplifier BDD baseband delay detector BEQ baseband equalizer CNV1, CNV2 signal conversion circuit DET detector DD delay Detector DD1, DD2 Delay detection circuit EQ Equalizer ER1, ER2 Error signal detection circuit EST1, EST2 Signal estimation circuit I Input terminal IQ1, IQ2 Synchronous quadrature baseband terminal IQD In-phase quadrature quasi-synchronous detector LIM-AMP Limiter amplifier O output Terminal SQ1, SQ2 square circuit VA Viterbi algorithm estimation circuit

Claims (1)

[Claims] 1. A differential detection circuit for inputting a radio signal of polyphase shift keying modulation and outputting in parallel N multiple differential detection signals from 1 to N symbol delay including an amplitude component, and the differential detection circuit. An error signal detection circuit that generates an error signal from the respective differences between the N outputs of the circuit and the N replica signals, and the N absolute output values of the error signal detection circuit are 2
A Viterbi algorithm estimation circuit that multiplies and synthesizes to generate one branch metric, performs Viterbi algorithm estimation based on this, outputs the estimation result as a detection signal, and outputs a differential code candidate sequence, and this Viterbi algorithm estimation circuit. A signal conversion circuit for branching the differential code candidate sequence of the algorithm estimation circuit and converting it into N composite code sequences, a vector of the N composite code sequences converted by the signal conversion circuit, and N variable A signal estimating circuit for performing an inner product operation with a coefficient vector to obtain the replica signal, and N variable outputs of the error signal detecting circuit and N synthetic code sequences of the signal converting circuit are branched and input to the variable coefficient vector. And a coefficient adjusting circuit for controlling the coefficient of 1.