JPH06177866A - Clock control method - Google Patents

Abstract

PURPOSE:To prevent occurrence of a data error at the time of switching a system by issuing an alarm when a phase difference between inputted 0 system and 1 system clocks is more than a normal value. CONSTITUTION:The duplexed 0-system and 1-system clocks transmitted from a DCS are received, one clock is selected by a selecting circuit 31 of a selecting part 30, the clock is switched to the other clock when a disconnection abnormal fault occurs at the clock, and supplied to a phase synchronizing oscillator 60 as an in-device reference clock. This selecting part 30 is provided with a phase monitoring means 40 which inputs the 0-system and 1-system clocks, the output clock of the selector 31, and the clock outputted by the phase synchronizing oscillator 60, monitors the phase difference between the inputted 0-system and 1-system clocks, and issues an alarm at the time of detecting that the phase difference is more than the preliminarily set value. Then, the phase monitoring means 40 issues the alarm at the time of detecting that the phase difference between the 0-system and 1-system input clocks is more than the preliminarily set value.

Description

Detailed Description of the Invention

[0001]

The present invention relates to DCS, 0 series, 1
The present invention relates to a clock control method for receiving a clock supplied in a duplexed form with a system and selecting one of them as an in-apparatus reference clock to issue an alarm and create an optimum phase in an apparatus.

In order for the transmission device to perform network synchronization, the normal station device receives a clock from the DCS and creates a reference clock in the device. And, at the time of system switching, it must operate normally without causing a data error.

[0003]

2. Description of the Related Art In the conventional transmission equipment, when operating the equipment, in wiring work for clock supply from the DCS to the transmission equipment at the equipment installation station,
Since one system is not always connected via the same route, the line length of each system is different, and therefore the clocks are supplied with a phase shift, and a data error occurs when the system is switched. There was an occasion.

[0004]

As described above, when the clocks supplied from the DSC to the transmission device are connected via different routes, the 0-system and the 1-system are supplied with their phases being deviated, or However, there is a problem that the clock is supplied to the transmission device while the phase shift exceeding the specified value occurs depending on the wiring work method, and a data error occurs when the system is switched.

An object of the present invention is to solve the above problems and to provide a clock control method for issuing an alarm when the phase difference between the input 0-system clock and the 1-system clock is more than a specified value. .

[0006]

FIG. 1 is a block diagram showing the principle of a clock control method according to the present invention. In the figure, 2 is a transmission device, 30 is a selection unit, 31 and 33 are selection circuits (SE
L), 40 is a phase monitoring means, 50 is a phase control means, 56
Is a variable delay circuit, and 60 is a phase-locked oscillator (PLO).

The present invention is based on the 0 system sent from DCS,
When the clock duplicated with the 1-system is received, one clock is selected by the selection circuit 31 of the selection unit 30 and when a disconnection fault occurs in the clock, the clock is switched to the other clock and the phase is set as the reference clock in the device. A clock control method for supplying and operating the synchronous oscillator 60, comprising:
The 0-system and 1-system input clocks, the output clock of the selector 31 and the clock output from the phase-locked oscillator 60 are input to 0, and the input 0-system and 1-system clock positions are input. A phase monitoring unit 40 is provided which monitors the phase difference and issues an alarm when it detects that there is a phase difference larger than a preset value.

Then, in the phase monitoring means 40, the 0 system,
The object can be achieved by issuing an alarm when it is detected that the phase difference from the input clock of the 1-system exceeds a preset value.

Further, inside the selecting section 30, the 0-system,
The input clock of the 1-system is input, the phase difference is monitored, and when the phase difference is within the preset range, the phase control means 50 for generating the delay amount signal corresponding to the phase difference, and the inside of the apparatus. It is connected to the input side of the 1-system clock of the selection circuit 33 for supplying the in-device reference clock to the phase-locked oscillator 60, receives the delay amount signal from the phase control means 50, and delays the delay amount signal. A variable delay circuit 56 for setting the amount and correcting the phase of the input clock is provided.

Then, in the phase control means 50, the 0 system,
When it is detected that the 1-system input clock has a phase difference within a preset range, the 1-system input clock is delayed so as to correct the phase difference.

[0011]

According to the present invention, the 0-system input clock, the 1-system input clock, the output clock of the selection circuit 31 and the clock output from the phase-locked oscillator 60 are input into the selection unit 30 and the input 0 is input. Phase monitoring means 40 is provided which monitors the phase difference between the system and system 1 clocks and issues an alarm when a phase difference greater than a preset value is detected.

By doing so, when the phase difference between the input clocks of the 0-system and the 1-system is the preset phase difference or more, the phase monitoring means 40 detects the phase difference and issues an alarm. be able to.

Further, the phase control for inputting the 0-system input clock and the 1-system input clock and monitoring the phase difference to generate delay amount data corresponding to the phase difference when the phase difference is within a preset range. The delay amount signal from the phase control means 50 is received by the means 50 and the 1-system input clock side of the selection circuit 33 which supplies the in-device reference clock to the phase-locked oscillator 60 in the device, and corresponds to the delay amount signal. A variable delay circuit 56 for setting the delay amount and delaying the phase of the input clock is provided.

By doing so, when the 0-system input clock and the 1-system input clock have a phase difference within a preset range, the phase control means 50 detects the phase difference and corresponds to the phase difference. Since the delay amount can be set by the variable delay circuit 56, the input clock can be corrected by the phase difference.

[0015]

EXAMPLES Next, examples will be described with reference to FIGS. 2 is an embodiment of a clock control method according to the present invention, and FIG. 3 is an alarm issuing time chart and an optimum phase determination time chart of the embodiment of FIG.

In the figure, the same reference numerals as those in FIG.
10 and 20 are clock receiving units (CREC) 11 and 21
Is a bipolar / unipolar conversion circuit (B / U), 32 is the same selection circuit (SEL) as 31 and 33, 41 and 52 are counters, 42 and 51 are OR circuits, 43 is an AND circuit, 5
3 is a NOT circuit, 54 is a flip-flop circuit, 55 is a decoder, 57 is a fixed delay circuit, and 61 is a phase synchronization circuit (PLL).

The ◯ symbol shown in FIG. 2 indicates the ◯ symbol shown in FIG.
Corresponds to the sign. First, in the first embodiment of the invention for monitoring the phase difference and issuing an alarm, the 0-system and 1-system clocks are sent from the DCS to the CRECs 10 and 20, and the B / Us 11 and At 21, the 64 KHz clock and the 8 KHz frame pulse are separated and sent to the SELs 31, 32, and 33 of the selection unit 30, respectively. SEL
In 31, 32, and 33, normally, the 0 system is used as the active system, and when an abnormality such as a momentary interruption occurs in the 0 system clock, 1
It is designed to switch to the system.

Here, in the OR circuit 42, the 8 KHz signals sent from the 0 and 1 systems of DCS,
The clock generated by the PLL 61, which is formed by the 8 KHz frame pulse currently selected by the SEL 33, is calculated by ORing the frame pulses, for example, 8 MHz.
Then, when the counter 41 is operated to count using this clock, one frame has 1024 bits.

Then, the pulse width of the window is set to 0.
If you set 3 pulses both before and after, the count value ”
1021-1023, 0-3 "is the window allowable range. Therefore, the count values" 1021-1023 "
When a 7-bit width window of 0, 1 to 3 "is created and the count value is within this range, the counter 41 displays
L "is output, and" H "is output in other cases. Then, when a frame pulse out of this window occurs, the AND circuit 43 detects it and outputs" H ". It will give an alarm.

The counter 41 is reset by SEL.
The frame pulse selected as the in-apparatus reference clock output by 31 is used, and this frame pulse is sent to the load terminal of the counter 41 to reset the count value of the counter 41.

A second embodiment of the optimum phase determination according to the present invention is as follows. In the OR circuit 51, 8 KHz, which is sent as a 0-system clock and a 1-system clock from DCS,
The frame pulse is ORed, and the signal is used to load the counter 52 that performs the counting operation using the same clock generated by the PLL 61 as the counter 41 described above.

Then, the counter 51 repeats counting with the count number corresponding to the phase difference. For example, if the phase difference is 3 pulses, "0 to 2" will be repeated.
Then, the sign of the load signal is inverted by the NOT circuit 53, and at the rising edge of the inverted signal, the flip-flop (FF) 54 for inputting the value corresponding to each phase difference of the counter 52 is latched, and it corresponds to the phase difference. Since the address is held, the delay amount can be identified.

Then, in the decoder 55 which inputs the address, a value corresponding to the delay amount is generated and sent to the variable delay circuit 56. The input side of SEL33 is 0
For example, a fixed delay circuit 57 that delays 4 pulses is inserted on the system side, and when there is no phase difference, the variable delay circuit 56 is also delayed by 4 pulses, and the 0 system clock is used as a reference. When the phase of the 1-system clock advances, the delay amount of the variable delay circuit 56 is increased by that amount, and when the phase is delayed, the delay amount is decreased by that amount to eliminate the phase difference.

That is, the decoder 55 generates a signal corresponding to the phase difference of the 1-system clock based on the 0-system clock, but if the delay amount of the fixed delay circuit 57 is 4 pulses,
The signal corresponding to the phase difference generated by the decoder 55 sends the value of the delay amount of four pulses to the variable delay circuit 56 when there is no phase difference. When the 1-system advances by 2 pulses, the value of the delay amount generated by the decoder 55 is set to 6 pulses.

By doing so, the phase difference between the 1-system clock and the 0-system clock input to the SEL 33 can be eliminated.

[0026]

As described above, according to the present invention,
If the phase difference is out of the specified range, notify the maintenance person.In case of the phase difference within the specified range, the phase difference is detected, corrected to the optimum phase, and used as the in-apparatus clock. Switching can be performed without causing a data error, and the reliability of the communication line can be improved.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of a clock control method according to the present invention.

FIG. 2 is an embodiment of a clock control method according to the present invention.

FIG. 3 is a time chart of a clock control method according to the present invention.

[Explanation of symbols]

10, 20 Clock receiver (CREC) 11, 21 Bipolar / unipolar conversion circuit (B /
U) 30 selection unit 31, 32, 33 selection circuit (SEL) 40 phase monitoring means 41, 52 counter 42, 51 OR circuit 43 AND circuit 50 phase control means 53 NOT circuit 54 flip-flop circuit 55 decoder 56 variable delay circuit 57 fixed Delay circuit 60 Phase locked oscillator (PLO) 61 Phase locked circuit (PLL)

Claims (2)

[Claims] 1. A clock duplicated with a 0-system and a 1-system sent from a DCS is received, one clock is selected by a selection circuit (31) of a selection unit (30), and a disconnection abnormality occurs in the clock. When a failure occurs, the clock is switched to the other clock and the phase-locked oscillator (6
0) supplying and operating the input circuit of the 0-system and 1-system, the output clock of the selection circuit (31), and the phase synchronization in the selection unit (30). The clock output from the oscillator (60) is input to
A phase monitoring means (40) is provided for monitoring the phase difference between the input clocks of the system 1 and the system 1, and issuing an alarm when a phase difference more than a preset value is detected. A clock control method which issues an alarm when it is detected that the phase difference between the input clocks of the 1-system and the 1-system is more than a preset value. 2. The selection system (30) according to claim 1, wherein the 0-system and 1-system clocks are input to the inside of the selection unit (30), and the phase difference between the 0-system and 1-system input clocks is monitored in advance. When the phase difference is within the set range, the in-apparatus reference clock is supplied to the phase control means (50) for generating a delay amount signal corresponding to the phase difference and the phase-locked oscillator (60) in the apparatus. Connected to the 1-system clock input side of the selection circuit (33) for receiving the delay amount signal from the phase control means (50), setting the delay amount corresponding to the delay amount signal, and inputting the clock of the input clock. Variable delay circuit that delays the phase (5
6) and a fixed delay circuit (57) for applying a predetermined amount of delay to the 0-system clock input side of the selection circuit (33), and the phase control means (50) inputs the 0-system and 1-system inputs. A clock control method characterized in that, when it is detected that the clock has a phase difference within a preset range, the 1-system input clock is delayed so as to correct the phase difference.