JPH06177754A - Phase locked loop oscillation circuit - Google Patents

Abstract

PURPOSE:To suppress a phase fluctuation of an output at a change of an input reference clock from 'interruption' into 'presence' and vice versa. CONSTITUTION:When an interruption detection circuit 16 detects 'interruption' of a reference clock signal RC, a clock signal MC obtained by applying 1/M frequency division to a standby clock signal BC outputted from a standby oscillator 18 at a 1/M frequency divider circuit 19 is phase-controlled by a clock signal NC obtained by applying 1/N frequency division to an output clock signal OC outputted from a voltage controlled oscillator 13 at a 1/N frequency divider circuit 14. On the other hand, when the reference clock signal RC is normal, a clock signal LC obtained by applying 1/L frequency division to the reference clock signal RC at a 1/L frequency divider circuit 17 is phase-controlled by a clock signal NC obtained by applying 1/N frequency division to an output clock signal OC outputted from the voltage controlled oscillator 13 at the 1/N frequency divider circuit 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase-locked oscillator circuit, and more particularly to a phase-locked oscillator for subordinating an external synchronous network, which switches a reference clock signal to a clock signal of an internal oscillator when a failure occurs in the external synchronous network. Regarding the circuit.

[0002]

2. Description of the Related Art FIG. 4 shows a conventional phase locked oscillator circuit.
Phase-locked oscillator circuit includes an input terminal 11 for inputting a reference clock signal RC having an input frequency f _i, the output frequency f _o
And an output terminal 12 for outputting an output clock signal OC having When the phase-locked oscillator circuit is in the phase-locked state, the output frequency f _o is N (N is an integer of 2 or more) times the input frequency f _i .

The phase locked oscillator circuit has a control voltage C which will be described later.
It has a voltage controlled oscillator 13 that oscillates an output clock signal OC based on V. That is, the voltage controlled oscillator 13 changes the output frequency f _o of the output clock signal OC by the control voltage CV. The output clock signal OC is an N frequency dividing circuit 14
Is supplied to. The N divider circuit 14 outputs the output clock signal OC
The output frequency f _o and N divides and outputs a clock signal NC which divided by N. The clock signal NC divided by N has a frequency equal to the input frequency f _i in the phase locked state.
The clock signal NC divided by N is supplied to one input of the phase comparison circuit 15. The reference clock signal RC is supplied from the input terminal 11 to the other input of the phase comparison circuit 15. The phase comparison circuit 15 compares the phases of the reference clock signal RC and the clock signal NC divided by N, and supplies a voltage representing a phase difference between them as a control voltage CV to the voltage controlled oscillator 13.

[0004]

[0007] Conventional phase-locked oscillation circuit shown in FIG. 4, the output frequency f _o of the output clock signal OC when the reference clock signal RC becomes "cross", the voltage controlled oscillator 13 Oscillation frequency deviation and phase comparison circuit 1
Depends on stability of 5. Therefore, in order to obtain the output frequency f _o of the high precision required a voltage controlled oscillator 13 and a high stability of the phase comparison circuit 15 with high accuracy.

Further, when the reference clock signal RC changes from "off" to "present", the phase of the reference clock signal RC and the phase of the clock signal NC divided by N become indefinite.
Therefore, in the worst case, the output frequency f _{o of the} output clock signal OC output from the voltage controlled oscillator 13 exceeds the allowable value and fluctuates greatly as shown in FIG. In FIG. 5, _fod represents the desired output frequency. In such a situation, there is a problem that a circuit using the output clock signal OC as a clock malfunctions.

Therefore, an object of the present invention is to provide a phase-locked oscillator circuit capable of suppressing the phase fluctuation of the output clock signal when the reference clock signal changes from "off" to "present" and vice versa. To do.

[0007]

A phase-locked oscillator circuit according to a first aspect of the present invention receives a reference clock signal having an input frequency, and when the reference clock signal is normal, the phase-locked oscillator circuit outputs the reference clock signal. An output clock signal that is phase-locked with respect to the output frequency and has an output frequency that is (N / L) times the input frequency (N and L are integers of 2 or more, respectively),
It is a circuit that outputs a clock signal of an internally created phase as an output clock signal when the received reference clock signal is "disconnected".

According to the first aspect of the present invention, the phase locked oscillator circuit detects "disconnection" of the reference clock signal and determines whether the reference clock signal is "disconnected" or "present". A disconnection detection circuit that outputs the disconnection detection signal shown, a voltage controlled oscillator that oscillates an output clock signal based on a control voltage, an output clock signal divided by N, a clock signal divided by N, and this clock divided by N A first frequency divider circuit that outputs a first phase signal that indicates the phase of the signal, and a spare that oscillates a spare clock signal with a frequency that is (M / L) (M is an integer of 2 or more) times the input frequency. , And the standby clock signal M at an arbitrary phase when the disconnection detection signal indicates “disconnection” and at a phase indicated by the first phase signal when the disconnection detection signal indicates “presence”. The clock signal divided by M and divided by M A second frequency dividing circuit that outputs a second phase signal that indicates the phase of the clock signal that has been divided by M, and a reference clock signal that is divided by L at an arbitrary phase when the disconnection detection signal indicates "present". And outputs a clock signal whose frequency is divided by L, and when the disconnection detection signal indicates "disconnection", the third division is on standby so that the frequency division can be started at the phase indicated by the second phase signal. The frequency divider circuit receives the L-divided clock signal and the M-divided clock signal, and when the disconnection detection signal indicates "present", the L-divided clock signal indicates the disconnection detection signal indicates "disconnected". M when
A selection circuit that selects and outputs the divided clock signal as a selected clock signal is phase-compared with the selected clock signal and the N-divided clock signal, and a voltage representing the phase difference between them is used as a control voltage. And a phase comparison circuit for supplying to a controlled oscillator.

A phase-locked oscillator circuit according to a second aspect of the present invention receives a reference clock signal having an input frequency, and when the reference clock signal is normal, phase-locks with the reference clock signal, And the input frequency N (N is 2
This is a circuit that outputs an output clock signal having an output frequency that is a multiple of the above integer) and outputs the internally generated clock signal as the output clock signal when the received reference clock signal is "disconnected".

According to the second aspect of the present invention, the phase-locked oscillator circuit detects "disconnection" of the reference clock signal, and either "disconnection" or "presence" of the reference clock signal is detected. A disconnection detection circuit that outputs the disconnection detection signal shown, a voltage controlled oscillator that oscillates an output clock signal based on a control voltage, an output clock signal divided by N, a clock signal divided by N, and this clock divided by N A first frequency divider circuit that outputs a phase signal that indicates the phase of the signal, and an input frequency M (M
Is an integer greater than or equal to 2) and a spare oscillator that oscillates a spare clock signal having a frequency that is multiple times, and when the disconnection detection signal indicates "disconnection", the disconnection detection signal indicates "present" at any phase. Occasionally, the second frequency divider circuit that divides the spare clock signal by M and outputs the M-divided clock signal at the phase indicated by the phase signal, and receives the reference clock signal and the M-divided clock signal, A selection circuit that selects and outputs a reference clock signal when the disconnection detection signal indicates “present”, and a clock signal divided by M as the selected clock signal when the disconnection detection signal indicates “disconnection”. And a phase comparison circuit that compares the phases of the selected clock signal and the clock signal divided by N and supplies a voltage representing the phase difference between them to the voltage controlled oscillator as a control voltage.

[0011]

Embodiments of the present invention will now be described in detail with reference to the drawings.

Referring to FIG. 1, a phase locked oscillator circuit according to a first embodiment of the present invention receives a reference clock signal RC having an input frequency f _i, and the reference clock signal RC
Output clock if it is normal, phase-locked to the reference clock signal RC, and having (N / L) (N and L are each an integer of 2 or more) times the output frequency f _o of the input frequency f _i It is a circuit that outputs the signal OC and outputs the internally generated phase clock signal as the output clock signal OC when the received reference clock signal RC becomes "disconnected".

The phase-locked oscillator circuit of this embodiment includes a disconnection detecting circuit 16, an L frequency dividing circuit 17, a spare oscillator 18, and an M oscillator.
It has the same configuration as that shown in FIG. 4 except that it has a frequency dividing circuit 19 and a selecting circuit 20. Those having the same functions as those shown in FIG. 4 are designated by the same reference numerals, and their description will be omitted. The N frequency dividing circuit 14 outputs not only the clock signal NC divided by N but also the first phase signal P1 indicating the phase of the clock signal divided by N.

The disconnection detection circuit 16 has a reference clock signal RC.
"Disconnection" of the reference clock signal RC is detected.
A disconnection detection signal ID indicating either "present" or "present" is output.

The spare oscillator 18 oscillates a spare clock signal BC having a frequency that is (M / L) (M is an integer of 2 or more) times the input frequency f _i . The M divider circuit 19 has an arbitrary phase when the disconnection detection signal ID indicates “disconnected”,
When the disconnection detection signal ID indicates “present”, the backup clock signal B is in the phase indicated by the first phase signal P1.
C is divided by M, the M-divided clock signal MC and the second phase signal P indicating the phase of the M-divided clock signal MC.
2 and are output.

When the disconnection detection signal ID indicates "present", the L frequency dividing circuit 17 frequency-divides the reference clock signal RC by L at an arbitrary phase to output a clock signal LC which is L-divided, and at the same time disconnects. When the detection signal ID indicates "disconnected", it stands by so that the frequency division can be started at the phase indicated by the second phase signal P2. The selection circuit 20 receives the L-divided clock signal LC and the M-divided clock signal MC, and when the disconnection detection signal ID indicates “present”, L
The frequency-divided clock signal LC has a disconnection detection signal ID "disconnected".
, The clock signal MC divided by M is
The selected clock signal SC is selected and output. The selected clock signal SC is supplied to one input terminal of the phase comparison circuit 15. Therefore, the phase comparison circuit 15
Supplies the voltage control oscillator 13 with a voltage representing the phase difference between the selected clock signal SC and the N-divided clock signal NC as a control voltage CV.

First, the operation when the reference clock signal RC is normal will be described. In this case, the reference clock signal RC is frequency-divided by the L frequency dividing circuit 17, and the L-frequency-divided clock signal LC is supplied to the phase comparison circuit 15 through the selection circuit 20. Phase comparison circuit 15
Then, the phase difference between the clock signal NC obtained by dividing the output clock signal OC of the voltage controlled oscillator 13 by the N divider circuit 14 and the clock signal LC obtained by dividing the output clock signal LC by L is detected, and the voltage representing this phase difference is controlled. The voltage CV is supplied to the voltage controlled oscillator 13.

As described above, the output clock signal OC of the voltage controlled oscillator 13 is phase-synchronized with the reference clock signal RC. At this time, the M-divided clock signal MC output from the M-divider circuit 19 is output from the N-divider circuit 14 because the disconnection detection signal ID transmitted from the disconnection detection circuit 16 indicates “present”. First phase signal P1
The phase (approximately the same phase as the clock signal LC divided by L) indicated by is forced to match.

Here, the disconnection detection signal 16 detects "disconnection" of the reference clock signal RC, and the disconnection detection signal I indicating "disconnection".
Suppose D is output. In this case, the selection circuit 20 selects the clock signal MC divided by M as the selected clock signal SC. The phase comparison circuit 15 compares the phases of the clock signal MC divided by M and the clock signal NC divided by N, and outputs a voltage representing the phase difference between them as the control voltage CV. As a result, the output clock signal OC of the voltage controlled oscillator 13 is phase-locked with the spare clock signal BC output from the spare oscillator 18.

At this time, the output clock signal OC output from the voltage controlled oscillator 13 causes a phase jump at the control voltage CV generated by the phase difference between the clock signal NC divided by N and the clock signal MC divided by M. The phase of the clock signal MC divided by M by the first phase signal P1 is set to such an extent that it does not occur. This can prevent discontinuity of the output clock signal OC. When the reference clock signal RC is "disconnected", the L frequency dividing circuit 17 stops the frequency dividing operation, but the disconnection detection signal I indicating "disconnected".
D is in the standby state so that the frequency division can be started at the phase indicated by the second phase signal P2 output from the M frequency dividing circuit 19.

Next, it is assumed that the reference clock signal RC transits from "off" to "present". In this case, the disconnection detection circuit 16
Outputs a disconnection detection signal ID indicating “present”, the selection circuit 20 again outputs L as the selected clock signal SC.
Since the divided clock signal LC is selected, the output clock signal OC output from the voltage controlled oscillator 13 is phase-locked with the reference clock signal RC.

At this time, the clock signal NC divided by N is also used.
To the extent that the output clock signal OC output from the voltage controlled oscillator 13 does not cause a phase jump due to the control voltage CV generated by the phase difference between the L-divided clock signal LC and the L-divided clock signal LC. By setting the phase of the divided clock signal LC, the output clock signal O
It is possible to prevent discontinuity of C.

Referring to FIG. 2, the phase-locked oscillator circuit according to the second embodiment of the present invention has the same configuration as that shown in FIG. 1 except that the L divider 17 is omitted. That is, the reference clock signal RC is directly supplied to the selection circuit 20 without being divided. In this embodiment, as in the conventional example shown in FIG. 4, when the phase synchronization state, the output frequency f _o of the output clock signal OC is filed at N times the input frequency f _i of the reference clock signal RC. The frequency of the spare clock signal BC output from the spare oscillator 18 is M times the input frequency f _i of the reference clock signal RC.

FIG. 3 shows an output clock signal OC when the reference clock signal RC changes from "present" to "disconnected" and when it changes from "disconnected" to "present" in the phase locked oscillator circuit of the present invention. 3 shows how the output frequency f _o of V f changes. As is clear from this figure, the reference clock signal RC
Changes from “Yes” to “No” and “No” to “Yes”
It can be seen that even if the output frequency f 0 changes, the output frequency f _o does not fluctuate significantly beyond the allowable value, and the phase fluctuation can be suppressed.

[0025]

As described above, according to the present invention, the accuracy of the output frequency can be determined only by the frequency of the signal output from the spare oscillator by switching to the spare oscillator when the reference clock signal becomes "disconnected". Determined and does not require any other frequency stabilizing circuit. Also, when the reference clock signal changes from “OFF” to “Yes” and from “Yes” to “OFF”, the phase of the clock signal that can be switched is the same as the phase of the clock signal that has been selected until then. In the worst case of the output clock signal,
It will not be flipped. As a result, for example, when the reference clock signal is "disconnected", the output clock signal of the phase-locked oscillation circuit is phase-synchronized with the backup oscillator in the own device, and when the reference clock signal is input, it is dependent on the external synchronization network. In a system that synchronizes, it is possible to prevent the malfunction of the circuit due to the change from the spare oscillator to the slave synchronous output or vice versa.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a phase locked oscillator circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a phase locked oscillator circuit according to a second embodiment of the present invention.

FIG. 3 is a diagram showing a variation of the output frequency of the output clock signal when the reference clock signal is changed from “present” to “disconnected” and when the reference clock signal is changed from “disconnected” to “present” in the phase locked oscillator circuit of the present invention. It is a figure which shows the mode.

FIG. 4 is a block diagram showing a configuration of a conventional phase locked oscillator circuit.

FIG. 5 is a diagram showing how the output frequency of the output clock signal changes when the reference clock signal changes from “break” to “present” in the conventional phase-locked oscillator circuit.

[Explanation of symbols]

 11 Input Terminal 12 Output Terminal 13 Voltage Controlled Oscillator 14 N Divider Circuit 15 Phase Comparison Circuit 16 Break Detection Circuit 17 L Divider Circuit 18 Spare Oscillator 19 M Divider Circuit 20 Selection Circuit

Claims (2)

[Claims] 1. A reference clock signal having an input frequency is received, and when the reference clock signal is normal, the reference clock signal is phase-locked to the reference clock signal and (N / L) (N of the input frequency. And L is an integer greater than or equal to 2)
A phase-locked oscillator circuit that outputs an output clock signal having a double output frequency, and outputs the internally generated phase clock signal as the output clock signal when the received reference clock signal is "disconnected" A disconnection detection circuit that detects a disconnection of the reference clock signal and outputs a disconnection detection signal indicating one of "disconnection" and "presence" of the reference clock signal, and the output based on a control voltage A voltage-controlled oscillator that oscillates a clock signal, a first frequency divider that divides the output clock signal by N, and outputs a clock signal that is N divided and a first phase signal that indicates the phase of the N divided clock signal. A frequency divider circuit, a spare oscillator that oscillates a spare clock signal having a frequency that is (M / L) (M is an integer of 2 or more) times the input frequency, and the disconnection detection signal indicates "disconnection". When At an arbitrary phase, and when the disconnection detection signal indicates “present”, the spare clock signal is divided by M at the phase indicated by the first phase signal, and the clock signal is divided by M. A second frequency divider circuit that outputs a second phase signal that indicates the phase of the clock signal divided by M, and the reference clock signal at an arbitrary phase when the disconnection detection signal indicates "present". The frequency is divided by L and a clock signal divided by L is output, and the disconnection detection signal is "disconnected".
, The third frequency divider circuit is on standby so that the frequency division can be started at the phase indicated by the second phase signal, the L-divided clock signal and the M-divided clock signal. In response to this, when the disconnection detection signal indicates “present”, the L-divided clock signal is selected, and when the disconnection detection signal indicates “disconnected”, the M-divided clock signal is selected. A selection circuit that selects and outputs as a clock signal and the selected clock signal and the N-divided clock signal are compared in phase, and a voltage representing the phase difference between them is supplied to the voltage controlled oscillator as the control voltage. A phase-locked oscillator circuit having a phase comparator circuit. 2. A reference clock signal having an input frequency is received, and when the reference clock signal is normal, the reference clock signal is phase-locked to the reference clock signal and the input frequency is N (N is 2 or more). Outputs an output clock signal having an output frequency of (integer) times, and outputs a clock signal having an internally created phase as the output clock signal when the received reference clock signal is "disconnected". In the circuit, a disconnection detection circuit that detects a disconnection of the reference clock signal and outputs a disconnection detection signal indicating one of “disconnection” and “presence” of the reference clock signal; A voltage-controlled oscillator that oscillates the output clock signal; a frequency-divided clock signal that divides the output clock signal by N; and a phase signal that indicates the phase of the N-divided clock signal. A first frequency divider circuit for outputting a first frequency divider circuit, a spare oscillator for oscillating a spare clock signal having a frequency M (M is an integer of 2 or more) times the input frequency, and the disconnection detection signal indicating "disconnection". Is output at an arbitrary phase, and when the disconnection detection signal indicates "present", the spare clock signal is frequency-divided by M and a clock signal frequency-divided by M is output. Second
Receiving the reference clock signal and the M-divided clock signal, the reference clock signal is turned off when the disconnection detection signal indicates "present", and the disconnection detection signal is switched off. When shown, the selection circuit that selects and outputs the M-divided clock signal as the selected clock signal is phase-compared with the selected clock signal and the N-divided clock signal, and their phase difference is obtained. And a phase comparison circuit which supplies the voltage representing the voltage as the control voltage to the voltage controlled oscillator.