JPH06176501A - Disk reader - Google Patents

Abstract

PURPOSE:To reduce the number of retrying times and to promote effective reading speed by surely reading contents of information in accurate synchronization even when a read information signal is somewhat defective. CONSTITUTION:The reader is equipped with a main channel MCA for bit- synchronizing an information signal S read out by an optical pickup, which is not shown in the figure, with a PLL 30 and detecting an AM (address mark) with an AM detector 33 and an n-number of subchannels SCA1-SCAn for detecting the AM in synchronization with clocks shifted in phase by each 360 deg./n respectively to be outputted by a clock circuit 20. The main channel MCA is preferentially selected by a channel selecting circuit 24 if the AM is detected by the main channel MCA, and if not, the best bit-synchronized subchannel SCAk (k=1-n) among plural subchannels having detected the AM is selected. Then, ID information following upon the AM is outputted via the selected channel to a controller 9, and its contents are read out.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reader for a disk device that uses a storage medium such as a magnetic disk or an optical disk.

[0002]

2. Description of the Related Art There is a disk device for recording or reproducing information or a reproduction-only disk device using a storage medium such as a magnetic disk such as a floppy disk or a hard disk, or an optical disk such as a CD (compact disk) or a magneto-optical disk. It is widely used as a mass storage device that is a peripheral device of a host machine.

Information recorded on such a disc is
A disk reading device that reads with a pickup such as an optical pickup or a magnetic head uses a VFO pattern recorded in a VFO section provided immediately before a synchronization pattern of an ID section and a data section of each sector (information recording unit).
After the LL (Phase Lock Loop) circuit is pulled in to perform bit synchronization, word synchronization is performed with an ID synchronization pattern or a data synchronization pattern, and I following each synchronization pattern.
D information and data can be read.

In this case, if there is a defect in the VFO portion, the bit synchronization cannot be established, so that the word synchronization cannot be obtained, so that the information such as ID information and data cannot be read.
In order to prevent such a defect from occurring at the time of writing, a read-after-write method is used in which the information once written is read immediately after writing and if any error occurs, the writing is performed again.

However, even if the information is correctly written, in case that a defect is caused for some reason after that, it is necessary to read again the sector where the information could not be read as a remedy when reading. A retry method is used in which the information is read or the preset number of times is performed.

Therefore, as disclosed in, for example, Japanese Patent Publication No. 1-39258, the correlation between the first read signal before decoding and the second read signal whose phase after decoding is shifted is monitored, There has been a proposal to determine whether or not the decoding operation is synchronized. Alternatively, as disclosed in Japanese Patent Laid-Open No. 64-13263, the information signal after binarization is sampled, the sampling data is divided into several blocks, and the coincidence with the synchronization pattern is detected for each block. Then, there was a proposal to detect the sector mark.

[0007]

However, since the former proposal is for determining whether or not synchronization is established, even if it is possible to prevent reading erroneous information, when it is determined to be no, Even if the disk rotates at high speed, it is much slower than the data reading speed, and dozens of sectors are provided in one track, so that normal reading is possible. It is unavoidable that the reading speed is reduced to several tenths each time one retry is performed as compared with the speed.

The latter proposal can be applied to other than the sector mark, and it can be expected that the number of retries will be greatly reduced, but the frequency of the information signal to be read can also be written, read, or read as the processing speed increases. In the current situation where data processing is as high as possible, ultra high-speed elements are required to process the sampled data in real time by performing sampling that further divides the waveform. I must say that it is very difficult in practical use.

The present invention has been made in view of the above points, and even if there is some defect in the information signal read by the pickup, the content of the information is surely read by accurate synchronization and the number of retries is repeated. To improve the effective reading speed.

[0010]

In order to achieve the above object, the present invention provides a disk reading apparatus for reading information recorded on a disk with a pickup to reproduce the data, which is read by the pickup. A main channel for detecting an address mark from the information signal in bit synchronization with the information signal, a clock generating means for outputting a plurality of clocks having substantially equal phase differences with each other at a frequency equal to the frequency of the information signal, and the clock. The main channel detects an address mark by inputting a plurality of sub-channels that detect an address mark in synchronization with each of a plurality of clocks output by the generating means and detection results of the plurality of sub-channels and the main channel. When the main channel is selected, the main channel is selected. A plurality of sub-channels in which a plurality of sub-channels are detected, and a channel selection unit that selects a sub-channel synchronized with a clock having a phase closest to a phase of a combined vector of clocks with which the plurality of sub-channels are synchronized, The ID information following the address mark in the information signal is read through the channel selected by the channel selection means.

According to a second aspect of the present invention, in a disc reading apparatus for reading information recorded on a disc with a pickup to reproduce data, a data sync mark is detected from the information signal bit-synchronized with the information signal read by the pickup. A main channel, a clock generating means for outputting a plurality of clocks having a substantially equal phase difference with each other at a frequency equal to the frequency of the information signal, and a data sync mark in synchronization with the plurality of clocks output by the clock generating means. When a plurality of sub-channels for detecting the data sync and the detection results of the plurality of sub-channels and the main channel are input, and when the main channel detects the data sync mark, the main channel is selected and not detected. Of multiple sub-channels that have detected the data sync mark A plurality of sub-channels, each of which is provided with channel selection means for selecting a sub-channel synchronized with a clock having a phase closest to a phase of a combined vector of clock phases, and a channel selected by the channel selection means The contents of the data part following the data sync mark in the information signal are read.

Further, in the above-mentioned disc reading device, a plurality of phase-locked loop circuits for outputting pulses to be synchronized with each of a plurality of sub-channels, and inputs of the plurality of phase-locked loop circuits are always provided. A plurality of clocks are provided for each of them, and a synchronous input switching means for switching to an information signal when the channel selecting means selects any one of the plurality of sub-channels is provided.

[0013]

In the disk reader according to the first aspect of the present invention, when the main channel detects the address mark from the information signal read by the pickup, that is, when the main channel is bit-synchronized with the information signal, the channel selecting means selects the main channel. Therefore, the ID information following the address mark can be reliably read through the main channel.

On the other hand, some of a plurality of sub-channels, each of which is synchronized with a plurality of clocks having a frequency substantially equal to the frequency of the information signal output from the clock generating means and having a substantially equal phase difference ( The plurality of sub-channels detect the address mark in bit synchronization with the information signal.

Therefore, when the main channel does not detect the address mark, the channel selecting means synchronizes with the clock having the phase closest to the phase of the combined vector of the clocks with which the plurality of sub-channels which have detected the address mark are synchronized. The selected sub-channel, that is, the sub-channel with the best bit synchronization is selected, so that the ID information following the address mark can be reliably read through the selected sub-channel.

The disc reader according to the second aspect of the present invention has the address mark in the disc reader according to the first aspect of the present invention replaced with a data sync mark.
Even if the length of the mark changes, the contents of the data portion following the data sync mark can be surely read through the main or sub-channel similarly selected by the channel selection means.

However, since the length of the data part is much longer than the length of the ID information, even if bit synchronization is initially good when the sub-channel is selected, it can be read due to a slight fluctuation of the disk rotation. The phase of the bit of the information signal and the phase of the clock output by the clock generating means may deviate while reading the contents of the data part.

In preparation for such a case, when the channel selection means selects any one of the plurality of sub-channels, the synchronization input switching means outputs a pulse to be synchronized for each of the plurality of sub-channels. Since the inputs of a plurality of phase-locked loop circuits are switched from their respective clocks to the information signals, the sub-channels that have been the most bit-synchronized will be synchronized with the information signals in that state, and the bit-synchronization deviation will occur. Does not happen. It goes without saying that the same effect can be obtained even when applied to the disk reading device according to the first invention.

[0019]

FIG. 2 is an embodiment of the present invention and is a schematic configuration diagram showing the configuration of an optical disc apparatus for recording and reproducing information by using an optical disc for recording information by the density of bits.

The mechanism section of the optical disk device 1 shown in FIG. 2 includes a spindle motor 3 for mounting and rotating an optical disk 2 which is a removable disk, and a target track on the recording surface (back side) of the optical disk 2. And an seek motor 5 for moving the optical pickup 4 in the radial direction of the optical disk 2 for searching and tracking.

An optical pickup 4, which is a pickup for optically recording and reproducing information, forms a laser beam output from a laser diode (not shown) as a sharp spot on (the recording surface of) the optical disc 2, and at the time of recording. The intense laser light is turned on / off according to the bit of information, and the heat of the spot forms a row of shades. At the time of reproduction, weak laser light is continuously emitted to detect the reflected light according to the light and shade, convert it into an electric signal and output it.

The information processing unit of the optical disk device 1 includes a reproduction input unit including a preamplifier 6, an equalizer 7, and a demodulator 8, a controller 9, a CPU 10, a ROM 11, and a RAM.
It is composed of a processing control unit consisting of 12 and a recording output unit consisting of a modulator 13 and an amplifier 14.

The processing control unit includes a buffer register 9 incorporated in the controller 9 in response to a command from the CPU 10 based on a program stored in the ROM 11 in advance.
Input / output and processing of information (including data) is performed by using the RAM such as a and ECC register 9b. The controller 9 is also connected to the host computer 16 to input / output information. The buffer register 9a temporarily stores input / output information, and the ECC register 9b is used for data error correction.

At the time of information recording, the write data stored in the buffer register 9a and combined into one sector and output from the controller 9 is modulated by the modulator 13 of the recording output section and amplified by the amplifier 14 to the write power. Then, the laser diode (not shown) of the optical pickup 4 is strongly turned on / off to record on the optical disc 2.

At the time of reproducing information, the laser diode continuously emits light with a weak output, and the optical pickup 4 collects information recorded in several tens of sectors on the target track of the optical disk 2 for each sector and reflects light. Is detected serially as the strength of, and converted into an electric signal (information signal) and output to the preamplifier 6.

The input information signal is amplified by the preamplifier 6 and then input to the demodulator 8 as a binarized signal whose waveform is shaped by the equalizer 7. The demodulator 8 first bit-synchronizes the input binarized information signal, then word-synchronizes with an ID synchronization pattern, a data synchronization pattern, etc. to determine the type of the signal, and then the ID following each synchronization pattern. Information and data are output to the controller 9, and the controller 9 reads each information and data.

FIG. 3 is an explanatory diagram showing an example of the format of the information recorded on the optical disc 2, and FIG.
Shows the entire format for one sector, and (B) in the same figure
And (C) are enlarged views of the ID part and the ODF part, respectively. The numbers outside the margins of FIG. 3 and the numbers in parentheses in the following description indicate the length of each piece of information in bytes.

In FIG. 3A, a pre-format section (52) provided at the leading end of one sector of information (746), which is a recording and reproducing unit, is an SM (5, 5) indicating the beginning of the sector. Sector mark) and an information group consisting of VFO, AM (1, address mark) and ID part (5) which are each repeated three times.
Is preformed by formatting before use.

The VFO forming each of the above information groups is a mark for bit synchronization when reading, AM is a mark indicating that the ID portion comes next for word synchronization, and the ID portion following AM is As shown in FIG. 3B, ID information including a track number, a sector number and a CRC (Cyclic Redundancy Code) is written.

In recording and reproducing information, first, the track number of the ID information is read to search for the target track from among the thousands of tracks, and then the sector number is read and there are tens of tracks for each track. After the target sector is specified from among the sectors, data is recorded in an area following the pre-format section or information is read from the area to reproduce the data. Therefore, the same information group is written three times so that important ID information is not missed.

ODF section (1
4) shows ODF (1, offset detection flag), flag, ALPC (2, auto laser power control) across two gaps (3) as shown in FIG. 3C. ) Is provided, ODF is a mark for correcting an offset (deviation) in the track signal, and ALPC is for adjusting the laser output.

A data part (665) following the ODF part is a VFO (12) for re-establishing bit synchronization, a word sync and a data sync mark Sync (3) indicating that the next data area comes, and User data, D
It consists of a data area (650) consisting of MP, ECC, CRC, and resync. After the data section, the buffer section (1
5) follows, and the information for one sector ends.

FIG. 1 is a circuit diagram showing a first embodiment of the demodulation device 8 (FIG. 2) of the optical disk device 1 according to the first invention.

The demodulator 8a for detecting the address mark according to the first embodiment shown in FIG. 1 includes an equalizer 7 (FIG. 2).
From the main channel MCA for detecting AM (address mark) from the binarized information signal input from
As the above integers, a clock circuit 20 that is a clock generating unit that outputs n clocks CK _{1 to} CKn having phases different from each other by 360 ° / n, and clocks CK _{1 to} CK.
It is composed of n sub-channels SCA ₁ -SCAn for detecting AM in synchronization with n and a channel selection circuit 24 which is a channel selection means.

The clock circuit 20 has a frequency f of the information signal.
An oscillator 21 that outputs a clock CLK having a frequency fc equal to i, and a clock CLK that is serially connected
The consists of n delay elements 22 for forming the n-number of clock CK ₁ ~CKn by delaying by 360 ° / n, the clock CK ₁ ~CKn is output to subchannel SCA ₁ to SCAN respectively.

The main channel MCA includes a signal demodulation section including a PLL (phase lock loop circuit) 30 and a D-FF (flip-flop circuit) 31, an S / P (serial / parallel) converter 32, and an AM detector (DET).
And an AM detection unit composed of 33.

The PLL 30 outputs to the input information signal a D-F clock which is phase-synchronized with the VFO signal immediately before it.
The signal demodulator outputs the signal to the CK terminal of F31, and the D-FF31 latches the information signal input to the D terminal at the rising edge of the clock input to the CK terminal and outputs it from the Q terminal. The minute data is held until the next bit is input, and is output to the S / P converter 32 and the switch element 26 ₀ of the channel selection circuit 24 described later.

The S / P converter 32 is the D of the signal demodulator.
The 1-bit data serially input from the FF 31 is combined with the 7-bit data that was input and held immediately before, is converted into 8-bit parallel data, and is output to the AM detector 33. The AM detector 33 is the S / P converter 3
The 8-bit data pattern input from 2 is compared with the pre-stored address mark pattern, and if a match of a preset threshold value or more is obtained, an AM pattern detection signal is output to the arbiter 25 of the channel selection circuit 24. .

Hereinafter, when a certain channel outputs an AM pattern (or a Sync pattern described later) detection signal, that channel is also referred to as "significant", and AM (S
ync) The channel that outputs the pattern detection signal is also referred to as a "significant channel".

Arbiter 25 of channel selection circuit 24
When the AM pattern detection signal is input from the main channel MCA (the main channel is significant), only the switch element 26 _{0 is} preferentially turned on regardless of whether the sub-channels SCA _{1 to} SCAn are significant. hand,
The controller 9 causes the controller 9 to output the information signal output from the D-FF 31 of the main channel MCA.
The ID information following M is read.

If there is no defect in the information signal, the PLL 30 is correctly phase-synchronized with the information signal to be bit-synchronized, and the AM detector 33 detects the AM pattern to be word-synchronized, the controller 9 directly outputs AM. The pattern detection signal is detected, and subsequently input ID information is input to the D- of the signal demodulation unit.
It can be read via the FF 31.

Conventionally, as described above, the information is demodulated from the information signal using only the main channel to reproduce the data. However, if there is a defect in the information signal, correct bit synchronization cannot be obtained. Therefore, since the AM pattern cannot be detected, word synchronization cannot be obtained either. Therefore, the retry is repeated until the bit synchronization is obtained by chance.

According to the present invention, by providing n sub-channels, even if the main channel is not correctly phase-synchronized and bit synchronization or word synchronization cannot be achieved (insignificant), one of the sub-channels is phase-synchronized. Bit synchronization and word synchronization are established in synchronism with each other, and the sub-channel that has become significant is selected and the information is read.

That is, n sub-channels SCA ₁
~ The configuration of SCAn is all main channel MCA
The PLL 30 is removed from the above, and 360 ° / n output from the clock circuit 20 instead of the output of the PLL 30.
The n clocks CK _{1 to} CKn whose phases are shifted from each other are input to the CK terminals of the respective D-FFs 31 _{1 to} 31n.

Therefore, the sub-channels SCA ₁ -S
The D-FFs 31 _{1 to} 31 n of CAn sequentially latch information signals with a phase difference of 360 ° / n, and the S / P converter 32 ₁
The 8-bit data pattern ~32n is converted by detecting AM detector 33 ₁ ~33n is AM, it outputs the respective sub-channel having detected the address mark AM pattern detection signal to the arbiter 25 of the channel selection circuit 24.

Since it is desirable that the number n of sub-channels is as small as possible, it depends on the threshold value for judging the pattern coincidence of the AM detector 33, but theoretically, at least one sub-channel will be significant as long as it is significant. Good. However, in that case, there is a possibility that pattern matching may not be obtained in practice, so at least a number of sub-channels that makes a plurality of sub-channels significant will be provided.

The arbiter 25 is a main channel MCA.
When an AM pattern detection signal is input from any of a plurality of sub-channels SCA _{1 to} SCAn without inputting an AM pattern detection signal from the sub-channel SCA _{1 to} SCAn, a composite vector of clock phases with which the significant sub-channels are respectively synchronized Select the sub-channel synchronized with the clock of the phase closest to the phase of the selected sub-channel S
Only the switch element 26k corresponding to CAk is turned on to output the information signal that has passed through the sub-channel SCAk to the controller 9.

Here, the subscript k is an integer value in the range of 1 to n, but when considering in terms of phases, a ring is formed and 1 and n are adjacent to each other with a phase difference of 2π / n. Therefore, n-1, n, and n + 1 are equal to -1, 0, and 1, respectively.

For example, when the three subchannels with the subscripts k-1, k, k + 1 become significant, the phase x of the combined vector of the phases of the clocks CK becomes k,
The sub-channel SCAk having the same clock phase is selected and the switch 26k is turned on.

Further, for example, when two consecutive sub-channels SCA ₂ , SCA ₃ or four consecutive sub-channels SCA _{1 to} SCA ₄ become significant, the clocks CK ₂ , CK ₃ or the clocks CK ₁ to Since the phase of the combined vector of the phases of CK ₄ becomes x = 2.5, either the sub-channel SCA ₂ or SCA ₃ synchronized with the clock CK ₂ or CK ₃ of the phase closest to it is selected. In this case, it is equally effective regardless of which sub-channel is selected.

Generally, when an odd number of consecutive sub-channels becomes significant, a sub-channel (center sub-channel) whose subscript is the average value of those subscripts is selected, and an even number of sub-channels is significant. When
It suffices to select a subchannel whose subscript is one of integers on both sides of the average value of those subscripts.

By doing so, even if only one subchannel becomes significant for some reason, or even if the subchannels other than both ends of consecutive subchannels do not become significant, n subchannels are not significant. Since any one of them is selected, the address mark is not missed or the ID information is unreadable.

Even if the main channel and the sub-channel do not become significant, even if the replay is performed, the probability of reading the ID information at the time of the replay is significantly higher than that of the demodulator of the conventional disc reader.

FIG. 4 is a circuit diagram showing a second embodiment of the demodulation device 8 (FIG. 2) of the optical disk device 1 according to the second invention, and the same parts as those of the first embodiment shown in FIG. 1 are the same. The reference numerals are given and the description is omitted.

The demodulator 8b for detecting the data sync mark, which is the second embodiment shown in FIG. 4, is the first embodiment (FIG. 1).
3 is different from the main channel MCA and the sub-channels SCA _{1 to} SCAn for detecting AM, respectively, in the sync part of the data section shown in FIG. 3A.
Main channel M to detect (data sync mark)
That is, the CS and the sub-channels SCS _{1 to} SCSn are set.

More specifically, since the word sync mark to be detected is changed from 1-byte AM to 3-byte Sync, 8-bit S / P converters 32, 32 _{1 to} 32 are used.
n and AM detector 33,33 ₁ ~33n are each 2
4-bit S / P converter 36,36 ₁ ~36n and Sync detector 37, 37 is to become _{1 ~37n,} is exactly the same as action.

Therefore, the channel selection circuit 24
When the main channel MCS detects Sync and becomes significant, the main channel MCS is preferentially selected, and the main channel MCS is not significant, and some of the n sub-channels SCS _{1 to} SCSn are significant. If the sub-channel becomes significant, the sub-channel synchronized with the clock having the phase closest to the phase of the combined vector of the clocks with which the significant sub-channel is synchronized is selected.

Information such as user data, DMP, ECC, CRC, and resync contained in the 650-byte data area following Sync is sent to the controller 9 via the channel selected by the channel selection circuit 24, and the controller 9 sends it. The data (user data) is read and reproduced.

The ECC (error check code) included in the data area is stored in the ECC register 9 in the controller 9.
It is for performing error correction if there is a data error in the information read and stored in b (FIG. 2).

In the first embodiment, there is no problem because the ID information following AM is only 5 bytes, but in the second embodiment there is 650 bytes and 15 bytes of information in the data area and buffer following Sync respectively. There is a length of.
Therefore, if there is a slight difference between the frequency fc of the clock CLK output from the oscillator 21 and the frequency fi of the information signal, the bit synchronization is lost during the reading and the information cannot be read.

Generally, the difference between the frequency fc and the frequency fi is constantly monitored, and if a difference occurs, the rotational speed of the spindle motor 3 is servo-controlled so that the frequency fi matches the frequency fc. The two are in agreement. However, microscopically, the spindle motor 3
Due to uneven rotation of the disk, eccentricity of the optical disk 2, and the like, minute fluctuations in the frequency difference between the two are inevitable.

FIG. 5 is a circuit diagram showing a third embodiment of the demodulation device 8 of the optical disk device 1 for preventing such loss of bit synchronization, and the same parts as those of the second embodiment shown in FIG. 4 are the same. The reference numerals are given and the description is omitted.

The demodulator 8c for detecting the data sync mark according to the third embodiment shown in FIG. 5 is the second embodiment (FIG. 4).
Is different from the arbiter 2 of the channel selection circuit 24a.
5a is to output an input switching signal when the selected one of the sub-channel SCS ₁ ~SCSn.

Further, changeover switch elements 27 ₁ to 27 ₁ to output clocks CK _{1 to} CKn input from the clock circuit 20 in response to the input changeover signals, respectively, are switched to information signals.
A switching circuit 28 which is a synchronous input switching means composed of 27n.
And the clock signals phase-synchronized with the respective outputs of the changeover switch elements 27 _{1 to} 27 n are supplied to the sub-channels SCS _{1 to} SCS.
n D-FF31 _{1 to} 31n PL output to the CK terminal
L30 _{1 to} 30n are provided.

Normally, the clocks CK _{1 to} CKn output from the clock circuit 20 are transferred to the PLL 30 via the switching circuit 28.
Fill in _{1 ~30n,} from PLL30 ₁ ~30n is outputting a clock synchronized in phase with each D-FF31 ₁ ~31n, to channel selection circuit 24a selects one of the subchannels SCS ₁ ~SCSn Is exactly the same as the second embodiment.

When the channel selection circuit 24a selects _{one of the} sub-channels SCS _{1 to} SCSn, the arbiter 25a outputs an input switching signal to the switching circuit 28, and the switching switch elements 27 _{1 to} 27n of the switching circuit 28 respectively PLL 30 _1. Since the input of .about.30n is switched to the information signal, the PLLs 30 _{1 to} 30n thereafter output a clock bit-synchronized with the information signal, and the rising edges of the clock cause the D-FFs 31 _{1 to} 31n to latch the information signal, respectively.

In this case, the selected sub-channel SC
The clock CKk synchronized with Sk is the main channel M
Since it is a clock that is bit-synchronized with the information signal better than the clocks of all other channels including CS,
The information signal input to the controller 9 via the sub-channel SCSk and the switch element 26k can be smoothly switched without any influence.

After the input is switched, the frequency f of the information signal due to the uneven rotation of the spindle motor 3 and the eccentricity of the optical disk 2, etc.
Even if there is some variation in i, the data sync mark (Sy
During the reading of the data part and the buffer subsequent to nc), the bit synchronization is surely maintained and the data is not missed. This input switching does not matter even if it is applied to the first embodiment for detecting AM.

The demodulator 8a for detecting AM in the first embodiment and the demodulators 8b, 8c for detecting Sync in the second and third embodiments have been described above as separate circuits based on the bit difference. For example, a 24-bit S / P converter 3
6,36 _{1 to} 36 n and Sync detector 37,37 ₁ to
8n AM detected by 37n or 8
Bit S / P converters 32, 32 _{1 to} 32 n and A
S of 24 bits by M detectors 33,33 ₁ ~33n
It is also possible to detect ync in three times.

In this way, if the controller 9 outputs the AM or Sync pattern to the detector in accordance with the respective timings, the same demodulator 8 is used to output the AM or Sync pattern.
And Sync are detected, and the controller 9 can read the ID information and the contents of the data portion which follow respectively in correct bit synchronization and word synchronization.

As described above, in the optical disc device 1 according to the present invention, the demodulation device 8 is composed of a main channel (conventional channel) and a plurality of sub-channels, and the information signal read by the optical pickup 4 is somewhat different. Even if the main channel cannot read the address mark or the data sync mark due to the defect of the sub-channel, any of the multiple sub-channels of the n sub-channels (only one due to an error etc.) may be the address mark. Or data sync mark is detected.

Among these significant sub-channels (in which the mark is detected), the channel selection circuit 24 selects the sub-channel that is most bit-synchronized with the information signal, and the controller 9 transmits the information through the selected sub-channel. You can read it correctly. Therefore, the information is read and the data is reproduced much more surely as compared with the reading by the conventional optical disk device, so that almost no retry is required.

In the unlikely event that the main channel and the sub channel cannot read the address mark and the data sync mark,
Even if a retry is made, the probability of re-reading is also high, so the number of retries that significantly reduce the reading speed is drastically reduced, and the effective reading speed is improved. Further, although the number of parts is increased, an ultra-high speed element is not required, so that the cost will not be significantly increased.

Although the embodiment of the reading device of the optical disk device has been described above, the present invention is not limited to the optical disk device and can be applied to a reading device of a magnetic disk device using a hard disk, floppy disk or the like. Needless to say.

[0075]

As described above, the disc reader according to the present invention ensures accurate reading of the contents of information even if there is some defect in the information signal read by the pickup, and the retry of the retry is performed. It is possible to reduce the number of times and improve the effective reading speed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a first embodiment of a demodulation device for an optical disc device according to the present invention.

FIG. 2 is a schematic configuration diagram showing a configuration of an optical disc device according to an embodiment of the present invention.

FIG. 3 is an explanatory diagram showing an example of a format of information recorded on an optical disc.

FIG. 4 is a circuit diagram showing a configuration of a second embodiment of a demodulation device of an optical disc device.

FIG. 5 is a circuit diagram showing a configuration of a third embodiment of the demodulation device of the optical disc device.

[Explanation of symbols]

1 Optical Disc Device (Disc Reading Device) 2 Optical Disc (Disc) 4 Optical Pickup (Pickup) 8, 8a, 8b, 8c Demodulator 20 Clock Circuit (Clock Generating Means) 24, 24a Channel Selection Circuit (Channel Selection Means) 28 Switching Circuit (Synchronous input switching means) 30, 30 _{1 to} 30n PLL (Phase-locked loop circuit) MCA, MCS main channel SCA _{1 to} SCAn, SCS _{1 to} SCSn sub-channel

Claims (3)

[Claims] 1. A disc reading apparatus for reading information recorded on a disc by a pickup to reproduce data, wherein a main channel for detecting an address mark from the information signal bit-synchronized with the information signal read by the pickup. A clock generating means for outputting a plurality of clocks having a frequency substantially equal to the frequency of the information signal and having substantially equal phase differences, and the address mark detected in synchronization with the plurality of clocks output by the clock generating means. Input a plurality of sub-channels, detection results of the plurality of sub-channels and the main channel, and select the main channel when the main channel detects the address mark and does not detect the main channel Contains the sub-channels that detected the address mark. Channel selection means for selecting a sub-channel synchronized with a clock having a phase closest to the phase of a combined vector of clocks of the plurality of sub-channels, among the plurality of sub-channels, and selected by the channel selection means. A disc reading device characterized in that ID information following an address mark in the information signal is read through a channel. 2. A disc reading apparatus for reading information recorded on a disc by a pickup to reproduce data, wherein a data sync mark is detected from the information signal in bit synchronization with the information signal read by the pickup. A channel, a clock generating means for outputting a plurality of clocks having a frequency substantially equal to the frequency of the information signal and having substantially equal phase differences, and the data sync mark in synchronization with each of the plurality of clocks output by the clock generating means. A plurality of sub-channels for detecting a plurality of sub-channels and the detection results of the plurality of sub-channels and the main channel are input, and when the main channel detects the data sync mark, the main channel is selected and detected. If not, the data sync mark is detected. A plurality of sub-channels, and a channel selection means for selecting a sub-channel synchronized with a clock having a phase closest to a phase of a combined vector of clocks with which the plurality of sub-channels are synchronized, respectively. A disc reading device, wherein the contents of the data portion following the data sync mark in the information signal are read through the selected channel. 3. The disk reader according to claim 1, wherein a plurality of phase-locked loop circuits output a pulse to be synchronized with each of the plurality of sub-channels, and the plurality of phase-locked loop circuits. The input of the circuit is always the plurality of clocks, and the synchronous input switching means for switching to the information signal when the channel selecting means selects one of the plurality of sub-channels is provided. Characteristic disk reader.