JPH06175611A - Liquid crystal display - Google Patents

Abstract

PURPOSE:To decrease signal lines formed at the peripheral section of a liquid crystal panel and to reduce area of the peripheral section by providing a switching circuit, switching bits of a digital picture signal and the reference voltage, and supplying them to a data driver via the same signal line. CONSTITUTION:A switching circuit 115 changes over the bits Dm-Do of a digital picture signal DIN and Vn-Vn-m being a part of plural reference voltage Vn-V1, and switched bits Dm-Do of the digital picture signal and the reference voltage Vn-Vn-m are supplied to a data driver 114 via the same signal line group 116. The data driver selects the reference voltage having a voltage value corresponding to the digital picture signal Din out of the supplied reference voltage Vn- Vn-m, and the selected reference voltage is sent to the data line of a liquid crystal panel 113 as an analog picture signal. Therefore, the number of signal lines can be decreased when being compared with the case in which bits Dm-Do of the digital picture signal Din and the reference voltage Vn-V1 are supplied to the data driver 114 with individual signal lines.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device having an active matrix type liquid crystal display panel.

In recent years, liquid crystal display devices have come to have a cathode ray tube (CR).
T) is expected as a display device that substitutes for a display device, and its technical development is actively carried out.
In particular, a liquid crystal display device including an active matrix type liquid crystal display panel is regarded as promising because it has a high display speed and excellent display quality.

[0003]

[Prior art]

First Conventional Example ... FIGS. 26 to 30 FIG. 26 is a diagram schematically showing a circuit configuration of a first conventional example of a liquid crystal display device including an active matrix type liquid crystal display panel.

[0004] In the figure, 1 is a liquid crystal display panel of active matrix type that an array of pixels as a minimum unit of a display image 4 (horizontal) × 4 (vertical), 2 _{11-2 44} each represent a pixel ing.

[0005] Figure 27 is a diagram showing the structure of the liquid crystal display panel 1 schematically in the drawing, 3 _{11-3 44} pixels 2 ₁₁
Liquid crystal capacitance of ~ 2 _44, 4 _{11-4 44} pixel electrodes provided in each pixel ₂₁₁ to 2 _44, 5 is a common electrode provided in common to all the pixels 2 ₁₁ to 2 _44.

Further, 6 _{11 to} 6 ₄₄ are pixel electrodes 4 ₁₁ to 4 _{44, respectively.}
A thin film transistor (Thin Film Transiste) that functions as a switching element when an analog image signal (voltage) obtained by analog-converting a digital image signal is supplied to
r. Hereinafter referred to as TFT).

Further, X ₁ to X ₄ is the pixel electrode 4 _{11-4 44} data lines (signal lines) for supplying an analog image signal to, Y
₁ to Y ₄ is TFT 6 ₁₁ to 6 ₄₄ ON of a gate line that controls the OFF (scanning lines).

In the actual liquid crystal display panel, the number of pixels is, for example, 64 in the case of monochrome (mono-color) display.
It is set to 0 (horizontal) × 480 (vertical), and in the case of color display, each pixel for R (red), G (green), and B (blue) is required. Therefore, for example, 640 × 3 ( It is set to (horizontal) × 480 (vertical).

Here, the arrangement of pixels in the horizontal direction is generally called a line, and the writing of the analog image signal to one screen is performed in sequence for each line, and the writing of the analog voltage to this one screen is performed 60 times per second. By doing so at a certain rate, an image without "flickering" is shown to the human eye.

Further, in FIG. 26, 7 is a control circuit for controlling the entire apparatus, HS is a horizontal synchronizing signal, VS is a vertical synchronizing signal, D _IN is a digital image signal, and CLK is a timing of fetching the digital image signal D _IN. Is a timing signal that gives

In this example, the digital image signal D _IN has a 4-bit structure of D3 (most significant bit), D2, D1, D0 (least significant bit) in order to display 16 gradations. .

A reference voltage source 8 outputs reference voltages V16 to V1. The reference voltage source 8 is constructed as shown in FIG. In the figure, 9 to 24 are reference voltages V
It is an individual reference voltage source that generates 16 to V1.

Further, in FIG. 26, reference numeral 25 is an integrated circuit which converts the digital image signal D _IN into an analog image signal and sends the analog image signal to the data lines X _{1 to} X ₄ of the liquid crystal display panel 1. It is a data driver.

In this data driver 25, 26
Is a start signal T1 output from the control circuit 7 for each line, and a clock signal C output from the control circuit 7.
It is a serial input / parallel output type shift register having a 4-bit configuration that shifts bit by bit in synchronization with K1 and sequentially outputs timing signals TS _{1 to} TS ₄ .

Numerals 27 _{1 to} 27 ₄ are 4-bit capacitors for sequentially holding the digital image signals D _IN supplied from the outside in synchronization with the timing signals TS _{1 to} TS ₄ output from the shift register 26 for each pixel. Memory circuit.

Further, 28 _{1 to} 28 ₄ are memory circuits 27 ₁ to
27 ₄ is obtained by decoding the digital image signal D _IN held at the reference voltage output from the reference voltage source 8 V16～V1
Is a decoder that outputs a selection signal for selecting a reference voltage having a voltage value corresponding to the digital image signal D _IN from among the above.

These decoders 28 _{1 to} 28 ₄ have the same circuit configuration. If the decoder 28 ₁ is represented as a representative,
It is configured as shown in FIG. 29 to 32 in the figure
Are inverters, 33-40 are NAND circuits, 41-56
Is a NOR circuit.

In this decoder 28 ₁ , the digital values [D3, D2, D1, D0] of the digital image signal D _IN are obtained.
According to the above, the output of any one of the NOR circuits 41 to 56 is set to the H level, and the output of the other NOR circuits is set to the L level.

Further, in FIG. 26, 57 ₁ to 57 ₄ in accordance with the selection signal output from the decoder 28 _{1-28 4,}
It is a selector that selects a reference voltage having a voltage value corresponding to the digital image signal D _IN from the reference voltages V16 to V1 output from the reference voltage source 8.

[0020] These selectors 57 ₁ to 57 ₄ are the same circuit configuration, if Shimese on behalf of the selector 57 _1,
It is configured as shown in FIG. 58-73 in the figure
Is an analog switch whose ON and OFF are controlled by the outputs of the NOR circuits 41 to 56 of the decoder 28 ₁ .

These analog switches 58-73 are
Of the NOR circuits 41 to 56, the corresponding NO
ON when the output of the R circuit = H level, corresponding NOR
When the output of the circuit = L level, it is turned off, and when the reference voltage is selected, only one of the analog switches is turned on.
It is said that

Further, in FIG. 26, 74 ₁ to 74 ₄ are turned on and off by the control signal T2 output from the control circuit 7.
These analog switches 74 ₁ to 74 ₄ are F-controlled analog switches, and all the selectors 57 _{1 to} 5 ₄ have a reference voltage corresponding to a digital image signal of one line.
When they are output from 7 ₄ , they are turned on at the same time.

Further, 75 ₁ to 75 ₄ are selectors 57 _{1 to} 5
A capacitor that holds the reference voltage selected by 7 ₄ ,
Reference numerals 76 _{1 to} 76 ₄ are buffers composed of operational amplifiers for sending the reference voltages held by the capacitors 75 ₁ to 75 ₄ to the data lines X _{1 to} X ₄ .

Reference numeral 77 denotes an integrated circuit gate driver for driving the gate lines Y _{1 to} Y ₄ , and T 3 denotes a start signal CK 2 having the same period as the vertical synchronizing signal VS output from the control circuit 7. Is a clock signal having the same period as the horizontal synchronizing signal HS output from the control circuit 7.

Reference numeral 78 is a serial input / parallel output type shift register having a 4-bit structure for shifting the start signal T3 in 1-bit units in synchronization with the clock signal CK2 and outputting the gate drive signals DV _{1 to} DV ₄ . 79 _{1-79 4}
Is a driver for driving the gate lines Y _{1 to} Y ₄ .

[0026] In this liquid crystal display device, a digital image signal D _IN, after being held in the memory circuit 27 ₁ to 27 ₄ for each digital image signal D _IN of the pixel decoder 28 _{1-28 4}
Is decoded with.

[0027] Then, based on the decoding result, the selector 57 ₁ to 57 _4, the reference voltage of the voltage value corresponding to the digital image signal D _IN of the pixel is selected, these selected reference voltage capacitor 75 ₁ 75 ₄ is held, and is further transmitted to the data lines X ₁ to X ₄ via a buffer 76 ₁ to 76 _4.

On the other hand, since the gate driver 77 sets _one of the gate lines Y _{1 to} Y _{4 to} the H level, all the TFTs in this line are turned ON.
And buffers 76 _{1 to} 7 are provided on the respective pixel electrodes of this line.
The reference voltage sent from 6 ₄ is applied as an analog image signal. Thereafter, the same operation is sequentially repeated for each line, and the liquid crystal display panel 1 displays an image corresponding to the digital image signal D _IN .

FIG. 29 is a diagram showing an example of mounting the data driver (DD) 25 and the gate driver (GD) 77 on the liquid crystal display panel 1 in an actual product, 80
Is a glass substrate, and 81 is a glass substrate having a larger area than the glass substrate 80.

Pixels are formed in the opposing portions of the glass substrates 80 and 81, and the data driver 25 and the gate driver 77 are the peripheral portions of the glass substrate 81 that do not overlap with the glass substrate 80, so-called liquid crystal. It is mounted on the frame portion 82 of the display panel 1.

FIG. 30 is an enlarged view showing a part of the frame portion 82 of the liquid crystal display panel 1 in FIG.
DR3 to DR0 are red image signals, DG3 to DG0 are green image signals, and DB3 to DB0 are blue image signals. The reference line as a return line is not shown.

Second Conventional Example ... FIG. 31 FIG. 31 is a diagram schematically showing a circuit configuration of a second conventional example of a liquid crystal display device including an active matrix type liquid crystal display panel.

This liquid crystal display device differs from the liquid crystal display device of the first conventional example shown in FIG. 26 in that the data shown in FIG.
Data driver 83 having a circuit configuration different from that of the driver 25
Other points are the same as those of the liquid crystal display device of the first conventional example shown in FIG.

Here, the first difference of the data driver 83 from the data driver 25 shown in FIG. 26 is a memory for re-holding the digital image signal D _IN held in the memory circuits 27 _{1 to} 27 _4. Circuits 84 _{1 to} 84 ₄ are provided, and the decoders 28 _{1 to} 28 ₄ are provided with these memory circuits 84 ₁
It is configured to decode the digital image signal D _IN held again at ˜84 ₄ .

These memory circuits 84 _{1 to} 84 ₄ are arranged such that when the digital image signal D _IN of one line is held in the memory circuits 27 _{1 to} 27 ₄ , before the digital image signal D _IN of the next line arrives. It is a 4-bit capacity memory circuit which holds the digital image signal D _IN held in these memory circuits 27 _{1 to} 27 ₄ under the control of the control signal T2 at the same time.

The second difference of the data driver 83 from the data driver 25 shown in FIG. 26 is that the analog switches 74 ₁ to 74 ₄ and the capacitor 75 shown in FIG.
_{1-75 4} and not provided a buffer 76 ₁ to 76 _4, as the data lines X ₁ the output of the selector 57 ₁ to 57 ₄
A point that is configured to deliver a to X _4.

The memory in this liquid crystal display device, a digital image signal D _IN, after being held in the memory circuit 27 ₁ to 27 ₄ for each digital image signal D _IN of the pixel, for each digital image signal D _IN for one line It is held again in the circuits 84 _{1 to} 84 ₄ and decoded by the decoders 28 _{1 to} 28 ₄ .

[0038] Then, based on the decoding result, the selector 57 ₁ to 57 _4, the reference voltage of the voltage value corresponding to the digital image signal D _IN of the pixel is selected, these selected reference voltage to a data line X It is sent to _{1 to} X ₄ .

On the other hand, since the gate driver 77 sets _one of the gate lines Y _{1 to} Y _{4 to} the H level, all the TFTs in this line are turned on.
And the selectors 57 _{1 to} 5 are attached to the respective pixel electrodes of this line.
The reference voltage sent from 7 ₄ is applied as an analog image signal. Thereafter, the same operation is sequentially repeated for each line, and the liquid crystal display panel 1 displays an image corresponding to the digital image signal D _IN .

[0040] Here, in the liquid crystal display device, since the performing 16 gradation display, (see analog switches 58 to 73 in FIG. 28) the selector 57 _1-57 16 analog switches each of the ₄ Are arranged.

Therefore, for example, if the number of pixels is 1920 (horizontal)
In the case of x480 (vertical), 1920 selectors are required as selectors for selecting the reference voltage, and therefore 1920 × 16 = 30720 analog switches are required as analog switches constituting these selectors. I will end up.

Further, for example, in the case of performing full-color display for displaying 260,000 colors, it is necessary to display 64 gradations in each pixel. In this case, 64 selectors are provided for each selector for selecting a reference voltage. Need analog switch.

Therefore, for example, if the number of pixels is 1920 (horizontal)
In the case of × 480 (vertical), 192 is used as an analog switch which constitutes a selector for selecting a reference voltage.
0x64 = 122880 analog switches are required.

As described above, in this liquid crystal display device, when the number of gradations is increased, the number of analog switches constituting the selector for selecting the reference voltage becomes huge,
When integrating the data driver 83 into an integrated circuit, there is a problem that the chip area increases and the cost of the data driver 83 increases, which causes the cost of the liquid crystal display device to increase.

Further, in this liquid crystal display device, when the number of gray scales is increased, the circuit scale of the reference voltage source 8 also becomes large, which also causes a problem of cost increase. A liquid crystal display device that solves such a problem is a liquid crystal display device of a third conventional example described below.

32 to 37. FIG. 32 is a diagram schematically showing a circuit configuration of a third conventional example of a liquid crystal display device including an active matrix type liquid crystal display panel.

This liquid crystal display device is different from the liquid crystal display device of the second conventional example shown in FIG. 31 in that the control circuit 7, the reference voltage source 8, and the data driver 83 shown in FIG. 31 have different circuit configurations. A point 85 is provided with a reference voltage source 86 and a data driver 87, and other points are the same as those of the liquid crystal display device of the second conventional example shown in FIG.

The control circuit 85 differs from the control circuit 7 shown in FIG. 31 in that it outputs a clock signal CK3 to be supplied to a counter described later and a control signal T4 to be supplied to a D flip-flop described later. The other points are the same as those of the control circuit 7 shown in FIG.
Is configured similarly to.

Further, the reference voltage source 86 is reset by the control signal T2, and a 2-bit counter 88 for counting the clock signal CK3 and the output [D1C, D0C] of the counter 88 are converted into a positive analog voltage. D
/ A conversion circuit 89, individual reference voltage sources 90 to 93 that output reference voltages VR4 to VR1, and output of the D / A conversion circuit 89 and reference voltages VR4 to VR1 output from individual reference voltage sources 90 to 93. Of the reference voltage VA4 to V
And adding circuits 94 to 97 for outputting A1.

In the D / A conversion circuit 89, the output [D1C, D0C] of the counter 88 is [0, 0], [0,
1], [1, 0], and [1, 1] are 0, respectively.
[V], 0.2 [V], 0.4 [V], and 0.6 [V] are output.

The individual reference voltage sources 90, 91, 92,
Reference numeral VR3 denotes a reference voltage VR4, VR3, VR2, and VR1, which are 4.2 [V], 3.4 [V], and 2.6, respectively.
It is configured to output [V] and 1.8 [V].

FIG. 33 is a time chart showing the operation of the reference voltage source 86, and FIG. 33 (A) shows the counter 8
Control signal T2 supplied as reset signal to FIG.
3 (B) shows a clock signal CK3 supplied as a signal to be counted by the counter 88. This clock signal CK3 indicates that the counter 88 has 1 within one horizontal period.
It has a waveform that counts cycles.

Further, FIG. 33 (C) shows the output [D1C, D0C] of the counter 88, and FIG. 33 (D) shows addition circuits 94-9.
7 shows the reference voltages VA4 to VA1 output from No. 7.

[0054] Moreover, it is different from the data driver 83 to the data driver 87 shown in FIG. 31, the decoder 28 _{1-28 4} shown in FIG. 31, the selector 57 ₁ to 57 ₄ decoders 98 ₁ to the different circuit configuration from the 98 _4, selector 99 _1-9
9 ₄ in that the is provided, and, the comparison circuit 100 _1-10 not provided in the data driver 83 shown in FIG. 31
0 ₄ , D flip-flops 101 _{1 to} 101 ₄ , and analog switches 102 _{1 to} 102 ₄ are provided, and the other components are the same as those of the data driver 83 shown in FIG. Note that R _{1 to} R ₄ are comparison circuits 10
0 _{1 to} 100 ₄ outputs, K _{1 to} K ₄ are D flip-flops 1
01 _1-101 a positive phase output of _4.

Here, the decoders 98 _{1 to} 98 ₄ have the same circuit configuration, and the decoder 98 ₁ is configured as shown in FIG. 34 as a representative. 10 in the figure
Reference numerals 3 and 104 denote inverters, and 105 to 108 denote NOR circuits.

Further, the selectors 99 _{1 to} 99 ₄ have the same circuit configuration. If the selector 99 ₁ is shown as a representative,
It is configured as shown in FIG. In the figure, 109-1
12 is an analog switch.

[0057] Here, the upper two bits of the digital image signal D _IN [D3, D2] is input to the decoder 98 _1, and the output of the decoder 98 ₁ of the NOR circuit 105 to 108, analog switches 109 of the selector 99 ₁ ~ 112 O
Table 1 shows the relationship between N and OFF and the selected reference voltages VA4 to VA1.

[0058]

[Table 1]

Further, the comparison circuits 100 _{1 to} 100 ₄ have the digital image signals D _IN held in the memory circuits 84 _{1 to} 84 _4.
Lower two bits [D1, D0] of the
Output [D1C, D0C] and the comparison result R
The ₁ to R ₄ and supplies to the reset input terminal R of the D flip-flop 101 ₁ to 101 _4.

When the lower 2 bits [D1, D0] of the digital image signal D _IN and the output [D1C, D0C] of the counter 88 match, the comparison circuits 100 _{1 to} 100 ₄ compare results R ₁ to When the H level is output as R ₄ , and the lower 2 bits [D1, D0] of the digital image signal D _IN do not match the output [D1C, D0C] of the counter 88, the comparison results R _{1 to} R ₄ are L. It is configured to output the level.

Further, the analog switches 102 ₁ to 10
2 ₄ is turned on and off by the positive phase outputs K _{1 to} K ₄ obtained at the positive phase output terminals Q of the D flip-flops 101 _{1 to} 101 _4.
Is controlled, and ON when the positive phase outputs K _{1 to} K ₄ = H level, respectively, and OF when the normal phase outputs K _{1 to} K ₄ = L level.
It is assumed to be F.

FIG. 35 shows the comparison circuits 100 ₁ and D.
35 is a time chart showing the operation of the flip-flop 101 ₁ , FIG. 35 (A) is a control signal T2, FIG. 35 (B) is a clock signal CK3, and FIG. 35 (C) is an output [D1C, D0C] of the counter 88. 35 (D) is a control signal T supplied as a set signal to the D flip-flop 101 _1.
4 is shown.

FIG. 35E shows the digital image signal D
_IN lower two bits of [D1, D0] is [0,0] Output R ₁ and D flip-flop 10 of the comparator circuit 100 ₁ in the case of
Shows a positive-phase output K ₁ 1 _1.

FIG. 35F shows the digital image signal D
_IN lower two bits of [D1, D0] is [0,1] Output R ₁ and D flip-flop 10 of the comparator circuit 100 ₁ in the case of
Shows a positive-phase output K ₁ 1 _1.

Further, FIG. 35G shows a digital image signal D
_IN lower two bits of [D1, D0] is [1,0] Output R ₁ and D flip-flop 10 of the comparator circuit 100 ₁ in the case of
Shows a positive-phase output K ₁ 1 _1.

Further, FIG. 35H shows the digital image signal D
_IN lower two bits of [D1, D0] is [1,1] Output R ₁ and D flip-flop 10 of the comparator circuit 100 ₁ in the case of
Shows a positive-phase output K ₁ 1 _1.

[0067] Therefore, the digital image signal D _IN and relationships and D flip-flop 101 ₁ of the positive-phase output K ₁ and the analog switch (SW) and the reference voltage output to the data line X ₁ 102 ₁ ON, OFF state Figure 3 shows the relationship between
As shown in 6.

Incidentally, FIG. 36 (A) shows the digital image signal D
The relationship between _IN and the reference voltage output to the data line X ₁ ,
Figure 36 (B) is D flip-flop 101 ₁ of the positive-phase output K ₁ and the analog switch 102 ₁ ON, the shows the relationship between the OFF state.

Digital image signal D _IN and data line X ₂
Relationship and D flip-flop 101 _{2-101 4} positive phase output K ₂ ~K ₄ and the analog switch 102 _{2-102 4} ON the reference voltage output to to X _4, the relationship of the OFF state, similarly a is there.

[0070] Memory in this liquid crystal display device, a digital image signal D _IN, after being held in the memory circuit 27 ₁ to 27 ₄ for each digital image signal D _IN of the pixel, for each digital image signal D _IN for one line It is held in the circuits 84 _{1 to} 84 ₄ .

Then, the upper 2 bits [D of the digital image signal D _IN held in these memory circuits 84 _{1 to} 84 ₄ [D
3, D2] are decoded by the decoders 98 _{1 to} 98 ₄ , and in each of the selectors 99 _{1 to} 99 ₄ , any one of the analog switches is turned on and the reference voltage VA4 to
One of VA1 is selected.

At the start of the horizontal period, the D flip-flops 101 _{1 to} 101 ₄ are preset with the control signal T4 = “H” and the positive phase outputs K _{1 to} K ₄ = “H” are set. When the horizontal period starts, the analog switch 102
_{1 to} 102 ₄ = ON, and the data lines X _{1 to} X ₄ have the reference voltages VR4, VR3, VR2 or VR1 for the time being.
Rise towards.

On the other hand, the lower 2 bits [D1, D of the digital image signal D _IN output from the memory circuits 84 _{1 to} 84 ₄ are
0] is supplied to the comparison circuits 100 _{1 to} 100 ₄ and compared with the output [D1C, D0C] of the counter 88.

Here, the comparison circuit 100 _j (j = 1 to 4)
In the case where the lower 2 bits [D1, D0] of the digital image signal D _IN output from the memory circuit 84 _j and the output [D1C, D0C] of the counter 88 match and then do not match, the D flip-flop 101 _j Positive phase output of K _J =
It becomes L level and analog switch 102 _j = OFF
And the voltage of the data line X _j is the reference voltage VA at the time when the analog switch 102 _j = OFF.
4, VA3, VA2 or VA1.

On the other hand, one of the gate lines Y _{1 to} Y ₄ is set to the H level by the gate driver 77, so that all the TFTs in this line are turned on.
And each of the pixel electrodes on this line has selectors 99 _{1 to} 9
The reference voltage sent from 9 ₄ is applied as an analog image signal. Thereafter, the same operation is sequentially repeated for each line, and the liquid crystal display panel 1 displays an image corresponding to the digital image signal D _IN .

Here, for example, in FIG. 37, the pixel electrode 2 ₁₁
As the digital image signal D _IN corresponding to [D3, D2,
D1, D0] = [1,1,1,0] is a time chart illustrating a voltage change of the pixel electrode 4 ₁₁ when input, FIG. 37 (A) is outputted from the selector 99 ₁ Changes in the reference voltage, FIG. 37 (B) shows the ON / OFF state of the analog switch 102 ₁ , FIG. 37 (C) shows the voltage change of the data line X ₁ , and FIG. 37 (D) shows the voltage change of the pixel electrode 4 _11. Shows.

In this case, the reference voltage output from the selector 99 ₁ is VA4 as shown in FIG.
As is clear from 3 (D), 4.2 [V] → 4.4
It changes as [V] → 4.6 [V] → 4.8 [V].

Further, the analog switch 102 ₁ is turned off.
In the N and OFF states, the lower 2 bits [D1, D0] = [1, 0] of the digital image signal D _IN are shown in FIG.
As is apparent from FIG. 37B, it becomes as shown in FIG.

Therefore, the voltage of the data line X ₁ is as shown in FIG.
As shown in 7 (C), 4.2 [V] → 4.4 [V] →
It rises stepwise like 4.6 [V] and data line X ₁
It is held at 4.6 [V] by the parasitic capacitance of.

As a result, the voltage of the pixel electrode 4 ₁₁ first rises toward 4.2 [V], and then 4.4 [V].
, And finally rises to 4.6 [V] and stabilizes at 4.6 [V], and the digital image signal D _IN =
The gradation display corresponding to [D3, D2, D1, D0] = [1,1,1,0] is performed.

According to this liquid crystal display device, the number of analog switches forming the selectors 99 _{1 to} 99 ₄ for selecting the reference voltage forming the data driver 87 can be reduced, so that the data driver 87 can be reduced. When the LSI is integrated into an LSI, the chip area is reduced and the data driver 8
7, the cost of the liquid crystal display device itself can be reduced.

Further, since it is sufficient for the reference voltage source 86 to provide the four individual reference voltage sources 90 to 93, the counter 88,
Even if the D / A conversion circuit 89 and the adding circuits 94 to 97 are provided, the circuit configuration can be simpler than that of the reference voltage source 8 shown in FIG. 31, and from this point as well, the cost of the liquid crystal display device can be reduced. Can be achieved.

[0083]

Here, in the liquid crystal display device of the first conventional example shown in FIG. 26, as shown in FIG. 30, the frame portion 82 of the liquid crystal display panel 1 on which the data driver 25 is mounted is mounted. Since the number of signal lines to be formed is large, the area of the frame portion 82 of the liquid crystal display panel 1 becomes large, which reduces the value as a product and has been a problem.

Further, in the liquid crystal display device of the third conventional example shown in FIG. 32, the T formed on the liquid crystal display panel 1 is used.
If the leakage current of FT6 _{11 to} 6 ₄₄ is large, the data line X
There is a problem that the voltage of _{1 to} X ₄ is lowered and it becomes impossible to perform gradation display corresponding to the digital image signal D _IN supplied from the outside.

Note that, in FIG. 37C, the alternate long and two short dashes line W ₁
Shows an example in which the voltage of the data line X ₁ drops, and the chain double-dashed line W ₂ in FIG. 37 (D) shows the corresponding voltage change of the pixel electrode 4 ₁₁ .

In view of the above point, the present invention is directed to a liquid crystal display device which is capable of reducing the frame area of the liquid crystal display panel to downsize the device and increasing the product value of the liquid crystal display device. Also, even when the leakage current of the TFT formed in the liquid crystal display panel is large, gradation display corresponding to a digital image signal supplied from the outside can be performed to enhance the product value as a liquid crystal display device. It is an object of the present invention to provide a liquid crystal display device having

[0087]

FIG. 1 shows the first embodiment of the present invention.
FIG. 3 is a diagram showing in principle the circuit configuration of the liquid crystal display device of the invention of FIG. 1, in which D _IN is a digital image signal, D _m , D _m-1 , D _0.
Are the 2 ^m-th bit and 2 ^{m-1 of the} digital image signal D _IN , respectively.
Bit, 2 ⁰ bit of the _{signal, V n, V n-1} , V nm, V
_nm-1, V ₁ is the reference voltage.

Reference numeral 113 denotes a pixel electrode provided for each pixel, a common electrode commonly provided for all pixels, and a switching provided for each pixel electrode to supply an analog image signal to the pixel electrode. It is an active matrix type liquid crystal display panel including an element.

[0089] Further, 114 a plurality of reference voltages V _n ~V ₁ of different digital image signals D _IN and the voltage value is supplied, from among the plurality of reference voltages V _n ~V ₁ into a digital image signal D _{I N} A reference voltage having a corresponding voltage value is selected, and the selected reference voltage is used as an analog image signal on the liquid crystal display panel 1.
It is a data driver that sends data to 13 data lines.

Reference numeral 115 switches some or all of the bits of the digital image signal D _IN and some or all of the plurality of reference voltages V _{n to} V ₁ to switch some or all of these digital image signals D _IN. It is a switching circuit that supplies a part or all of a bit and a plurality of reference voltages V _{n to} V ₁ to the data driver 114 via the same signal line group 116.

In FIG. 1, when m <n, all the bits D _{m to} D ₀ of the digital image signal D _IN and some of the plurality of reference voltages V _{n to} V ₁ are V _{n to} V _nm . And all the bits D _{m to} D _{0 of} these digital image signals D _{IN and} a part of the plurality of reference voltages V _{n to} V ₁ V _{n to} V _nm are in the same signal line group 1.
A case where the data driver 114 is supplied via 17 is shown.

Further, FIG. 2 is a diagram showing in principle the circuit configuration of the liquid crystal display device of the second invention in the present invention.
Reference numeral 117 is a reference voltage output circuit that outputs a plurality of reference voltages V _{n to} V ₁ having different voltage values, and 118 is a staircase voltage output circuit that outputs a staircase voltage that changes stepwise multiple times within one horizontal period. is there.

Reference numeral 119 adds a plurality of reference voltages V _{n to} V ₁ output from the reference voltage output circuit 117 and the staircase wave voltage output from the staircase wave voltage output circuit 118 to obtain a plurality of voltage values different from each other. This is an adder circuit that outputs the staircase voltage multiple times within one horizontal period.

Reference numeral 120 designates a plurality of one voltage corresponding to the digital image signal D _IN among one of the plurality of staircase voltages output from the adder circuit 119 within one horizontal period. It is a data driver which selects a plurality of times and sends one voltage corresponding to the selected digital image signal D _IN to the data line of the liquid crystal display panel 113 as an analog image signal.

[0095]

In the first aspect of the invention, the switching circuit 115 is provided, and a part or all of the bits of the digital image signal D _IN ,
Some or all of the plurality of reference voltages V _{n to} V ₁ are switched, and some or all of the bits of the digital image signal D _IN and some or all of the plurality of reference voltages V _{n to} V ₁ are the same. The data driver 114 is supplied via the signal line group 116.

As a result, a comparison is made when all the bits D _{m to} D _{0 of} the digital image signal D _IN and all the reference voltages V _{n to} V ₁ are supplied to the data driver 114 by separate signal lines. The number of signal lines to be formed in the frame portion of the liquid crystal display panel 113 can be reduced, and the liquid crystal display panel 1
The area of the frame portion of 13 can be reduced.

In addition, in the second invention, the adder circuit 1
A single voltage corresponding to the digital image signal D _IN is selected from a plurality of staircase voltages among the plurality of staircase voltages output from the A / D converter 19 a plurality of times within one horizontal period, and the selected digital signal is selected. One voltage corresponding to the image signal D _IN is sent to the data line of the liquid crystal display panel 113 as an analog image signal.

[0098] Consequently, even if the leakage current of the TFT formed in the liquid crystal display panel 113 is large, increased to a voltage corresponding to the voltage of the pixel electrode into a digital image signal D _IN, a digital image signal D _IN It is possible to perform gradation display corresponding to.

[0099]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The first embodiment of the present invention will be described below with reference to FIGS.
Examples to 8th Example will be described. In addition, in FIGS. 3, 5, 7, and 8, parts corresponding to those in FIG. 26 are denoted by the same reference numerals, and redundant description thereof will be omitted.
21 and 24, portions corresponding to those in FIG. 32 are designated by the same reference numerals, and duplicate description thereof will be omitted.

First Embodiment ... FIG. 3 and FIG. 4 FIG. 3 is a diagram schematically showing the circuit configuration of the first embodiment of the present invention. The liquid crystal display device of the first embodiment is shown in FIG. The liquid crystal display device of the first conventional example shown in FIG.

The liquid crystal display device of the first embodiment is shown in FIG.
26 is different from the first conventional liquid crystal display device shown in FIG.
26, a control circuit 121 and a data driver 122 having different circuit configurations from the control circuit 7 and the data driver 25 are provided, and a switching circuit not provided with the liquid crystal display device of the first conventional example shown in FIG. Other than that, the configuration is the same as that of the liquid crystal display device of the first conventional example shown in FIG.

Here, the control circuit 121 differs from the control circuit 7 shown in FIG. 26 in that it is configured to output a control signal T5 for controlling the switching circuit 123. The control circuit 7 shown in FIG.

Further, the switching circuit 123 inputs the digital image signal D _IN supplied from the outside and V16 to V13 of the reference voltages V16 to V1 output from the reference voltage source 8 and inputs it to the control signal T5. The switching operation is performed under the control of the digital image signal D _IN or the reference voltages V16 to V13.
Of the digital image signal D _IN and the reference voltages V16 to V13 by using the same signal line group 124.
Is supplied to the data driver 122 in a time division manner.

That is, in the first embodiment, the reference voltage source 8
Among the reference voltages V16 to V1 output from the reference voltages V16 to V13, the reference voltages V16 to V13 are supplied to the data driver 122 via the switching circuit 123, and the reference voltages V12 to V1 are directly supplied to the data driver 122.

Here, the switching circuit 123 controls the control signal T
When 5 = H level, the digital image signal D _IN is output,
When the control signal T5 = L level, the reference voltages V16 to V1
It is configured to input 3.

The period in which the control signal T5 is at the H level is the period in which the digital image signal D _IN is supplied from the image signal source, and the period in which the control signal T5 is at the L level is the digital image signal D _IN. Is a period in which the supply from the image signal source is stopped.

The data driver 122 differs from the data driver 25 shown in FIG. 26 in that the switching circuit 1
The digital image signal D _IN and reference voltage V16~V13 supplied in time division from 23 is the point that is configured to be supplied to the memory circuit 27 ₁ to 27 ₄ and a selector 57 _{1-57 4,} other About Is the data shown in FIG.
It is configured similarly to the driver 25.

[0108] That is, of the analog switches constituting the selector 57 ₁ to 57 _4, the reference voltage V16~V13 the analog switch to select each bit signal D3~D0 and the reference voltage of the digital image signal D _IN V16
~ V13 is supplied in a time division manner.

FIG. 4 is a time chart showing the operation of the first embodiment, where D _{11 to} D ₁₄ are the pixels 2 _{11 on} the first line.
Digital image signals for ~2 _14, D ₂₁ ~D ₂₄ shows a digital image signal to the pixel 2 _{21-2 24} of the second line.

Since the control signal T5 is set to the H level during the period when the digital image signal D _IN is supplied from the image signal source, as described above, the switching circuit 123 outputs the digital image signals D _{11 to} D ₁₄ to each other. When sequentially transmitted, these digital image signals D _{11 to} D ₁₄ are output and supplied to the data driver 122.

As a result, the digital image signals D _{11 to} D
Reference numeral ₁₄ designates memory circuits 27 _{1 to} 27 _{4 in} order in synchronization with the timing signals TS _{1 to} TS ₄ output from the shift register 26.
After being held in, is decoded by the decoder 28 _{1-28 4,} in the selector 57 ₁ to 57 _4, analog switches provided corresponding to the reference voltage to be selected O
N.

[0112] At this point, the analog switch to select the reference voltage V16~V13 selectors 57 ₁ to 57 _4, respectively the digital image signal D ₁₁ signals of each bit of to D ₁₄ D3-D0 is supplied But these signals D3
Even if any one of D0 to D0 is selected, the control signal T2
= L level, the analog switches 74 ₁ to 74 ₄ are O
Since it is FF, no problem occurs.

After that, when the supply of the digital image signal D _{IN from} the image signal source is stopped and the control signal T5 is set to the L level, the switching circuit 123 replaces the digital image signals D _{11 to} D ₁₄ . The reference voltages V16 to V13 are output, and these reference voltages V16 to V13 are output to the memory circuit 27.
It is supplied to the analog switch for selecting the reference voltage V16~V13 of _{1-27 4} data input terminal and the selector 57 ₁ to 57 _4.

In this case, the memory circuits 27 _{1 to} 27 ₄ have
Since the timing signals TS _{1 to} TS ₄ are not supplied, the reference voltages V16 to V13 are not input to the memory circuits 27 _{1 to} 27 ₄ .

[0115] On the other hand, the selector 57 ₁ to 57 _4, respectively, selection of the reference voltage corresponding to the digital image signal D ₁₁ to D ₁₄ is performed, these selected reference voltage selectors 5
Outputted from 7 _{1-57 4.}

Then, the control signal T2 becomes H level,
Is the analog switches 74 ₁ ~74 ₄ = ON, the reference voltage outputted from the selector 57 ₁ to 57 ₄ are capacitors 7
5 ₁ to 75 ₄ and is sent to the data lines X _{1 to} X ₄ via the buffers 76 _{1 to} 76 ₄ .

On the other hand, since _one gate line among the gate lines Y _{1 to} Y ₄ is set to the H level by the gate driver 77, all the TFTs in this line are turned on.
And buffers 76 _{1 to} 7 are provided on the respective pixel electrodes of this line.
The reference voltage sent from 6 ₄ is applied as an analog image signal. Thereafter, the same operation is sequentially repeated for each line, and the liquid crystal display panel 1 displays an image corresponding to the digital image signal D _IN .

Here, in the first embodiment, a switching circuit 123 is provided and the digital image signal D _{IN is transferred} to the data
Signal line group to be supplied to the driver 122 and the reference voltage V1
6 to V13 can share a signal line group to be supplied to the data driver 122.

Therefore, according to the first embodiment, as the signal lines to be formed in the frame portion 82 of the liquid crystal display panel 1, when the data driver 122 is mounted on the upper and lower sides, eight signal lines are reduced. Therefore, the area of the frame portion 82 of the liquid crystal display panel 1 can be reduced by this amount, the device can be downsized, and the product value of the liquid crystal display device can be increased.

Second Embodiment ... FIG. 5 and FIG. 6 FIG. 5 is a diagram schematically showing a circuit configuration of a second embodiment of the present invention. The liquid crystal display device of the second embodiment is shown in FIG. The present invention is to improve the liquid crystal display device of the first embodiment shown in FIG.

The liquid crystal display device according to the second embodiment is different from the liquid crystal display device according to the first embodiment shown in FIG. 3 in that the control circuit 121 and the data driver 122 shown in FIG. 3 have different circuit configurations. A circuit 125 and a data driver 126 are provided, and the other points are configured similarly to the liquid crystal display device of the first embodiment shown in FIG.

Here, the control circuit 125 is different from the control circuit 121 shown in FIG. 3 in that the control circuit 125 is configured to output a control signal T6 for controlling the decoding operation of the decoder described later. Are configured similarly to the control circuit 121 shown in FIG. The control signal T
6 is a signal that changes similarly to the control signal T5.

In addition, the data driver 126 is shown in FIG.
The difference from the data driver 122 shown is shown in FIG.
Decoder 28₁~ 28_FourDecoder 1 with different circuit configuration
27 ₁~ 127_FourAbout the other
Is configured similarly to the data driver 122 shown in FIG.
Has been.

These decoders 127 _{1 to} 127 ₄ have the same circuit configuration, and the decoder 127 ₁ is configured as shown in FIG. 6 as a representative. Here, this decoder 127 ₁ is an improvement of the decoder 28 ₁ shown in FIG. 28. Instead of the 2-input NAND circuits 33 to 40 shown in FIG. 28, the decoder 127 ₁ has a 3-input gate having a control signal T6. The NAND circuits 128 to 135 are provided, and the other parts are configured similarly to the decoder 28 ₁ shown in FIG.

That is, these decoders 127 _{1 to} 127
₄ does not perform the decoding operation when the control signal T6 = H level, all outputs thereof are at L level, and the selector 57
The analog switches _{1-57 4} and all OFF, when the control signal T6 = L levels are configured to perform a decoding operation in the same manner as the decoder 28 _{1-28 4} shown in FIG. 3 .

Since the control signal T6 is a signal which changes like the control signal T5, the digital image signal D _IN is output from the switching circuit 123, and the memory circuits 27 ₁ ...
27 ₄ holds the digital image signal D _IN , the control signal T6 = H level, and the decoders 127 _{1 to} 12
7 ₄ = selector 57 _{1 to} 57 _{4 in the} decoding operation disabled state
All analog switches in the inside are turned off.

On the other hand, when the switching circuit 123 outputs the reference voltages V16 to V13, the control signal T
6 = the L level, the decoder 127 _{1-127 4} = in decoding operation state, is an analog switch = selectable state of the selector 57 ₁ to 57 _4.

Since the switching circuit 123 is provided in the second embodiment as in the case of the first embodiment, the area of the frame portion 82 of the liquid crystal display panel 1 can be reduced to downsize the device. , it is possible to increase the product value of the liquid crystal display device, when writing the digital image signal D _iN outputted from the switching circuit 123 to the memory circuit 27 ₁ to 27 _4, the analog selector 57 _{1-57 4} Since all the switches are turned off, the selector 5
7 _1-57 for _fourth output capacity, the digital image signal D _IN
It is possible to prevent a delay in the transmission of the data.

Third Embodiment FIG. 7 FIG. 7 is a diagram schematically showing the circuit configuration of a third embodiment of the present invention. The liquid crystal display device of the third embodiment is shown in FIG. This is to improve the liquid crystal display device of the first embodiment.

The liquid crystal display device of the third embodiment differs from the liquid crystal display device of the first embodiment shown in FIG. 3 in that instead of the control circuit 121 shown in FIG. 3, the control circuit 12 shown in FIG.
5 is provided, and a data driver 136 having a circuit configuration different from that of the data driver 122 shown in FIG. 3 is provided. Other points are the liquid crystal display of the first embodiment shown in FIG. It is constructed similarly to the device.

Here, the data driver 135 is shown in FIG.
The difference from the data driver 122 shown in FIG. 6 is that a switch circuit 137 is provided.
It is configured similarly to the data driver 122 shown in FIG.

This switch circuit 137 controls the control signal T6.
= H level, it is turned off and the switching circuit 1
Selector 5 for digital image signal D _IN output from 23
7 _1-57 blocks the transmission to _4, the control signal T6 = an ON state when the L level, switching the selector 57 ₁ to 57 ₄ of the reference voltage V16~V13 output from circuit 123
It is possible to transmit to.

Since the switching circuit 123 is provided in the third embodiment as in the case of the first embodiment, the area of the frame portion 82 of the liquid crystal display panel 1 is reduced and the size of the device is reduced. , The product value of the liquid crystal display device can be increased, and the switch circuit 137 is turned off when the digital image signal D _IN output from the switching circuit 123 is written in the memory circuits 27 _{1 to} 27 _4. Therefore, as in the case of the second embodiment, the selector 5
7 _{1-57 4} even when the analog switch to be ON was present, because of its output capacity, the digital image signal D
It is possible to prevent a delay in the transmission of _IN .

Fourth Embodiment FIG. 8 FIG. 8 is a diagram schematically showing the circuit configuration of a fourth embodiment of the present invention. The liquid crystal display device of the fourth embodiment is shown in FIG. This is to improve the liquid crystal display device of the second embodiment.

The liquid crystal display device of the fourth embodiment differs from the liquid crystal display device of the second embodiment shown in FIG. 5 in that the data driver 126 shown in FIG.
The driver 138 is provided, and the other points are the same as those of the liquid crystal display device of the second embodiment shown in FIG.

[0136] is different from the data driver 126 shown this data driver 138 in FIG. 5, the capacitor 75 _{1-75 4} shown in FIG. 5, is not provided a buffer 76 ₁ to 76 _4, the selector 57 ₁ to 57 as ₄ outputs through the analog switch _{72d 4} data lines X ₁ to X ₄
The other points are similar to those of the data driver 126 shown in FIG.

Since the switching circuit 123 is provided in the fourth embodiment as in the case of the first embodiment, the area of the frame portion 82 of the liquid crystal display panel 1 can be reduced to downsize the device. In addition to enhancing the product value of the liquid crystal display device, when writing the digital image signal D _IN output from the switching circuit 123 into the memory circuits 27 _{1 to} 27 _{4 as} in the case of the second embodiment. , Decoder 127 ₁
Can be the all OFF state analog switches of the selector 57 ₁ to 57 ₄ by 127 _4, for output capacitance of the selector 57 ₁ to 57 _4, a delay occurs in the transmission of digital image signals D _IN Can be prevented.

Fifth Embodiment FIG. 9 to FIG. 15 FIG. 9 is a diagram schematically showing the circuit configuration of the fifth embodiment of the present invention. The liquid crystal display device of the fifth embodiment is shown in FIG. This is to improve the liquid crystal display device of the third conventional example shown in FIG.

The liquid crystal display device of the fifth embodiment is shown in FIG.
32 is different from the liquid crystal display device of the third conventional example shown in FIG.
A control circuit 139 and a data driver 140 having different circuit configurations from the control circuit 85 and the data driver 87 shown in FIG. 32 are provided. Others are the same as those of the liquid crystal display device of the third conventional example shown in FIG. Is configured.

Here, the control circuit 139 is different from the control circuit 85 shown in FIG. 32 in that the counter 88 is used and the clock signal CK4 for making the count 3 cycles within one horizontal period, that is, within one horizontal period. [0,0] → [0,1]
→ [1,0] → [1,1] is to output a clock signal CK4 that should be counted for three cycles, and control signals T7 and T8 for controlling a gate circuit described later. Is configured similarly to the control circuit 85 shown in FIG.

FIG. 10 is a time chart showing the operation of the reference voltage source 86, and FIG. 10 (A) shows the counter 8
8 functions as a reset signal for the memory circuit 8
For 4 _{1-84 4} shows a control signal T2 which functions as a signal indicating a timing of writing.

Further, FIG. 10B shows the clock signal CK4 counted by the counter 88, FIG. 10C shows the output [D1C, D0C] of the counter 88, and FIG. 10D shows the output from the adder circuits 94 to 97. Reference voltage VA4 to V
A1 is shown.

In addition, the data driver 140 is shown in FIG.
Differs from the data driver 87 shown in, instead of the D flip-flop 101 ₁ to 101 ₄ to the data driver 87 shown in FIG. 32 is provided, the gate circuits 141 ₁ to
141 ₄ is a point a is provided, for the rest, is configured similarly to the data driver 87 shown in FIG. 32.

Here, the gate circuits 141 _{1 to} 141 ₄ have the same circuit configuration, and the gate circuit 141 ₁ is configured as shown in FIG. 11 as a representative. 14
2 is a D flip-flop, 143 is an inverter, 144
˜146 are NAND circuits. In addition, in FIG.
E _{1 to} E ₄ are outputs of the gate circuits 141 _{1 to} 141 ₄ .

FIG. 12 is a time chart showing the operation of the comparison circuit 100 ₁ and the gate circuit 141 ₁ , and FIG. 12A shows the gate circuit 141 ₁ shown in FIG.
1 shows a control signal T7 that functions as a preset signal for the D flip-flop 142 shown in FIG.

Further, FIG. 12B shows a control signal T8 for distinguishing the count of the first cycle of the counter 88 from the second and subsequent cycles, and FIG. 12C shows a clock signal C.
K4, FIG. 12D shows the output of the counter 88 [D1C, D
0C] is shown.

FIG. 12E shows the digital image signal D
_IN lower two bits of [D1, D0] indicates the output R ₁ and the output E ₁ of the gate circuit 141 ₁ of the comparator circuit 100 ₁ in the case of [0,0].

FIG. 12F shows the digital image signal D
_IN lower two bits of [D1, D0] indicates the output R ₁ and the output E ₁ of the gate circuit 141 ₁ of the comparator circuit 100 ₁ in the case of [0,1].

Further, FIG. 12G shows the digital image signal D
_IN lower two bits of [D1, D0] indicates the output R ₁ and the output E ₁ of the gate circuit 141 ₁ of the comparator circuit 100 ₁ in the case of [1,0].

FIG. 12H shows the digital image signal D
_IN lower two bits of [D1, D0] indicates the output R ₁ and the output E ₁ of the gate circuit 141 ₁ of the comparator circuit 100 ₁ in the case of [1,1].

Further, FIG. 13 shows the clock signal CK4,
An output E ₁ of the gate circuit 141 _1, the analog switch 1
02 ₁ ON, the a view showing the OFF state, the relationship between the reference voltage VA4~VA1 output from the reference voltage source 86, FIG. 13 (A) shows the clock signal CK4.

FIG. 13B shows the digital image signal D
_INWhen the lower 2 bits [D1, D0] of [0, 0] are
Gate circuit 141₁Output E₁And analog switch 1
02 ₁Shows the ON and OFF states of.

FIG. 13C shows the digital image signal D
_INWhen the lower 2 bits [D1, D0] of [0, 1] are
Gate circuit 141₁Output E₁And analog switch 1
02 ₁Shows the ON and OFF states of.

FIG. 13D shows the digital image signal D
_INWhen the lower 2 bits [D1, D0] of [1, 0] are
Gate circuit 141₁Output E₁And analog switch 1
02 ₁Shows the ON and OFF states of.

FIG. 13E shows the digital image signal D
_INWhen the lower 2 bits [D1, D0] of [1, 1] are
Gate circuit 141₁Output E₁And analog switch 1
02 ₁Shows the ON and OFF states of.

Further, FIG. 13F shows addition circuits 94 to 97.
The reference voltages VA4 to VA1 output from the above are shown.

Therefore, the relationship between the digital image signal D _IN and the reference voltage output to the data line X ₁ , the reference voltages VA4 to VA1 output from the reference voltage source 86, and the analog switch (SW) 102 ₁ are set. The relationship between the ON and OFF states is as shown in FIG.

FIG. 14A shows the digital image signal D
The relationship between _IN and the reference voltage output to the data line X ₁ ,
14B shows the reference voltages VA4 to VA1 output from the reference voltage source 86, and FIG. 14C shows the analog switch 1.
The relationship between the ON and OFF states of 02 ₁ is shown.

Digital image signal D _IN and data line X ₂
To the reference voltage output to X ₄ and the reference voltage source 8
The relationship between the reference voltages VA4 to VA1 output from 6 and the ON / OFF states of the analog switches 102 _{2 to} 102 ₄ is the same.

[0160] Incidentally, FIG. 15, for example, as a digital image signal D _IN corresponding to the pixel electrode 2 ₁₁ [D3, D2, D
9 is a time chart for explaining a voltage change of the pixel electrode 4 ₁₁ when [1, D0] = [1, 1, 1, 0] is input.

Here, FIG. 15A shows a voltage change of the reference voltage VA4 output from the selector 99 ₁ , and FIG.
Is the ON / OFF state of the analog switch 102 ₁ , FIG. 15C is the voltage change of the data line X ₁ , FIG.
(D) shows the voltage change of the pixel electrode 4 ₁₁ .

In this case, the reference voltage output from the selector 99 ₁ is VA4 as shown in Table 1, and is shown in FIG.
As is clear from (D), as shown in FIG. 15 (A), 4.2 [V] → 4.4 [V] → 4. 4 within one horizontal period.
6 [V] → 4.8 [V] (above first cycle) → 4.2
[V] → 4.4 [V] → 4.6 [V] → 4.8 [V] (above second cycle) → 4.2 [V] → 4.4 [V] → 4.4
It changes like 6 [V] → 4.8 [V] (above, 3rd cycle).

Also, the analog switch 102 ₁ is turned off.
In the N and OFF states, the lower 2 bits [D1, D0] = [1, 0] of the digital image signal D _IN are shown in FIG.
As is clear from FIG. 15D, it becomes as shown in FIG.

Therefore, the voltage of the data line X ₁ is as shown in FIG.
As shown in FIG. 5 (C), 4.2 [V] → 4.4 [V] →
It rises stepwise like 4.6 [V] and data line X ₁
It is held at 4.6 [V] by the parasitic capacitance of.

As a result, the voltage of the pixel electrode 4 ₁₁ is as shown in FIG.
As shown in (D), first rises to 4.2 [V], then rises to 4.4 [V], and finally 4.6.
It rises toward [V], stabilizes at 4.6 [V], and the digital image signal D _IN = [D3, D2, D1, D0] =
Gradation display corresponding to [1, 1, 1, 0] is performed.

[0166] In the fifth embodiment, for example, when the leakage current of the TFT that is connected to the data lines X ₁ is large, the voltage change of the data line X ₁ is FIG. 15 (C)
As indicated by the chain double-dashed line W ₃ , even if the analog switch 102 ₁ is turned off from 4.6 [V] after the analog switch 102 ₁ is _first turned off, the analog switch 102 ₁ becomes O in the second cycle.
When it becomes N, the voltage is returned to 4.6 [V], and after that, after the analog switch 102 ₁ is turned off,
Analog switch 10 even when lowered from 4.6 [V]
When 2 ₁ is turned on in the 3rd cycle, it is returned to 4.6 [V].

As a result, even if the leakage currents of the TFTs 6 _{11 to} 6 ₄₁ connected to the data line X ₁ are large, the voltage of the pixel electrode 4 ₁₁ is initially 4.2.
Ascend to [V], then to 4.4 [V], and finally to 4.6 [V], 4.
Stable at 6 [V] and digital image signal D _IN = [D3, D
The gradation display corresponding to [2, D1, D0] = [1, 1, 1, 0] is performed.

In the fifth embodiment, since the reference voltage corresponding to the digital image signal D _IN is applied to the data lines X _{1 to} X ₄ three times during one horizontal period, the liquid crystal display panel 1 is not affected. even if the leakage current of the formed by being TFT 6 ₁₁ to 6 ₄₄ is large, it is possible to apply a reference voltage corresponding to the digital image signal D _iN to the pixel electrode 4 _{11-4 44.}

[0169] Thus, according to the fifth embodiment, even when the leakage current of the TFT 6 ₁₁ to 6 ₄₄ to be formed on the liquid crystal display panel 1 is large, performs a gradation display corresponding to the digital image signal D _IN, The product value as a liquid crystal display device can be increased.

Sixth Embodiment FIG. 16 to FIG. 20 FIG. 16 is a diagram schematically showing a circuit configuration of a sixth embodiment of the present invention. The liquid crystal display device of the sixth embodiment is shown in FIG. This is to improve the liquid crystal display device of the fifth embodiment shown.

The liquid crystal display device of the sixth embodiment differs from the liquid crystal display device of the fifth embodiment shown in FIG. 9 in that the reference voltage source 147 has a circuit configuration different from that of the reference voltage source 86 shown in FIG.
Is provided and an inverter 148 which is not provided in the liquid crystal display device of the fifth embodiment is provided. Others are similar to those of the liquid crystal display device of the fifth embodiment shown in FIG. It is configured.

Here, the reference voltage source 147 differs from the reference voltage source 86 shown in FIG. 3 in that instead of the D / A conversion circuit 89 shown in FIG. 9, the output of the counter 88 [D1C, D0
D / A conversion circuit 1 for converting C] into a negative analog voltage value
49, and individual reference voltage sources 90 to 93
Instead of, the individual reference voltage source 1 that outputs the reference voltages VS4 to VS1 having a higher voltage value than the reference voltages VR4 to VR1.
50 to 153, and the other points are configured similarly to the reference voltage source 86 shown in FIG.

In the D / A conversion circuit 149, the output [D1C, D0C] of the counter 88 is [0, 0], [0,
1], [1, 0], and [1, 1] are 0, respectively.
[V], -0.2 [V], -0.4 [V], -0.6
It is configured to output [V].

Further, the individual reference voltage sources 150, 151, 1
52 and 153 are reference voltages VS4, VS3, VS2 and V
As S1, 4.8 [V], 4.0 [V],
It is configured to output 3.2 [V] and 2.4 [V].

FIG. 17 is a waveform diagram showing the operation of the reference voltage source 147. FIG. 17A shows the control signal T2 supplied as a reset signal to the counter 88, and FIG.
17B is the clock signal CK4 counted by the counter 88, and FIG. 17C is the output of the counter 88 [D1
C, D0C] and FIG. 17D show the reference voltages VS4 to VS1 output from the adder circuits 94 to 97.

FIG. 18 is a time chart showing the operation of the comparison circuit 100 ₁ and the gate circuit 141 ₁ provided in the data driver 139. FIG. 18A shows the control signal T7 supplied to the gate circuit 141 _1. Shows.

Further, FIG. 18B shows the same gate circuit 1.
Control signal T8 supplied to 41 _1, FIG. 18 (C) the clock signal is counted by the counter 88 CK4, the output of FIG. 18 (D) is an inverter 148 [/ D1C, / D0
C] is shown.

FIG. 18E shows the digital image signal D
_IN lower two bits of [D1, D0] indicates the output R ₁ and the output E ₁ of the gate circuit 141 ₁ of the comparator circuit 100 ₁ in the case of [0,0].

FIG. 18F shows the digital image signal D
_IN lower two bits of [D1, D0] indicates the output R ₁ and the output E ₁ of the gate circuit 141 ₁ of the comparator circuit 100 ₁ in the case of [0,1].

FIG. 18G shows the digital image signal D
_IN lower two bits of [D1, D0] indicates the output R ₁ and the output E ₁ of the gate circuit 141 ₁ of the comparator circuit 100 ₁ in the case of [1,0].

FIG. 18H shows the digital image signal D
_IN lower two bits of [D1, D0] indicates the output R ₁ and the output E ₁ of the gate circuit 141 ₁ of the comparator circuit 100 ₁ in the case of [1,1].

Further, FIG. 19 shows the clock signal CK4,
An output E ₁ of the gate circuit 141 _1, the analog switch 1
02 ₁ ON, the a view showing the OFF state, the relationship between the reference voltage VA4~VA1 output from the reference voltage source 147, FIG. 19 (A) shows the clock signal CK4.

FIG. 19B shows the digital image signal D
_INWhen the lower 2 bits [D1, D0] of [0, 0] are
Gate circuit 141₁Output E₁And analog switch 1
02 ₁Shows the ON and OFF states of.

FIG. 19C shows the digital image signal D
_INWhen the lower 2 bits [D1, D0] of [0, 1] are
Gate circuit 141₁Output E₁And analog switch 1
02 ₁Shows the ON and OFF states of.

FIG. 19D shows the digital image signal D
_INWhen the lower 2 bits [D1, D0] of [1, 0] are
Gate circuit 141₁Output E₁And analog switch 1
02 ₁Shows the ON and OFF states of.

FIG. 19E shows the digital image signal D
_INWhen the lower 2 bits [D1, D0] of [1, 1] are
Gate circuit 141₁Output E₁And analog switch 1
02 ₁ON / OFF state of the adder circuit 9 in FIG.
The reference voltages VA4 to VA1 output from 4 to 97 are shown.
ing.

Therefore, the relationship between the digital image signal D _IN and the reference voltage output to the data line X ₁ , and the reference voltages VA4 to VA1 output from the reference voltage source 147,
The relationship between the ON / OFF state of the analog switch (SW) 102 ₁ is as shown in FIG.

FIG. 20A shows the digital image signal D
The relationship between _IN and the reference voltage output to the data line X ₁ ,
20B shows the reference voltages VA4 to VA1 output from the reference voltage source 147, and FIG. 20C shows the relationship with the ON / OFF state of the analog switch 102 ₁ .

Digital image signal D _IN and data line X ₂
To the reference voltage output to X ₄ and the reference voltage source 1
The relationship between the reference voltages VA4 to VA1 output from 47 and the ON / OFF states of the analog switches 102 _{2 to} 102 ₄ is the same.

Also in the sixth embodiment, since the reference voltage corresponding to the digital image signal D _IN is applied to the data lines X _{1 to} X ₄ three times during one horizontal period, it is formed on the liquid crystal display panel 1. Even if the leak current of the TFTs 6 _{11 to} 6 ₄₄ is large, the reference voltage corresponding to the digital image signal D _IN can be applied to the pixel electrodes 4 ₁₁ to 4 ₄₄ .

Therefore, according to the sixth embodiment as well,
As in the fifth embodiment, even when the leakage current of the TFT 6 ₁₁ to 6 ₄₄ to be formed on the liquid crystal display panel 1 is large, performs a gradation display corresponding to the digital image signal D _IN,
The product value as a liquid crystal display device can be increased.

Seventh Embodiment FIG. 21, FIG. 22 FIG. 21 is a diagram schematically showing the circuit configuration of a seventh embodiment of the present invention. The liquid crystal display device of the seventh embodiment is shown in FIG. This is to improve the liquid crystal display device of the fifth embodiment shown.

The liquid crystal display device of the seventh embodiment is different from the liquid crystal display device of the fifth embodiment shown in FIG. 9 in that the data driver 140 shown in FIG.
The driver 154 is provided, and the other points are the same as those of the fifth embodiment shown in FIG.

Here, the data driver 154 is shown in FIG.
The difference from the data driver 140 shown in FIG. 3 is that a time base generator 155 is provided, and the comparison circuits 100 ₁ to
Instead of 100 ₄ and the gate circuits 141 _{1 to} 141 ₄ ,
And in that it is provided with a selection circuit 156 _{1 to 156 4,} and other, is configured similarly to the data driver 140 shown in FIG.

[0195] Incidentally, TB1～TB4 timebase signal output from the time base generator 155, H ₁ to H ₄ is the output of the selection circuit 156 _{1 to 156 4.}

Here, the selection circuits 156 _{1 to} 154 ₄ have the same circuit configuration, and FIG. 22 shows the circuit configurations of the time base generator 155 and the selection circuit 156 ₁ .

In the time base generator 155, 15
7 to 165 are inverters, 166 to 172 are NOR circuits, 173 to 175 are NAND circuits, and the selection circuit 1
In 56 ₁ , 176, 177 are inverters, 178
˜181 is a NOR circuit, and 182 to 186 are NAND circuits.

FIG. 23 shows the time base generator 155.
And a time chart showing the operation of the selection circuit 156 _1, FIG. 23 (A) the reference voltage VA4~VA1 is output from the addition circuit 94 to 97, FIG. 23 (B) is a counter 88
Control signal T2 supplied as a reset signal to
3 (C) shows the control signal T8 supplied to the gate circuits 141 _{1 to} 141 ₄ .

23D is a clock signal CK4 counted by the counter 88, FIG. 23E is an output [D1C, D0C] of the counter 88, and FIG. 23F is an output from the time base generator 155. The time base signals TB1 to TB4 are shown.

Further, FIG. 23G shows the digital image signal D
The lower 2 bits [D1, D0] of _IN are [0, 0], [0,
1], [1, 0], [1, 1] selection circuit 156
Shows _one of the output H _1.

In the seventh embodiment, the selection circuit 15
The outputs H _{1 to} H ₄ of 6 _{1 to} 15 6 ₂ match the outputs E _{1 to} E _{4 of the} gate circuits 141 _{1 to} 141 ₂ provided in the fifth embodiment shown in FIG. 9, respectively.

As a result, even in the seventh embodiment, 1
Since the reference voltage corresponding to the digital image signal D _IN is applied to the data lines X _{1 to} X ₄ three times during the horizontal period, the TFTs 6 _{11 to} 6 formed on the liquid crystal display panel 1 are formed.
Even if the leakage current is large _44, the pixel electrodes 4 ₁₁ -
A reference voltage corresponding to the digital image signal D _IN can be applied to ₄₄ 4.

Therefore, according to the seventh embodiment as well,
As in the fifth embodiment, even when the leakage current of the TFT 6 ₁₁ to 6 ₄₄ to be formed on the liquid crystal display panel 1 is large, performs a gradation display corresponding to the digital image signal D _IN,
The product value as a liquid crystal display device can be increased.

Eighth Embodiment FIG. 24, FIG. 25 FIG. 24 is a diagram schematically showing the circuit configuration of an eighth embodiment of the present invention. The liquid crystal display device of the eighth embodiment is shown in FIG. The liquid crystal display device of the seventh embodiment shown is improved.

The liquid crystal display device of the eighth embodiment is shown in FIG.
21 is different from the liquid crystal display device of the seventh embodiment shown in FIG.
A data driver 187 having a circuit configuration different from that of the data driver 154 shown in FIG. 21 is provided, and the other points are configured similarly to the seventh embodiment shown in FIG.

Here, the data driver 187 is shown in FIG.
21 is different from the data driver 154 shown in FIG.
With the decoder 98 _{1-98 4} provided decoders 188 _{1 to 188 4} of different circuit configuration shown in, remove the analog switch 102 ₁ to 102 ₄ shown in FIG. 21, as the output of the selector 99 ₁ to 99 ₄ The data lines X _{1 to} X ₄ of the liquid crystal display panel 1 are transmitted,
For the others, the data driver 15 shown in FIG.
It has the same configuration as that of No. 4.

These decoders 188 _{1 to} 188 ₄ have the same circuit configuration, and the decoder 188 ₁ is representatively shown in FIG. 25. 1 in the figure
89 to 191 are inverters, 192 to 195 are NAND
The circuits 196 to 199 are NOR circuits.

Here, the upper 2 bits [D3, D of the digital image signal D _IN when the selection circuit 156 ₁ = H level is present.
2], the outputs of the NOR circuits 196 to 199, and ON / O of the analog switches 109 to 112 of the selector 99 _1.
The relationship with the FF is as shown in Table 2, and the selection circuit 15
When 6 ₁ = L level, NOR circuits 196 to 199
Output = "0" (L level), analog switch 10
9 to 112 = OFF.

[0209]

[Table 2]

Therefore, also in this eighth embodiment,
Since the reference voltage corresponding to the digital image signal D _IN is applied to the data lines X _{1 to} X ₄ three times during one horizontal period, the TFTs 6 ₁₁ to ₁₁ formed on the liquid crystal display panel 1
Even if the leakage current of 6 ₄₄ is large, the pixel electrode 4 ₁₁
It is possible to apply a reference voltage corresponding to ~ 4 ₄₄ into a digital image signal D _IN.

Therefore, according to the eighth embodiment as well,
As in the fifth embodiment, even when the leakage current of the TFT 6 ₁₁ to 6 ₄₄ to be formed on the liquid crystal display panel 1 is large, performs a gradation display corresponding to the digital image signal D _IN,
The product value as a liquid crystal display device can be increased.

[0212]

As described above, according to the first aspect of the present invention, the switching circuit is provided so that some or all bits of the digital image signal and some or all of the plurality of reference voltages are provided. Switching is performed so that some or all of the bits of these digital image signals and some or all of the plurality of reference voltages are supplied to the data driver via the same signal line group. The number of signal lines to be formed in the frame part of the liquid crystal display panel can be reduced as compared with the case where a plurality of reference voltages are supplied to the data driver by separate signal lines, respectively, and as a result, the liquid crystal display The area of the frame portion of the panel can be reduced, and the value as a liquid crystal display device can be increased.

According to the second aspect of the present invention, one voltage corresponding to the digital image signal is selected from among one of the plurality of staircase voltages output from the adder circuit. Is selected a plurality of times within one horizontal period, and one voltage corresponding to the selected digital image signal is sent to the data line of the liquid crystal display panel as an analog image signal. Even if the leakage current of the TFT that is operated is large, the voltage of the pixel electrode can be raised to the voltage corresponding to the digital image signal, and as a result, gradation display corresponding to the digital image signal can be performed. Therefore, the value of the liquid crystal display device can be increased.

[Brief description of drawings]

FIG. 1 is a diagram showing in principle a circuit configuration of a liquid crystal display device of a first invention in the present invention.

FIG. 2 is a diagram showing in principle a circuit configuration of a liquid crystal display device of a second invention in the present invention.

FIG. 3 is a diagram schematically showing a circuit configuration of a first embodiment of the present invention.

FIG. 4 is a time chart showing the operation of the first embodiment of the present invention.

FIG. 5 is a diagram schematically showing a circuit configuration of a second embodiment of the present invention.

FIG. 6 is a diagram showing a circuit configuration of a decoder provided in a data driver which constitutes a second embodiment of the present invention.

FIG. 7 is a diagram schematically showing a circuit configuration of a third embodiment of the present invention.

FIG. 8 is a diagram schematically showing a circuit configuration of a fourth embodiment of the present invention.

FIG. 9 is a diagram schematically showing a circuit configuration of a fifth embodiment of the present invention.

FIG. 10 is a time chart showing the operation of the reference voltage source provided in the fifth embodiment of the present invention.

FIG. 11 is a diagram showing a circuit configuration of a gate circuit which constitutes a data driver provided in a fifth embodiment of the present invention.

FIG. 12 is a time chart showing the operation of a comparison circuit and a gate circuit which form a data driver provided in the fifth embodiment of the present invention.

FIG. 13 is a diagram showing the relationship between the output of the gate circuit, the ON / OFF state of the analog switch for sending the output of the selector to the data line, and the reference voltage output from the reference voltage source in the fifth embodiment of the present invention. 2 is a time chart showing.

FIG. 14 is a diagram showing a relationship between a digital image signal and a reference voltage output to a data line according to a fifth embodiment of the present invention;
The reference voltage output from the reference voltage source and the ON of the analog switch that sends the output of the selector to the data line,
It is a time chart which shows the relation of an OFF state.

FIG. 15 is a time chart for explaining an example of a voltage change of a pixel electrode in the fifth embodiment of the present invention.

FIG. 16 is a diagram schematically showing a circuit configuration of a sixth embodiment of the present invention.

FIG. 17 is a time chart showing the operation of the reference voltage source provided in the sixth embodiment of the present invention.

FIG. 18 is a time chart showing the operations of the comparison circuit and the gate circuit which form the data driver provided in the sixth embodiment of the present invention.

FIG. 19 shows the relationship between the output of the gate circuit, the ON / OFF state of the analog switch for sending the output of the selector to the data line, and the reference voltage output from the reference voltage source in the sixth embodiment of the present invention. 2 is a time chart showing.

FIG. 20 is a diagram showing a relationship between a digital image signal and a reference voltage output to a data line according to a sixth embodiment of the present invention;
The reference voltage output from the reference voltage source and the ON of the analog switch that sends the output of the selector to the data line,
It is a time chart which shows the relation of an OFF state.

FIG. 21 is a diagram schematically showing a circuit configuration of a seventh embodiment of the present invention.

FIG. 22 is a diagram showing a circuit configuration of a time base generator and a selection circuit which constitute a data driver provided in a seventh embodiment of the present invention.

FIG. 23 is a time chart showing an operation of a time base generator and a selection circuit which constitute a data driver provided in a seventh embodiment of the present invention.

FIG. 24 is a diagram schematically showing a circuit configuration of an eighth embodiment of the present invention.

FIG. 25 is a diagram showing a circuit configuration of a decoder which constitutes a data driver provided in an eighth embodiment of the present invention.

FIG. 26 is a diagram schematically showing a circuit configuration of a first conventional example of a liquid crystal display device including an active matrix type liquid crystal display panel.

27 is a diagram schematically showing the configuration of an active matrix type liquid crystal display panel provided in the liquid crystal display device of the first conventional example shown in FIG.

28 is a part (decoder, selector) of a data driver provided in the liquid crystal display device of the first conventional example shown in FIG.
FIG. 3 is a diagram showing a circuit configuration of a reference voltage source.

FIG. 29: Data to liquid crystal display panel in actual product
It is a figure which shows the example of mounting of a driver and a gate driver.

30 is an enlarged view showing a part of a frame portion of the liquid crystal display panel in FIG.

FIG. 31 is a diagram schematically showing a circuit configuration of a second conventional example of a liquid crystal display device including an active matrix type liquid crystal display panel.

FIG. 32 is a diagram schematically showing a circuit configuration of a third conventional example of a liquid crystal display device including an active matrix type liquid crystal display panel.

FIG. 33 is a time chart showing the operation of the reference voltage source provided in the liquid crystal display device of the third conventional example shown in FIG. 32.

34 is a diagram showing a part of a data driver and a reference voltage source provided in the liquid crystal display device of the third conventional example shown in FIG. 32.

FIG. 35 is a time chart showing the operations of a comparison circuit and a selector which form a data driver provided in the liquid crystal display device of the third conventional example shown in FIG. 32.

36 is a view showing a relationship between a digital image signal and a reference voltage output to a data line in the liquid crystal display device of the third conventional example shown in FIG. 32, and turning on an analog switch for sending the output of the selector to the data line; It is a time chart which shows the relation of an OFF state.

37 is a time chart for explaining an example of a voltage change of a pixel electrode in the liquid crystal display device of the third conventional example shown in FIG. 32.

[Explanation of symbols]

 113 liquid crystal display panel 114 data driver 115 switching circuit 116 signal line group 117 reference voltage output circuit 118 staircase voltage output circuit 119 adder circuit 120 data driver

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Yuichi Miwa 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor, Hiroyuki Isogai 1015, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited ( 72) Inventor Takahiro Nakano 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited

Claims (9)

[Claims] 1. A pixel electrode provided for each pixel, a common electrode commonly provided for all pixels, and a switching element provided for each pixel electrode for supplying an analog image signal to the pixel electrode. Liquid crystal display panel (11
And 3) is supplied with the digital image signal (D _IN) and a plurality of different reference voltages voltage value (V _n ~V _1), the digital image signals from a plurality of reference voltages (V _n ~V ₁₎ A data driver (114) for selecting a reference voltage having a voltage value corresponding to (D _IN ), and sending the selected reference voltage to the data line of the liquid crystal display panel (113) as the analog image signal; Some or all bits of the image signal (D _IN ) and some or all of the plurality of reference voltages (V _{n to} V ₁ ) are switched, and some or all bits of the digital image signal (D _IN ) are switched. And a part or all of the plurality of reference voltages (V _{n to} V ₁ ) via the same signal line group (116), the data driver (114)
And a switching circuit (115) for supplying the liquid crystal to the liquid crystal display device. 2. The data driver (114) holds a digital image signal (D _IN ) supplied through the switching circuit (115), and a digital image held in the holding circuit. 2. The liquid crystal display device according to claim 1, comprising a decoder for decoding a signal (D _IN ), and a selector for selecting the reference voltage based on an output signal of the decoder. 3. The digital image signal (D _IN ) is transferred from the switching circuit (115) to the data driver (114).
3. The liquid crystal display device according to claim 2, wherein the decoder operation of the decoder is prohibited and all the switches forming the selector are turned off during the period of being supplied to. 4. The data driver (114) holds a digital image signal (D _IN ) supplied through the switching circuit (115), and a digital image held by the holding circuit. A decoder that decodes a signal (D _IN ), a selector that selects the reference voltage according to an output signal of the decoder, and a reference voltage that is supplied via the switching circuit (115) among switches that configure the selector. And a switch connected in series with a switch for selecting the digital image signal (D _IN )
2. A switch connected in series to a switch for selecting a reference voltage supplied via the switching circuit (115) is turned off during a period in which the voltage is held in the holding circuit. The described liquid crystal display device. 5. A pixel electrode provided for each pixel, a common electrode commonly provided for all pixels, and a switching element provided for each pixel electrode for supplying an analog image signal to the pixel electrode. Liquid crystal display panel (11
3), a reference voltage output circuit (117) that outputs a plurality of reference voltages (V _{n to} V ₁ ) having different voltage values, and a staircase voltage that changes stepwise is output a plurality of times within one horizontal period. A staircase voltage output circuit (118) and a plurality of reference voltages (V _n ~) output from the reference voltage output circuit (117).
V ₁ ) and the staircase voltage output from the staircase voltage output circuit (118) are added, and a plurality of staircase voltage different voltage values are output a plurality of times within one horizontal period (119) And a plurality of one voltage corresponding to the digital image signal (D _IN ) among one of the plurality of staircase voltages output from the adder circuit (119) within one horizontal period. And a data driver (120) which selects one time and outputs one voltage corresponding to the selected digital image signal (D _IN ) to the data line of the liquid crystal display panel (113) as the analog image signal. A liquid crystal display device characterized by being configured as follows. 6. The staircase voltage output circuit (118) comprises a counter and a digital / analog conversion circuit for converting the output of the counter into a positive analog voltage. The data driver (120) comprises: Digital image signal (D
_IN ), a decoder for decoding the upper bits of the digital image signal (D _IN ) held in the holding circuit, and an output signal from the decoder for output from the adder circuit (119). A selector for selecting one staircase voltage from a plurality of staircase voltages, a switch connected between the output side of the selector and the data line of the liquid crystal display panel (113), and the holding circuit. A comparator circuit that compares the lower bit of the digital image signal (D _IN ) held in the counter with the output of the counter, and the digital signal from the step wave voltage selected by the selector based on the output signal of the comparator circuit. wherein one of the voltage corresponding to the image signal (D _iN) to the delivery to the data lines of the liquid crystal display panel (113) over a plurality of times within one horizontal period Sui The liquid crystal display device according to claim 5, characterized in that it is constituted by a switch control circuit for controlling the switch. 7. The staircase voltage output circuit (118) comprises a counter and a digital / analog conversion circuit for converting the output of the counter into a negative analog voltage, and the data driver (120) comprises: Digital image signal (D
_IN ), a decoder for decoding the upper bits of the digital image signal (D _IN ) held in the holding circuit, and an output signal from the decoder for output from the adder circuit (119). A selector for selecting one staircase voltage from a plurality of staircase voltages, a switch connected between the output side of the selector and the data line of the liquid crystal display panel (113), and the holding circuit. A comparator circuit for comparing the lower bit of the digital image signal (D _IN ) held in the counter with a signal obtained by inverting the output of the counter, and a staircase wave selected by the selector based on the output signal of the comparator circuit. the delivery to the data lines of the liquid crystal display panel (113) a plurality of times one of the voltage corresponding to the digital image signal (D _iN) in one horizontal period from the voltage The liquid crystal display device according to claim 5, characterized in that it is constituted by a switch control circuit for controlling the switch so that. 8. The staircase voltage output circuit (118) comprises a counter and a digital / analog conversion circuit for converting the output of the counter into a positive analog voltage, and the data driver (120) comprises: Digital image signal (D
_IN ), a decoder for decoding the upper bits of the digital image signal (D _IN ) held in the holding circuit, and an output signal from the decoder for output from the adder circuit (119). A selector for selecting one staircase voltage from a plurality of staircase voltages, a switch connected between the output side of the selector and the data line of the liquid crystal display panel (113), and the counter of the counter. A time base generator that inputs an output and outputs a predetermined time base signal, a predetermined time base signal output from the time base generator, and a lower order of the digital image signal (D _IN ) held in the holding circuit. a plurality from among the selected staircase wave voltage by the selector based on the bit of one of the voltage corresponding to the digital image signal (D _iN) within one horizontal period Over the liquid crystal display panel (11
6. A liquid crystal display device according to claim 5, further comprising a switch control circuit for controlling the switch so as to send to the data line of 3). 9. The staircase voltage output circuit (118) comprises a counter and a digital / analog conversion circuit for converting the output of the counter into a positive analog voltage. The data driver (120) comprises: Digital image signal (D
_IN ), a decoder for decoding the upper bits of the digital image signal (D _IN ) held in the holding circuit, and an output signal from the decoder for output from the adder circuit (119). A selector that selects one staircase voltage from a plurality of staircase voltages, a timebase generator that inputs the output of the counter and outputs a predetermined timebase signal, and an output from this timebase generator The decoder is controlled based on a predetermined time base signal and the lower bit of the digital image signal (D _IN ) held in the holding circuit, and the selector is operated to select the step wave voltage from the selected step wave voltage. Digital image signal (D
_And a decoder control circuit for sending one voltage corresponding to ( _IN ) to the data line of the liquid crystal display panel (113) a plurality of times within one horizontal period. The liquid crystal display device according to claim 5.