JPH0616567B2 - High efficiency amplifier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION "Industrial field of application" The present invention relates to an electronic device mounted on a satellite, a portable radio device, and the like.
ET (Field Effect Transistor) amplifier efficiency improvement.

"Prior Art" Conventionally, as this type of amplifier, a so-called class F amplifier as shown in FIG. 4 is used. A sinusoidal input signal (generally an FM wave, a PM wave, etc.) given to the input terminal IN is applied to the gate of a field effect transistor (hereinafter referred to as FET or simply transistor) Q via a DC blocking capacitor C _1. . The gate of the transistor Q is connected to the power supply terminal PW ₁ via the choke coil L ₁ . The source of the transistor Q is grounded, and the drain is connected via the choke coil ₂ to, for example, a power supply terminal P having a power supply voltage V _DD = 10V.
Connected to W ₂ . The signal amplified by the transistor Q is a DC blocking capacitor ₂ and a λ / 4 distributed constant line N ₁ ,
It is supplied to the load resistance R _L via the output terminal OUT in sequence. The output end of the λ / 4 distributed constant line is grounded via the parallel resonant circuit N ₂ that resonates at the frequency f ₁ of the fundamental wave of the input signal. The load impedance Z _L of the transistor Q is λ
Due to the characteristics of the harmonic reflection circuit RC composed of the / 4 distributed constant line N ₁ and the parallel resonant circuit N ₂ , (a) Z _L (f ₁ ) R ′ _{L with} respect to the fundamental wave, where R ′ _L = R ² ₀ / R _L , where R ₀ is the characteristic impedance of the λ / 4 distributed constant line N ₁ .

(B) For even-order high frequencies Z _L (2nf ₁ ) 0 (c) For odd-order high frequencies Is configured to be. Here, n ≧ 1 is an integer.

From the characteristics (a) to (c) above, (d) the drain voltage V _D includes only the direct current component, the fundamental wave, and the odd-order high-frequency waves (for the even-order, the load Z _L is short-circuited and the voltage is zero). (E) The drain current I _D includes only the DC component, the fundamental wave, and the even-order high frequency (since the load Z _L is open for the odd-order, no current flows).

The voltage of the current terminal PW ₁ , that is, the gate bias voltage V _G
Is equal to the pitting-off voltage V _P (which is the limit gate voltage at which the transistor Q is cut off, -3 V in this example).

When the gate voltage V _g of the sine wave shown in FIG. 5 A to the gate of the transistor Q is applied, as shown in FIG. B, V _g
> Viewed drain current I _D when the AC half-waves as a V _P flows toward the source, the other half-wave to be V _g ≦ V _P transistor Q is I _{D =} 0 is cut off. Therefore, the drain current _ID becomes a half-wave rectified wave having a sinusoidal waveform.
The amplitude of the drain current I _D changes depending on the magnitude of the gate voltage V _g . However, due to the characteristic (e), the drain current I _D maintains a sine half-wave rectified waveform including only the fundamental wave and the even-order high frequency waves. The drain voltage V _D corresponding to the drain current I _D has a waveform that swings up and down around the power supply voltage V _DD = 10 V as shown in FIG. In this example, the peak value is slightly larger than OV (it does not become OV because the transistor has ON resistance), and the peak value of the peak is 2
When the value is slightly smaller than V _DD = 20V, each end has a waveform with a slightly missing tip. _If the amplitude of the peak voltage _g becomes smaller than that of FIG. A to some extent, the peak value of the drain voltage V _D does not reach a peak. On the contrary, as the gate voltage V _g further increases, the drain voltage V _D reaches a peak level and approaches a trapezoidal wave or a rectangular wave. However, the above characteristic (d) is always maintained.

The drain current I _D is composed of a direct current component, a fundamental wave, and an even-order high frequency wave as described in (e) above. The direct current component flows through the choke coil L ₂ and the fundamental wave and the even-order high frequency wave are λ / 4.
It flows along the track N ₁ . Its even-order frequency is mostly flows into smaller parallel resonant circuit N ₂ of the impedance compared to R _L, hardly flows to R _L. Since the parallel resonant circuit N ₂ has an extremely high impedance with respect to the fundamental wave as compared with R _L , the current of the fundamental wave flows through R _L. Therefore, the output voltage Vout supplied to the load R _L becomes a sine wave of only the fundamental wave as shown in FIG. 5D.

The Figure 6 A through Figure 8 A in diagram _I D -V _D static characteristics of the transistor Q, taken by the transistor Q _(I D,
V _D ) is a diagram showing loci P ₁ -P ₂ that the set of V _D moves about the operating point P _{0 of the} amplifier, and B and C in each of the above figures are drain currents I _D and A corresponding to the locus of A, respectively. locus of the drain voltage V _D, that is a diagram illustrating waveforms. FIG. 6 shows the case where the amplitude of the input gate voltage V _g is small and the drain voltage V _D does not reach the peak, and the locus P ₁ to
P ₂ is a straight line having a break point at the operating point P ₀ . P _'1 ~
P ′ ₂ is the case where the amplitude of the gate voltage V _g is small. 7th
The figure shows the case where the amplitude of the gate voltage V _g is increased until the drain voltage V _D reaches a peak and becomes a trapezoidal wave. (I
The halves P _{1 to} P ₀ of the loci P _{1 to} P ₂ of _D , V _D ) are curved lines that are convex below the straight line P ₁ P ₀ . FIG. 8 shows the case where the amplitude of the gate voltage V _g is further increased to bring the drain voltage V _D closer to a rectangular wave, and the degree of curvature of the loci P _{1 to} P ₂ is further increased.

Since the drain loss of the transistor Q is I _D × V _D ,
The degree of curvature of the loci P _{1 to} P ₀ of the point (I _D , V _D ) is large, and the drain loss decreases as the coordinates approach the V _D axis and the I _D axis. In other words, the drain loss becomes smaller as the drain voltage waveform approaches a rectangular wave. Although detailed description is omitted, the output power P _o supplied to the load R _L increases as the drain voltage waveform approaches a rectangular wave. Therefore, power supply efficiency (drain efficiency) η = (P ₀ / P _DC ) × 100
The same is true for%. Note that P _DC is DC power supplied from the power source to the drain, and P ₀ is power of the signal wave supplied to the load R _L.

FIG. 7 and FIG. 8 are shown to explain the relationship between the power supply efficiency and the waveform of the drain voltage V _{D. In} practice, the drain voltage is limited due to the limitation on the gate voltage V _g as described in the next section. V _D cannot be trapezoidal or rectangular in this way.

[Problems to be Solved by the Invention] In an electronic device mounted on a satellite, a portable radio device, or the like, a power supply device needs to be small and lightweight and have a long life. Therefore, an output amplifier is required to have high power supply efficiency. . However,
FET to be used (Because it is in the GHz band, Ga _{a s} FET
Output amplifier is not at a satisfactory efficiency. That is, the maximum value V _{g max} of the gate voltage>
In the case of 0, a forward current (current flowing from the gate to the source) flows in the Schottky junction of the gate, and the allowable value is an average DC value of about several mA, so that the positive gate voltage V
_g is limited to the maximum allowable forward voltage.

On the other hand, when the minimum value V _{g min} of the gate voltage exceeds the reverse breakdown voltage of the Schottky junction (for example, −7 V), a leak current flows, and the allowable value is an average DC value of several mA. The voltage V _g is limited to the maximum allowable reverse voltage.

Since the positive and negative peak values of the gate voltage V _g are limited in this way, the amplitude of the gate voltage V _D cannot be increased until the drain voltage V _D becomes a trapezoidal wave or a rectangular wave, so that high power supply efficiency is obtained. I couldn't.

An object of the present invention is to solve the above-mentioned conventional problems and to provide a class F FET output amplifier with high power supply efficiency.

"Means for Solving the Problem" As an output load circuit of the drain of a source-grounded FET amplifier circuit whose gate is biased to a pinch-off voltage,
An FET amplifier connected by a high frequency reflection circuit in which the input impedance as seen from the drain side shows a resistive load at the frequency of the fundamental wave of the input signal and is almost short-circuited and open at the frequencies of even and odd high frequencies, respectively. In the present invention, a limiter is provided on the gate input side to clip the positive and negative peak values of the gate voltage to values equal to or less than the maximum allowable forward voltage and the maximum allowable voltage of the gate, respectively. .

It is desirable to provide a band stop filter for suppressing an even-order high frequency of the input signal on the gate input side of the amplifier.

"Embodiment" An embodiment of the present invention is shown in Fig. 1 by assigning the same reference numerals to portions corresponding to Fig. 4, and duplicated description will be omitted. In the present invention, the limiter LM is provided on the gate input side of the transistor Q.
, Which causes the gate voltage V _g to be a trapezoidal wave, the positive and negative peaks of which are equal to the maximum allowable forward voltage (eg 0.7 V) and the maximum allowable reverse voltage (eg −7 V) of the gate respectively, or It is set below that. The gate is a power supply terminal PW to which a voltage V _L1 corresponding to the positive peak voltage of the limiter output is supplied via a diode D _1.
3 and a diode D ₂ (diode D
₍ Reverse direction to ₁ ), and is connected to the power supply terminal PW ₄ to which the negative peak voltage of the limiter output and the corresponding voltage V _L2 are supplied. The power supply terminals PW ₃ and PW ₄ are grounded via bypass capacitors C ₄ and C ₅ that short-circuit high-frequency signals, respectively. A limiter LM is configured by these diodes D ₁ , D ₂ , capacitors C ₄ , C _{5, and the} like. In addition,
In this example, the gate coil L ₁ and the resistor R _G are sequentially connected to the power supply terminal PW ₁ , and the connection point between the coil L ₁ and the resistor R _G is grounded via the bypass capacitor C ₆ to provide the gate input. The signal is prevented from branching to the gate bias circuit and becoming a loss.

The waveforms of the main parts of the circuit of FIG. 1 are shown in FIG. In order to bring the output voltage of the limiter LM close to a rectangular wave, the amplitude of the input voltage V _in is selected to be sufficiently larger than that of the limiter output voltage. Since the limiter output voltage becomes a trapezoidal wave and the peak value of the voltage is set to a value close to the maximum allowable voltage of the gate, the drain voltage V _D oscillates in the range of about 0 to 20 V centering on V _DD = 10 V. It is a trapezoidal wave, and the waveform is closer to a rectangular wave than before.

Output power P when the input power P _{i of the} amplifier is changed
Fig. 3 shows changes in ₀ , power supply efficiency η, and gate current I _G.
The gate current characteristic shown by the dotted line in the figure is the conventional example shown in FIG. 4, and when the input power P _i approaches P _i1 , the gate current I _G changes from a negative current (flowing from the source to the gate) to a forward current ( Flowing from the gate to the source), and reaches the allowable value I _Gmax of the forward current at the input power P _i1 . Therefore, the input power P _i cannot be increased any more, and the maximum output and the maximum efficiency are limited to P ₀₁ and η ₁ , respectively.
(In this example, the peak value of the negative current does not exceed the allowable value I _G min,
This is the case where the input power is limited by the forward current. However, in the circuit of FIG. 1, the positive and negative peak values of the gate current are suppressed to be sufficiently smaller than those of the conventional example by the action of the limiter LM, and the allowable values I _G max and I _G min are not exceeded. Therefore, the same applies to the gate voltage V _g . Input power P
_{For i} , the efficiency η takes a saturation value η ₂ (> η ₁ ), for example P _i2 (>
P _i1 ), at which time the maximum output P
₀₂ (> P ₀₁ ) is obtained. To give a numerical example, η ₁ = 7
0%, η ₂ = 80%; P ₀₁ = 28.5 dB _m , P ₀₂ = 30 dB
_{Like m} .

As shown by the dotted line in FIG. 1, it is desirable to provide a trap circuit (generally a band stop filter) N ₃ for bypassing an even-order high frequency wave to the gate of the transistor Q. In this example, a case where the trap circuit TC is formed of a series circuit of a distributed constant line N ₃ of λ / 4 for a fundamental wave and a DC blocking capacitor C ₇ is shown. The capacitor C
₇ also serves as a bypass for high frequency signals.

Now, consider the case where there is no trap circuit TC. When the input signal includes two sine waves (f ₁ and f ₂ ) having frequencies close to each other, even-order high frequencies (2f ₁ , 4f ₁ , ...; 2f ₂ ) due to the non-linearity of the limiter LM , 4f ₂ , ...) also occurs. This even-order high frequency wave is coupled to the fundamental wave by the non-linear operation of the FET, and is 2f close to the fundamental wave frequencies f ₁ and f _2.
Intermodulation wave is generated with a _{1 -f 2, 2f 2 -f 1} . This is also called a third-order intermodulation distortion component.

Since these frequencies are close to the fundamental frequency, they are difficult to isolate and it is therefore desirable to eliminate the even high frequencies contained in the input of the FET, and the trap circuit TC is for this purpose.

According to the present invention, the limiter is provided on the gate input side of the FET, and the positive and negative peak values of the input gate voltage are approximately equal to the positive and negative allowable values of the gate voltage. Clipped to a trapezoidal wave below that, drain voltage V
It becomes possible to make _D much closer to a rectangular wave than in the past. As a result, the drain loss is reduced, and a class F amplifier having a higher power supply efficiency than ever can be realized.

If a band stop filter for suppressing even-order high frequencies is provided on the gate input side, the intermodulation distortion of the amplifier output can be greatly improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG.
FIG. 3 is a waveform diagram of the main part of the figure, FIG. 3 is a diagram showing changes in output power, power supply efficiency and gate current when input power is changed in the embodiment of FIG. 1, and FIG. 4 is a conventional high efficiency amplifier. FIG. 5, FIG. 5 is a waveform diagram of the main part of FIG. 4, and FIGS. 6 to 8 are drawn on the static characteristic diagram of the drain voltage V _D vs. drain current I _D of the FET of FIG. (V _D, I _D) and a set of trajectories of a diagram showing the corresponding drain current waveform, and a drain voltage waveform.

Claims (2)

[Claims] 1. As an output load circuit of a drain of a grounded source type FET amplifier circuit in which a gate is biased to a pinch-off voltage, an input impedance viewed from the drain side shows a resistive load at a frequency of a fundamental wave of an input signal, In an FET amplifier that is connected with a harmonic reflection circuit that is almost short-circuited and open at the frequencies of even-order and odd-order harmonics respectively, a limiter is provided on the gate input side to provide positive and negative peaks of the gate voltage. A high-efficiency amplifier characterized in that the values are clipped to values equal to or less than the maximum allowable forward voltage and the maximum allowable voltage of the gate, respectively. 2. A high efficiency amplifier according to claim 1, wherein a band stop filter for suppressing even harmonics of the input signal is provided on the gate input side.