JPH06164569A - Asynchronous data reception circuit - Google Patents

Abstract

PURPOSE:To securely fetch reception data even when an asynchronous clock is used for transmission speed by sequentially fetching input data in response to a sampling pulse outputted from a decoder in a shift register. CONSTITUTION:The decoder 107 outputs the Sp pulse in response to a QA signal and a signal phi0 for fetching reception data into the shift register 209 even when the clock signal phi0 asynchronous with reception data is used. At that time, the QA signal is processed in plural gate circuits and the SP pulse is formed. The shift register 209 sequentially fetches reception data whenever the SP pulse is received.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiver circuit in asynchronous communication, and more particularly to a receiver circuit incorporated in a low power 1-chip microcomputer.

[0002]

2. Description of the Related Art A conventional circuit for receiving asynchronous communication is shown in FIG. The circuit of FIG. 2 performs a receiving operation using a clock having a very high speed (high frequency) with respect to the transmission speed of the received data.

The circuit shown in FIG. 2 will be described below.

This circuit comprises a data input terminal 201, a start bit detection circuit 203, a synchronous clock generation circuit 205, a sampling pulse generation circuit 207 and a shift register 209. Data (hereinafter referred to as received data) is sequentially applied to the data input terminal 201 from the outside. This received data has a predetermined length, for example, a data transmission rate of 4800 [bp
s].

The start bit detection circuit 203 is connected between the data input terminal 201 and the sampling pulse generation circuit 207, and when the received data is applied to the data input terminal 201, the sampling pulse generation circuit 207.
The EN signal is output to.

Φ1 is a high-speed clock signal generally used in asynchronous communication, for example, a clock signal of 10 [MHz]. The clock signal φ1 is also supplied to various external circuits (not shown) arranged on the same chip and outside the circuit shown in FIG.

The synchronous clock generation circuit 205 is connected to the sampling pulse generation circuit 207, and generates from the clock signal φ1 a clock signal φ2 having a frequency synchronized with the transmission rate of received data. The reason for newly generating the clock signal φ2 is to synchronize the received data with the operation of the shift register 209 that processes the received data.

The sampling pulse generating circuit 207 includes a start bit detecting circuit 203 and a synchronous clock generating circuit 2.
05 and the shift register 209, and EN
In response to the signal, it outputs pulse SP signals at regular intervals.

The shift register 209 is connected to the data input terminal 201 and the sampling pulse generating circuit 207, and sequentially receives the received data in response to the SP signal given to the clock input terminal 211.

Next, the operation of the circuit shown in FIG. 2 will be described with reference to FIG.

FIG. 3 is a time chart showing the operation of the circuit shown in FIG. 2, and shows the temporal change of each signal.

First, the synchronous clock generation circuit 205 generates a clock signal φ2 having a frequency synchronized with the transmission rate of received data from the clock signal φ1.

Then, the start bit detection circuit 203
However, when the start bit indicating the beginning of the received data applied to the data input terminal 201 is detected, the EN signal is "H".
Get up to the level.

Then, the sampling pulse generation circuit 20
When the EN signal rises to the "H" level, 7 outputs the SP signal at the constant interval T1. The SP signal is a pulse located at about the center of the received data in the clock signal φ2 synchronized with the transmission rate of the received data.

Each time the shift register 209 receives the SP signal to the clock input terminal 211, the shift register 209 sequentially receives the received data 1, 2 ,.

[0016]

However, since the circuit described above uses a very high speed clock signal of 10 [MHz], the entire circuit including the asynchronous data receiving circuit consumes a large current. There was a problem.

In order to eliminate this problem, there is a demand for operating the asynchronous data receiving circuit with a low-speed clock signal to suppress the current consumption. However, in the asynchronous data receiving circuit, even if a low speed clock signal is used, it is necessary to newly generate a clock signal synchronized with the transmission speed of the received data from this low speed clock signal. That is, the synchronous clock generation circuit is necessary regardless of the speed of the clock signal. Therefore, the problem that the circuit area of the asynchronous data receiving circuit is increased cannot be solved yet.

[0018]

In order to eliminate the above problems, the present invention provides a data input terminal to which data having a predetermined length is continuously applied and a clock signal having a predetermined cycle. A clock input terminal, a data detection circuit connected to the data input terminal, which outputs a data detection signal in response to the data first applied to the data input terminal, the clock input terminal and the data detection circuit. A counter connected to a circuit for counting the clock signal in response to the data detection signal and outputting a count output signal; and a counter connected to the counter and the clock input terminal, the count output signal and the clock signal A decoder for selectively outputting a sampling pulse corresponding to the center position of each data in response to
A shift register connected to the data input terminal and the decoder is provided, which sequentially receives the data supplied to the data input terminal in response to the sampling pulse output from the decoder.

[0019]

According to the present invention, the received data can be accurately received even if a clock signal that is asynchronous with the transmission speed of the received data and is relatively low speed is used.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram for explaining an asynchronous data receiving circuit according to the present invention. Particularly, a portion surrounded by a dotted line is a circuit showing an embodiment of the present invention. FIG. 4 is a diagram showing the operation of the circuit shown in FIG.

An embodiment of the present invention will be described below with reference to FIGS. 1 and 4. In FIG. 1, the same components as those shown in FIG. 2 are assigned the same reference numerals as those given in FIG.

In FIG. 1, the asynchronous data receiving circuit of the present invention comprises a data input terminal 201 and a clock input terminal 1.
09, start bit detection circuit 203, and counter 1
05, a decoder 107, and a shift register 209.

The asynchronous data receiving circuit surrounded by the dotted line is connected to the oscillation circuit 103 shown outside the dotted line. The oscillator circuit 103 is 32768
It is connected to a crystal oscillator 101 for [Hz].

Data (hereinafter referred to as received data) is sequentially applied to the data input terminal 201 from the outside. The received data has a predetermined length and is transmitted at a predetermined transmission rate, for example, 4800 [bps].

The start bit detection circuit 203 is connected between the data input terminal 201 and the counter 105 and outputs an EN signal to the counter 105 when receiving data is applied to the data input terminal 201.

The oscillating circuit 103 oscillates at 32768 [Hz], which is the natural vibration frequency of the crystal unit 101, and outputs a clock signal φ0 asynchronous with the received data. The clock signal φ0 is supplied to the clock input terminal 109.
And to various external circuits (not shown) arranged outside the dotted line.

The counter 105 is connected to the start bit detection circuit 203 and the clock input terminal 109 and counts the clock signal φ0 in response to the EN signal. Then, the counter 105 represents the count result of the clock signal φ0 with a 7-bit QA signal.

The decoder 107 is connected to the counter 105, the shift register 209 and the clock input terminal 109, and outputs the SP pulse in response to the 7-bit QA signal and the clock signal φ0. This SP pulse is a pulse extracted from the clock signal φ0, and is an optimum pulse for the shift register 209 to receive the received data.

The reason why a predetermined pulse is extracted from the clock signal φ0 by using the 7-bit QA signal in this way is to accurately receive the received data in the shift register 209.

The shift register 209 has a decoder 107.
And the data input terminal 201, and sequentially receives the received data in response to the SP pulse given to the clock input terminal 211.

Next, the operation of the circuit shown in FIG. 1 will be described with reference to FIG. However, the transmission speed of the received data is 4
It is set to 800 [bps].

First, the oscillation circuit 103 and the crystal oscillator 101
By this, a clock signal φ0 of 32768 [Hz] is generated.

Then, the start bit detection circuit 203
However, when a start bit indicating the beginning of the received data applied to the data input terminal 201 is detected, the EN signal rises to the "H" level after the time of TS has elapsed.

The counter 105 counts the clock signal φ0 in response to the EN signal rising to the “H” level, and outputs a 7-bit QA signal to the decoder 107.

The decoder 107 outputs an SP pulse in response to the QA signal and the clock signal φ0 so that the received data can be taken into the shift register even when the clock signal φ0 asynchronous with the received data is used. This SP pulse is a pulse located approximately at the center of each of the received data 1 to 7 and the start bit and stop bit among the pulses forming the clock signal φ0 shown in the figure. After the EN signal rises to the “H” level, the decoder 107 of the present embodiment, 1, 8, 15, 22, 28, 35, 42,
It is designed to extract the pulses of the 49th, 56th, 62nd, 69th clock signal φ0. Specifically, FIG.
The circuit configuration is as shown in. In FIG. 5, a bus indicated by a thick line is a bus to which a 7-bit QA signal is transferred, and data lines 501 to 513 are connected to this bus, respectively.

The QA signal is processed by a plurality of gate circuits, and the processing result is finally output from the OR gate 515. The output from the OR gate 515 is that the pulses forming the clock signal φ0 are
It is an "H" level signal indicating that it is the eighth, 62nd, 69th occurrence.

Further, this OR gate 515 has an AND gate.
The gate 517 is connected. This AND gate 51
7 has one input terminal connected to the clock input terminal 109 and the other input terminal connected to the output terminal of the OR gate 515. The AND gate 517 outputs the SP pulse only when both the input terminals become "H" level. That is, the AND gate 517 outputs the clock signal φ located at the 1st, 8th, ...
Only the pulses that make up 0 are output.

The data line 513 is connected to the first stage of the counter 105, and the data line 501 is connected to the last stage of the counter 105.

The shift register 209 sequentially takes in the received data every time the SP pulse is received. That is, the shift register 209 includes 1,8,15,22,28,35,42,49,5 of the pulses forming the clock signal φ0.
Received data is captured in response to the sixth pulse.

As described above, the transmission speed of received data is 4800.
The case where the clock signal φ0 is 32768 [Hz] in [bps] has been described. 1 /
It is sufficient to provide a frequency dividing circuit for dividing the frequency by ² 1/2. In that case, it is not necessary to change the circuit configuration of the decoder 107.

[0041]

As described above in detail, according to the present invention, even if a clock signal asynchronous with the transmission rate of received data is used, the received data can be taken in reliably.

Further, according to the present invention, since the receiving operation can be performed using the clock signal of a relatively low speed, the current consumed by the entire circuit can be reduced.

Further, according to the present invention, it is not necessary to provide a synchronous clock generating circuit for modulating an externally applied clock signal into a clock signal which is synchronized with the transmission rate of received data. .

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a conventional asynchronous data receiving circuit.

FIG. 3 is a diagram showing an operation of a conventional asynchronous data receiving circuit.

FIG. 4 is a diagram showing the operation of one embodiment of the present invention.

FIG. 5 is a diagram showing a circuit configuration of a decoder of the present invention.

[Explanation of symbols]

 105 counter 107 decoder 109 clock input terminal 201 data input terminal 203 start bit detection circuit 209 shift register

Claims (2)

[Claims] 1. A data input terminal to which data having a predetermined length is continuously applied, a clock input terminal to which a clock signal having a predetermined cycle is applied, and the data input terminal connected to the data input terminal. A data detection circuit which outputs a data detection signal in response to the data initially given to the clock input terminal and the data detection circuit, and counts the clock signal in response to the data detection signal. A counter that outputs a count output signal; and a sampling pulse that is connected to the counter and the clock input terminal and that responds to the count output signal and the clock signal to selectively select a sampling pulse corresponding to the center position of each data. An output decoder, a data output terminal connected to the decoder, and a decoder output from the decoder. Asynchronous data receiving circuit, characterized in that it comprises a shift register responsive to pulling pulses sequentially fetches data given to the data input terminal. 2. The decoder according to claim 1, wherein the decoder circuit outputs a signal indicating a center position of each of the data, and an AND circuit that ANDs the signal output from the decoding unit and the clock signal. The asynchronous data receiving circuit according to claim 1, wherein the asynchronous data receiving circuit comprises: