JPH06164564A - Data transfer system - Google Patents

Abstract

PURPOSE:To prevent the deterioration of transmission speed by fetching data whose transmission delay time difference is small. CONSTITUTION:Data and a timing signal are supplied from a transmission circuit 101 to shift registers 301-*. The shift registers 301-* are driven by a clock whose period is considerably shorter than the repetitive period of data, and outputs for respective flip flops constituting them are selected by switching circuits 302-*. The switching circuits 302-* select the flip flop in accordance with the content of counters 303-*. The counters 303-* are updated for a period until all the outputs of the switching circuits 302-* become valid after corresponding output becomes valid by a control circuit 306 retrieving output from the switching circuits 302-* at the prescribed period. Above operation is tried twice and the center value of the update result of the counters 303-* is calculated by using storage circuits 308 and 309. Then, the value is rewritten into the counters 303-* again. Then, data whose transmission delay time is small can be fetched.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer system for transferring data using a plurality of signal lines.

[0002]

2. Description of the Related Art FIG. 10 shows the configuration of a conventional data transfer system. The data transfer system includes first to n-th (n is an integer of 2 or more) data signal lines 2 between a transmitter 10 and a receiver 30 that operate in synchronization with each other in a synchronization cycle.
, 20-n, and transfers data from the transmission device 10 to the reception device 30 by using the first to n-th data signal lines 20-1 to 20-n. The clock distribution circuit 4 is provided in the transmitter 10 and the receiver 30.
A clock signal (synchronization signal) that defines the above-mentioned synchronization cycle is supplied from 0. The transmitter 10 and the receiver 30 are connected by a timing signal line 21.

The transmitter 10 transmits data on the first to n-th data signal lines 20-1 to 20-n, and
A transmission circuit 101 that transmits a timing signal is provided on the timing signal line 21. The receiving device 30 includes the first to nth
Receiving register 304 for receiving the data on the data signal lines 20-1 to 20-n and also receiving the timing signal on the timing signal line 21, and the receiving register 30.
4 to the first to n-th signal lines 314-1, ..., 314-n
And a receiving circuit 305 connected via the.

Next, the operation of the data transfer system shown in FIG. 10 will be described. The transmitting device 10 transmits the first data
Through the nth data signal lines 20-1 to 20-n, the timing signal line 21 sends out a timing signal indicating that the data has been sent out to the receiving device 30.

In the receiving device 30, the timing signal line 21
When receiving the timing signal from the clock distribution circuit 40,
The reception register 30 in synchronization with the synchronization signal distributed by
The data sent through the first to n-th data signal lines 20-1 to 20-n is fetched at 4, and the data transfer is completed.

[0006]

However, in such a conventional technique, the first to n-th data signal lines 20-1 are used.
When the transmission distance of 20 to 20-n becomes long, the first to n-th data signal lines 20-1 to 20-n and the transmission circuit 101 thereof are provided.
/ Due to the propagation delay time of the receiving circuit 305, the transmitting device 10
It takes a considerable amount of time for the data transmitted from the device to reach the receiving device 30.

The first to nth data signal lines 20-
1-20-n and its transmission circuit 101 / reception circuit 305
Due to the variation in the propagation characteristics of, the arrival time (propagation delay time) of the signal from the transmission device 10 to the reception device 30 also varies.

FIG. 11 shows this state. As shown in FIG. 11, the transmission data / transmission timing transmitted from the transmission circuit 101 is the same as the reception data / reception timing in accordance with the propagation delay time T _D and its variation T _V.
Will be received at.

Therefore, the transmitter 10 to the receiver 20
When transmitting data to the device, the repetition period T _P of the data to be transmitted is lengthened (T _P > T _V ) in consideration of the variation T _V of the propagation delay time. That is, it is necessary to perform the data transfer at a time interval that is not affected by the propagation delay time variation T _V.

Generally, when the distance between the transmission lines (the first to n-th data signal lines 20-1 to 20-n) is long, the variation T _V of the propagation delay time becomes large. In such a situation, the repetition cycle T _{P of} data transfer becomes long, and the transmission speed is significantly reduced.

Therefore, an object of the present invention is to correct the propagation delay time corresponding to the signal line of the transmission line and generate a signal synchronized with the synchronizing signal of the receiving device to prevent a decrease in the transmission rate. It is to provide a data transfer system capable of

[0012]

In a data transfer system to which the present invention is applied, first to n-th (n is 2) between a transmission device and a reception device which operate in synchronization with each other in a synchronization cycle.
In this system, data is transmitted from the transmitter to the receiver by using the first to n-th data signal lines.

According to the present invention, the receiving device corresponds to the first to nth data signal lines, and the first to nth shift registers which operate in a shift cycle shorter than the synchronization cycle, and the first to nth shift registers. First to nth switching circuits for switching the output of the nth shift register respectively, and first to nth
And the first to nth counters for controlling the switching circuits so as to output the data from the first to nth signal lines in synchronization with the clock of the receiving device.

In the above data transfer system, it is desirable to have a means for sending a signal indicating whether or not the transmitting device and the receiving device are operating in synchronization from the receiving device to the transmitting device.

In the above data transfer system,
It is preferable to have means for instructing the receiving device to operate from the transmitting device in synchronization with the transmitting device.

Further, in the above data transfer system, a signal indicating that the variation of the propagation delay time from the transmitter to the receiver on the first to nth signal lines has exceeded a predetermined time is received. It is desirable to have means for sending from the device to the sending device.

[0017]

Embodiments of the present invention will now be described with reference to the drawings.

Referring to FIG. 1, in a data transfer system according to an embodiment of the present invention, a transmitter 10 includes first to n-th OR circuits 102-1, ..., 102-n for data.
The OR circuit 102-99 for the timing signal and the test signal generating circuit 103 are provided, and the receiving device 30 uses the first to nth shift registers 301-1 to 301- for the data.
n and a shift register 301-99 for timing signals
And the first to nth switching circuits 302-1 for data,
, 302-n and a switching circuit 302 for timing signals
-99 and the first to nth counters 303 for data-
1, ..., 303-n and a counter 3 for timing signals
03-99, the control circuit 306, and the two storage circuits 30.
8 and 309, and instead of the reception register 304, the first to nth reception registers 30 for data.
10-1, except that it includes the reception registers 304-99 for timing signals.
It has the same structure as that shown in FIG. Therefore, elements having the same functions as those shown in FIG. 10 are designated by the same reference numerals, and only the differences will be described below. In the following description, the subscripts (1, ..., N) are collectively represented by *.

The data / timing signal transmitted from the transmission circuit 101 of the transmission device 10 is the signal line 111-* / 1.
11-99, OR circuit 102-* / 102-99, data signal line 20-* / timing signal line 21, and corresponding shift register 301- * of receiving device 30.
/ 301-99.

The shift register 301-* / 301
-99 is driven by a clock signal having a cycle sufficiently shorter than the repetition cycle of the data sent from the transmission circuit 101. An output is taken out from the shift register 301-* / 301-99 for each flip-flop forming the shift register and is given to the switching circuit 302-* / 302-99. One of the outputs of the shift register selected by the switching circuit 302-* / 302-99 is supplied to the receiving circuit 305 via the receiving register 304-* / 304-99.

Here, the counters 303-* / 303-9
Reference numeral 9 holds contents for instructing the corresponding switching circuit 302-* / 302-99 which input is to be selected. Further, the control circuit 306 controls the counter 303- * corresponding to the state of the reception register at a predetermined cycle.
/ 303-99 is updated. Further, the control circuit 306 reads the contents of the counters 303-* / 303-99 and stores them in the storage circuits 308 and 309, and the respective counters 30-
Storage circuits 308 and 3 calculated for each 3-* / 303-99
The median value of 09 corresponds to the corresponding counter 303-* / 303-
Set to 99. Test signal generation circuit 1 in transmitter 10
03 is driven by the control circuit 306, and the OR circuit 102
-* / 102-99 for all data signal lines 20- *
/ A circuit for sending a test signal to the timing signal line 21.

In the above configuration, the control circuit 306 is
According to the procedure of FIGS. 2 and 3, the test signal generating circuit 10 is sent before the data is transmitted from the transmitter 10 to the receiver 30.
3 and drives all the data signal lines 20-* / timing signal lines 21 through the OR circuits 102-* / 102-99.
Then, the test signal is sent out to adjust the propagation delay time difference between all the data signal lines 20- * and the timing signal line 21. Note that, in FIGS. 2 and 3, when the operations are common for the data and the timing signal, the subscripts (1, ..., N, 99) are omitted to describe those components.

Referring to FIG. 2, first, control circuit 306 initializes counter 303 with signal line 316 (step S1). By initializing the counter 303,
Each switching circuit 302 corresponds to the corresponding shift register 301.
The signal with the smallest delay time (the signal closest to the input of the shift register) is selected from the outputs of the above. Next, the control circuit 3
Reference numeral 06 designates the test signal generation circuit 1 according to the test signal transmission instruction 22.
03 is instructed to send a test signal (step S
2). As a result, the test signal generation circuit 103 operates on the signal line 1
A test signal is sent to the OR circuit 102 through 13. Then, the OR circuit 102 sends a test signal to the data signal line 20 and the timing signal line 21.

After a predetermined time, the control circuit 306 refers to the contents of the reception register 304 through the signal line 314 (step S3). Then, the control circuit 306
Determines whether all the reception registers 304 have received the test signal (step S4). All reception registers 30
When the test signal cannot be received in step 4 (N in step S4)
o), first, the control circuit 306 determines that the first reception register 30
It is determined at 4-1 whether the test signal has been received (step S5). When the test signal can be received by the first reception register 304-1 (Yes in step S5), the signal line 313
-1 is added to the first counter 303-1 by "1" (step S6). As a result, the first switching circuit 302
-1 selects a signal whose delay time is one unit larger in the corresponding first shift register 301-1.

The control circuit 306 repeats steps S5 and S6 for all reception registers, and then returns to step S3. In step S4, if the test signals can be received by all the reception registers 304, the control circuit 30
6 reads the value of the counter 303 through the signal line 316 and stores it in the memory circuit 308 (step S7).

Turning to FIG. 3, subsequently, the control circuit 30 will be described.
Reference numeral 6 initializes the section (A) shown in FIG. 2 and instructs the test signal generation circuit 103 to send a test signal (step S8). As a result, the test signal generation circuit 103 sends a test signal to the OR circuit 102 through the signal line 113. Then, the OR circuit 102 uses the data signal line 20.
And a test signal is sent to the timing signal line 21.

After a predetermined time, the control circuit 306 refers to the contents of the reception register 304 through the signal line 314 (step S9). Then, the control circuit 306
Determines whether all the reception registers 304 have received the test signal (step S10). All receiving registers 3
When the test signal is not received in 04 (No in step S10), first, the control circuit 306 sets the first reception register 3
It is determined at 04-1 whether the test signal has been received (step S11). When the test signal can be received by the first reception register 304-1 (Yes in step S11), the signal line 313-1 increments the first counter 303-1 by "1" (step S12). As a result, the first switching circuit 302-1 causes the corresponding first shift register 301-
A signal having a delay time of 1 unit is selected from the signals of 1.

After the control circuit 306 repeats the above steps S11 and S12 for all the receiving registers,
It returns to step S9. When all the reception registers 304 can receive the test signal in step S10, the control circuit 306 reads the value of the counter 303 through the signal line 316 and stores it in the memory circuit 309 (step S1).
3). Then, the control circuit 306 calculates the median value of the values stored in the memory circuit 308 and the value stored in the memory circuit 309 for each counter, and writes the result in the write path 317.
Is set to the corresponding counter 303 (step S
14).

[0029] Thus, as shown in FIG. 4, a small data propagation delay time difference _T'V can be taken out switch circuit 302- * more a _{(T'P> T'V).}

Referring to FIG. 5, a data transfer system according to another embodiment of the present invention has the same configuration as that shown in FIG. 1 except that the transmitter 10 has an initialization circuit 104. Have. Therefore, components having the same functions as those shown in FIG. 1 are designated by the same reference numerals, and only the differences will be described below. The present embodiment can operate in first to third modes as described below. First, the first mode will be described, and then the second and third modes will be described.

In the first mode of this embodiment, the initialization circuit 104 receives from the control circuit 306 a synchronization display signal indicating that the synchronization of the signal lines within the receiving device 30 has been completed.

In this first aspect, the control circuit 306
The procedure shown in FIGS. 2 and 3 is followed by step S1.
4 is followed by the addition of step 15 as shown in FIG. Therefore, in the first mode, as described with reference to FIGS. 1 to 3, all the data signal lines 2
The propagation delay time difference between 0- * and the timing signal line 21 is adjusted, and further, the control device 306 is used to notify the transmitting device from the receiving device 30 that the adjustment is completed.

[0033] Thus, as shown in FIG. 4, a small data propagation delay time difference _T'V can be taken out switch circuit 302- * more a. Furthermore, the data valid period on the data transfer path can be measured.

In the second mode of the present embodiment, the initialization circuit 104 is driven by the control circuit 306 and waits for the completion of synchronization of the test signal before initializing the transmission circuit 101.

FIG. 7 shows an initialization circuit 1 according to the second embodiment.
The operation of 04 is shown. The initial setting circuit 104 first instructs the control circuit 306 of the receiving device 30 to start the synchronous operation by the initial setting instruction 23 (step Sa1). As a result, the control circuit 306 causes the control circuit 306 to operate as shown in FIGS.
It operates according to the procedure shown in. The initialization circuit 104 refers to the synchronous display signal 24 (step Sa2), and if the synchronous display signal 24 indicates the completion of synchronization, the signal line 1
The initialization command is sent to the transmission circuit 101 by 14 (step Sa3). As a result, the transmission circuit 101 initializes the inside and starts transmission.

As described above, in the second mode, the initialization circuit 104 instructs the transmission device 10 to start the synchronization operation from the transmission device 10 according to the procedure of FIG. 7, and with reference to FIGS. 1 to 3. As described above, the propagation delay time differences between all the data signal lines 20- * and the timing signal lines 21 are adjusted, and when the adjustment is completed, the inside of the transmission circuit 101 is initialized and transmission is started.

[0037] Thus, as shown in FIG. 4, it is possible to automate the adjustment for taking out the small data propagation delay time difference _T'V switching circuit 302- * more.

In the third mode of the present embodiment, the initialization circuit 104 is driven by the control circuit 306, waits for the completion of synchronization of the test signal / detection of the variation abnormality of the propagation delay time, and then the initialization of the transmission circuit 101. Conversion / reception device 3
Detach 0.

In the third mode, the control circuit 306
The procedure shown in FIGS. 2 and 3 is followed by step S1.
4 and the steps S15 to S18 shown in FIG. 8 are added, the initialization circuit 104 operates as shown in FIG.
It operates according to the procedure shown in. Here, in FIG. 8, steps S16 to S18 are further added to that of FIG. 6, and in FIG. 9, step Sa4 is further added to that of FIG.

Referring to FIG. 9, the initial setting circuit 104 is
First, the initial setting instruction 23 instructs the control circuit 306 of the receiving device 30 to start the synchronous operation (step S
a1). As a result, the control circuit 306 is controlled by the control circuit 306 shown in FIGS.
And it operates according to the procedure shown in FIG.

Turning to FIG. 8, the control circuit 306 calculates the difference between the maximum value and the minimum value of each counter after the processing of step S14 of FIG. 3 is completed (step S16). Subsequently, the control circuit 306 determines whether the difference between the counters is larger than a predetermined value (step S17).
When the difference between the counters is equal to or smaller than the predetermined value (No in step S17), the control circuit 306 displays the setting completion on the transmission device 10 through the signal line 24 (step S1).
5). On the contrary, when the difference of the counter is larger than the predetermined value (Yes in step S17), the control circuit 306
Displays the abnormality of the signal line group on the transmission device 10 through the signal line 25 (step S18).

Returning to FIG. 9, the initial setting circuit 104 refers to the synchronous display signal 24 (step Sa2). The control circuit 306 refers to the abnormality display signal 25 while the synchronization display signal 24 indicates that the synchronization is in progress (step Sa4). If the abnormality display signal 25 does not indicate an abnormality, step Sa
Return to 2. If the abnormality display signal 25 indicates an abnormality, the interface between the transmitter 10 and the receiver 30 is disconnected. Further, in step Sa2, the synchronous display signal 24
Indicates that the synchronization has been completed, the initialization circuit 104 instructs the transmission circuit 101 to initialize through the signal line 114 (step Sa3). As a result, the transmission circuit 101 initializes the inside and starts transmission.

As described above, in the third mode, the transmitter 1
From 0, the receiving device 30 is instructed to start the synchronization operation, and
As described with reference to FIG. 3, the propagation delay time differences between all the data signal lines 20- * and the timing signal lines 21 are adjusted. Then, when the adjustment is completed, the transmission circuit 1
The inside of 01 is initialized and transmission is started. When an abnormality is detected in the propagation delay time difference between the test signals, the interface between the transmitter 10 and the receiver 30 is disconnected.

[0044] Thus, as shown in FIG. 4, the signal adjusting for taking out the small data propagation delay time difference _T'V switching circuit 3-2- * more it is possible to automate, during initialization of the receiver Line anomalies can be detected.

[0045]

As described above, the present invention can realize a data transfer system in which variations in propagation delay time of signal lines are small. Further, this makes it possible to realize a high-speed data transfer system that is not affected by the propagation delay time. Furthermore, the initial setting of the transmitter is automated,
It is possible to configure a data transfer system in which the valid period of data transfer is clarified. Furthermore, it is possible to detect the abnormality of the signal line during the initialization of the receiving device from the difference in the dispersion of the propagation delay time between the signal line groups.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a data transfer system according to an embodiment of the present invention.

FIG. 2 is a flowchart for explaining a part of the operation of the control circuit in FIG.

FIG. 3 is a flowchart for explaining the remaining part of the operation of the control circuit subsequent to FIG.

4 is a time chart showing operation timing of data transfer of the data transfer system shown in FIG.

FIG. 5 is a block diagram showing a configuration of a data transfer system according to another embodiment of the present invention.

6 is a flow chart for explaining the operation of one mode of the control circuit in FIG. 5 together with FIG. 2 and FIG.

FIG. 7 is a flowchart for explaining the operation of one mode of the initial setting circuit in FIG.

8 is a flow chart for explaining the operation of another aspect of the control circuit in FIG. 5 together with FIG. 2 and FIG. 3;

9 is a flowchart for explaining the operation of another mode of the initial setting circuit in FIG.

FIG. 10 is a block diagram showing a configuration of a conventional data transfer system.

11 is a time chart showing the operation timing of data transfer of the data transfer system shown in FIG.

[Explanation of symbols]

10 transmitting device 101 transmitting circuit 102-1 ... 102-n, 102-99 OR circuit 103 test signal generating circuit 104 initial setting circuit 20-1 ... 20-n data signal line 21 timing signal line 22 test signal sending instruction 23 initial setting Instruction 24 Synchronous display signal 25 Abnormality display signal 30 Receiving device 301-1 ... 301-n, 301-99 Shift register 302-1 ... 302-n, 302-99 Switching circuit 303-1 ... 303-n, 303-99 Counter 304-1 ... 304-n, 304-99 Reception register 305 Reception circuit 306 Control circuit 308, 309 Storage circuit 40 Clock distribution circuit

Claims (4)

[Claims] 1. A transmission device and a reception device, which operate in synchronization with each other in a synchronization cycle, are connected by first to n-th (n is an integer of 2 or more) data signal lines, and the first to n-th data signals are connected.
In the data transfer system for transferring data from the transmitting device to the receiving device by using the data signal line, the receiving device shifts shorter than the synchronization cycle in correspondence with the first to nth data signal lines. Cycle-operated first to n-th shift registers, first to n-th switching circuits switching the outputs of the first to n-th shift registers, respectively, and the first to n-th switching circuits Respectively, and first to nth counters for controlling so that the data from the first to nth signal lines are output in synchronization with the clock of the receiving apparatus. . 2. The data transfer according to claim 1, further comprising means for sending a signal indicating whether or not the transmitting device and the receiving device are operating in synchronization from the receiving device to the transmitting device. system. 3. The data transfer system according to claim 1, further comprising means for instructing the receiving device to operate from the transmitting device in synchronization with the transmitting device. 4. A signal from the receiving device indicating that the variation in propagation delay time from the transmitting device to the receiving device on the first to n-th signal lines exceeds a predetermined time. The data transfer system according to claim 1, further comprising means for transmitting the data to the transmission device.