JPH06164346A - Output circuit - Google Patents

Abstract

PURPOSE:To prevent a through current from flowing and to reduce variation of a discharging current by cutting off a discharging current which flows so far and supplying a limited discharging current when the input signal of the output circuit varies from a level L to a level H. CONSTITUTION:When the level-L input signal S is impressed from an input terminal 706, a source voltage is applied to the gate 102c of a transistor(TR) 102; and the TR 102 turns OFF and a TR 104 is still ON, so that a discharging current i2 flows up to its permissible level. When the input signal S varies to the level H in the state, the level-H signal S is applied to the gate 304c of a TR 304 and the gate 306c of a TR 306; and the gate 104c of the TR 104 is grounded and the TR 104 turns OFF to cut off the discharging current i2. At this time, the output of a driving circuit 200 enters a high impedance state and the TR 102 is placed its original OFF state. Therefore, both the TRs 102 and 104 turn OFF, and consequently the through current is prevented from being generated. Then the variation rate of a discharging preventive current is suppressed low.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a complementary MOS (hereinafter referred to as "C
(Referred to as “MOS”) integrated circuit.

[0002]

2. Description of the Related Art Output circuits in CMOS integrated circuits are
A CMOS transistor having a large gate width, that is, a large size is used in the final stage because it plays a role of driving another circuit by transmitting a signal over a long distance. Figure 2
FIG. 6 is a diagram showing a final stage CMOS transistor of the output circuit.

When input signals S ₁ and S ₂ of the CMOS transistor 10 change, a through current I flowing through the CMOS transistor 10 via the PMOS transistor 11 and the NMOS transistor 12 is generated.
The rate of change dI / dt of this through current I is extremely large, which affects the power supply system as noise, which is one of the causes of malfunction.

FIG. 3 shows a first method for preventing this shoot-through current.
It is the timing chart which showed one. CM shown in FIG.
Shifting the timing of the input signal S ₂ of the input signal S _1, the NMOS transistor 12 of the PMOS transistor 11 constituting the OS transistor 10 as shown in FIG. 3, off both the PMOS transistor 11 and NMOS transistor 12 when the signal change The generation of the through current I can be prevented by creating the moment.

Further, the signal output line 13 shown in FIG.
This CMOS transistor has a large load capacity 14.
Input signal S of the register 10₁ , S₂ Is larger each time
Charging current i₁ , Or discharge current i₂ Flow through them
Change rate di₁ / Dt, di ₂ / Dt is also large, which is also
It affects the power supply system as noise and is one of the causes of malfunction.
It

FIG. 4 is a diagram showing an output circuit according to a conventional proposal constructed so as to suppress the rate of change of the charging / discharging current (see Japanese Patent Application Laid-Open No. 3-40313). When an L-level input signal S is input to this output circuit, the input signal S causes the outputs of the inverters 20, 22, 24, and 26 to be at the H level or L level shown in the figure, and the CMO at the output end is obtained.
The drive current i _b1 for driving the PMOS transistor 42 of the load drive circuit 40 including the S transistor flows into the PMOS drive circuit 28, and the charging current i ₁ flows through the PMOS transistor 42.

At this time, the NMOS drive circuit 30 is an NMOS
It acts to ground the gate of transistor 44,
The MOS transistor 44 is turned off. Here, when the signal level of the input signal S is inverted from the L level to the H level, this time, the gate of the PMOS transistor 42 is PM.
PMOS connected to the power supply by the OS drive circuit 28
The transistor 42 shifts to the cutoff state, and at the same time, the driving current i _b2 flows through the NMOS driving circuit 30, whereby the discharging current i ₂ passes through the NMOS transistor 44.
Flows.

Here, since the PMOS drive circuit 28 is provided with the diode-connected PMOS transistor 15, the gate of the PMOS transistor 42 does not fall to the ground level, and thus the charging current i ₁ is limited, which causes The rate of change d _i1 / dt is also suppressed to a low level, and the noise level is suppressed. Further, similarly to this, since the NMOS drive circuit 30 is provided with the diode-connected NMOS transistor 16, the NM
The gate of the OS transistor 44 does not rise to the power supply voltage level, so that the discharge current i ₂ is limited, and thus the rate of change d _i2 / dt thereof is suppressed low, and the noise level during discharge is also suppressed.

[0009]

In constructing the output circuit, the method shown in FIG. 3 is applied to the circuit shown in FIG. 4 in order to realize both prevention of shoot-through current and suppression of change rate of charge / discharge current. It is conceivable to add a circuit for realizing the timing shown in FIG. 3 to the front side of the PMOS drive circuit 28 and the NMOS drive circuit 30. However, even in this case, the gate of the PMOS transistor 42 does not fall to the ground level and therefore the charging current i ₁ is suppressed low, and the gate of the NMOS transistor 44 does not rise to the power supply level and therefore the discharging current is also suppressed low. However, even though the drive circuit 40 including a large-sized CMOS transistor is arranged at the output end so that a large current can flow, it cannot be fully utilized, and a stable charging / discharging current also flows. As a result, it will decrease.

In view of the above circumstances, the present invention realizes both prevention of shoot-through current and reduction of rate of change of charge / discharge current, and a drive circuit that does not limit the charge / discharge current that can be stably supplied. It is an object of the present invention to provide an output circuit capable of flowing a charging / discharging current up to an original current value.

[0011]

The output circuit of the present invention which can achieve the above object is as follows: (1) A first source and drain in which a source and a drain are connected in series from the power source side in order between a power source and a ground. PMO
A load drive circuit including an S-transistor and a first NMOS transistor and having the drains of the first PMOS transistor and the drain of the first NMOS transistor connected to each other as output ends (2) Between a power supply and a ground A second PMO whose source and drain are connected in series in order from the power supply side
An S-transistor, a second NMOS transistor, and a third NMOS transistor, and the drain of the second PMOS transistor and the second PMOS transistor connected to each other.
The drain of the NMOS transistor of the first PMO
S-transistor PMOS drive circuit connected to gate of transistor (3) Third PMO in which source and drain are connected in series in order from power supply side between power supply and ground
The drain of the fourth PMOS transistor and the drain of the fourth NMOS transistor which are connected to each other are composed of an S-transistor, a fourth PMOS transistor and a fourth NMOS transistor.
NMOS connected to the gate of MOS transistor
Driving circuit (4) Fifth PMOS transistor having drain and source connected to the source of the second N-channel transistor and the drain of the third NMOS transistor and the ground, which are connected to each other (5) Connected to each other A drain of the third P-channel transistor and a source of the fourth P-channel transistor, and a power source, and a fifth NMOS transistor connected to the drain and the source respectively. (6) The output terminal is the third NMOS A first inverter connected to the gate of the transistor and the gate of the third PMOS transistor, and the input end of which is connected to the gate of the fifth PMOS transistor and the gate of the fifth NMOS transistor (7) Output The end is the input end of the first inverter A second input connected to the gate of the second PMOS transistor, the gate of the second NMOS transistor, the gate of the fourth PMOS transistor and the gate of the fourth NMOS transistor It is equipped with an inverter.

[0012]

Since the output circuit of the present invention has the above-mentioned constitutions (1) to (7), the through current is prevented and the charging / discharging is performed only at the time when the level of the input signal changes, as shown in the embodiments described later. The current that is suppressed and flows stably thereafter can flow to the level of the drive capability that the load drive circuit originally has.

[0013]

EXAMPLES Examples of the present invention will be described below. Figure 1
FIG. 3 is a circuit diagram showing an embodiment of an output circuit of the present invention.
This output circuit includes a load drive circuit 100, a PMOS drive circuit 200, an NMOS drive circuit 300, a fifth PMOS transistor 400, and a fifth NMOS transistor 50.
0, a first inverter 600, and a second inverter 700.

The load driving circuit 100 is composed of a first PMOS transistor 102 and a first NMOS transistor 104 whose sources and drains are connected in series between the power source and the ground in order from the power source side, and are connected to each other. The drain 102a of the first PMOS transistor 102 and the drain 104a of the first NMOS transistor 104 are connected to the output terminal 106.

Further, the PMOS drive circuit 200 includes a second PMOS transistor 202, a second NMOS transistor 204, and a third PMOS transistor 202 whose sources and drains are connected in series from the power source side in series between the power source and the ground.
Drain 20 of the second PMOS transistor 202, which is composed of the NMOS transistor 206 of
2a and the drain 2 of the second NMOS transistor 204
04a is the gate 1 of the first PMOS transistor 102
02c.

The NMOS drive circuit 300 has a third PMOS transistor 302, a fourth PMOS transistor 304, and a fourth PMOS transistor 304, in which the source and the drain are connected in series from the power source side in series between the power source and the ground.
Drain 30 of the fourth PMOS transistor 304, which is composed of the NMOS transistor 306 of FIG.
4a and the drain 306a of the fourth NMOS transistor 306 are connected to the gate 104c of the first NMOS transistor 104.

The source 204b of the second N-channel transistor 204 and the drain 206a of the third NMOS transistor 206, which are connected to each other, and the ground are connected to the drain 400a and the source 400b of the fifth PMOS transistor, respectively. . Also, a third P-channel transistor 30 connected to each other
The second drain 302a, the source 304b of the fourth P-channel transistor 304, and the power supply are connected to the drain 500a and the source 500b of the fifth NMOS transistor, respectively.

Further, the first inverter 600 and the second inverter 700 are composed of PMOS transistors 602 and 702 and NMOS transistors 604 and 704 whose sources and drains are connected in series between the power source and the ground in order from the power source side. Configured drains 602a, 604a; 702a, 7 connected to each other
04a is an output terminal, and gates 602c and 6 are connected to each other.
04c; 702c and 704c form the input end.

The output terminal of the first inverter 600 is connected to the gate 206c of the third NMOS transistor 206 and the gate 302c of the third PMOS transistor 302, and the input terminal of the first inverter 600 is the fifth terminal.
Is connected to the gate 400c of the PMOS transistor 400 and the gate 500c of the fifth NMOS transistor 500.

The output terminal of the second inverter 700 is connected to the input terminal of the first inverter, and the input terminal of the second inverter 700 is connected to the second PMOS transistor 2
02 gate 202c, second NMOS transistor 2
04 gate 204c, fourth PMOS transistor 3
04 gate 304c and the fourth NMOS transistor 306 gate 306c. The input terminal of the second inverter 700 is connected to the input terminal 706 of this output circuit.

In the output circuit configured as described above, the case where the L-level input signal S is constantly input from the input terminal 706 is considered as a starting point. In this case, the signal levels of the second inverter 700 and the first inverter 600 are respectively inverted to output H-level or L-level signals as shown in the figure, the second PMOS transistor 202 is turned on, and the power supply voltage becomes the first level. PMO
Since this is applied to the gate 102c of the S transistor 102, the first PMOS transistor 102 is in the off state. Further, the power supply voltage is applied to the gate 104c of the first NMOS transistor 104 via the third PMOS transistor 302 and the fourth PMOS transistor 304, and thus the first NMOS transistor 104 is in the ON state, The discharge current i ₂ is flowing. In this state, the first NMOS transistor 10
The gate 104c of No. 4 has only the PMOS transistor (the third PMOS transistor 302 and the fourth PMOS transistor 302).
Since the power supply voltage is applied via the transistor 304), the power supply voltage itself is almost always the first NMOS.
The discharge current i _{2 that} is applied to the gate 104c of the transistor 104 and constantly flows can flow without being limited to the allowable current of the first NMOS transistor 104.

Consider the moment when the input signal S changes from this steady state to the H level. At this time, the input terminal 70
The H-level input signal S applied to 6 is immediately applied to the gate 304c of the fourth PMOS transistor 304 and the gate 306c of the fourth NMOS transistor 306 as it is, and the fourth PMOS transistor 304 is turned off and The fourth NMOS transistor 306 is turned on, the gate 104c of the first NMOS transistor 104 is connected to the ground, and the first NMO
The S transistor 104 is turned off and the discharge current i ₂
Shut off. At this moment, the output of the PMOS drive circuit 200 shifts to the high impedance state, and the first PMO
The S-transistor 102 remains in the original off state. Therefore, at this moment, both the first PMOS transistor 102 and the first NMOS transistor 104 are turned off, and both are turned off, so that the generation of the through current is prevented.

Next, when the propagation delay time of the second inverter 700 has elapsed, the output terminal of the second inverter 700 changes to the L level. Then, the signal of this level is applied to the gate 400c of the fifth PMOS transistor 400, and the fifth PMOS transistor 400 is turned on. Immediately before that, since the second NMOS transistor 204 has already transitioned to the ON state, the first PM
The gate 102c of the OS transistor 102 is the second NM
It is connected to the ground through the OS transistor 204 and the fifth PMOS transistor 400, but the PMO
S transistor (fifth PMOS transistor 400)
It will be connected to the ground via
A voltage higher than the ground level, for example, by about 1 V is applied to the gate of the PMOS transistor 102 of the first PMOS transistor 102, whereby the first PMOS transistor 102 is turned on with a predetermined resistance value, and the limited charging current i ₁
Will flow.

After that, when the propagation delay time of the first inverter 600 further elapses, the first inverter 600
The output terminal of changes to H level. Then, the gate 102c of the first PMOS transistor 102 is changed to the second gate
Of the first PMOS transistor 102 is connected to the ground via the NMOS transistor 204 and the third NMOS transistor 206, and is connected to the ground only via the NMOS transistor this time. Applied,
Thus, rather than charging current i ₁ a was restricted as described above, the charging current i ₁ in which the first PMOS transistor 102 is not restricted to a current value of the flow originally flows.
Thus, in this output circuit, when the input signal S changes from the L level to the H level, the discharge current i ₂ which has been flowing until then is interrupted first, and then the limited charging current i ₁ flows, which causes The rate of change di ₁ / dt of the charging current i ₁ is reduced and then the restriction is lifted. Therefore, the charging current i in the steady state is not limited and the original capability of the output circuit is exhibited.

Although the case where the input signal S changes from the L level to the H level has been described here, even when the input signal S changes from the H level to the L level, the first P signal is generated.
The roles of the MOS transistor 102 and the first NMOS transistor 104, the PMOS drive circuit 200 and the NMOS
If the roles of the drive circuit 300, the roles of the fifth PMOS transistor 400 and the fifth NMOS transistor 500, and the charging current i ₁ and the discharging current i ₂ are exchanged, the same thing as described above holds.

[0026]

As described above, since the output circuit of the present invention has the above configuration, the through current is prevented and the rate of change of the charge / discharge current is suppressed to a low level.
In addition, the original load driving capability of the output circuit is exhibited.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of an output circuit of the present invention.

FIG. 2 is a diagram showing a final stage CMOS transistor of an output circuit.

FIG. 3 is a timing chart showing one method of preventing a shoot-through current.

FIG. 4 is a diagram showing an output circuit according to a conventional proposal configured to suppress the rate of change of charge / discharge current.

[Explanation of symbols]

 100 load drive circuit 102 first PMOS transistor 104 first NMOS transistor 106 output terminal 200 PMOS drive circuit 202 second PMOS transistor 204 second NMOS transistor 206 third NMOS transistor 300 NMOS drive circuit 302 third PMOS Transistor 304 Fourth PMOS transistor 306 Fourth NMOS transistor 400 Fifth PMOS transistor 500 Fifth NMOS transistor 600 First inverter 700 Second inverter 706 Input terminal

Claims (1)

[Claims] 1. A first source and a drain connected in series between a power source and a ground in order from the power source side.
Drive circuit having a drain of the first PMOS transistor and a drain of the first NMOS transistor, which are connected to each other, as output terminals, and a power supply between a power supply and a ground. A second PMOS transistor, a second NMOS transistor, and a third N transistor whose source and drain are connected in series in this order from the side.
A drain of the second PMOS transistor and a second NM which are formed of a MOS transistor and are connected to each other.
A PMO in which the drain of the OS transistor is connected to the gate of the first PMOS transistor transistor
S drive circuit, a third PMOS transistor, a fourth PMOS transistor, and a fourth N transistor in which a source and a drain are connected in series between the power source and the ground in order from the power source side.
The drain of the fourth PMOS transistor and the drain of the fourth NMOS transistor which are MOS transistors and are connected to each other are connected to the first NMOS.
An NMOS drive circuit connected to the gate of the transistor; a source of the second N-channel transistor and a drain of the third NMOS transistor connected to each other; A PMOS transistor; a drain of the third P-channel transistor and a source of the fourth P-channel transistor connected to each other; a fifth NMOS transistor whose drain and source are connected to a power supply; A first inverter connected to the gate of the third NMOS transistor and the gate of the third PMOS transistor, and having the input terminal connected to the gate of the fifth PMOS transistor and the gate of the fifth NMOS transistor; And out With one end connected to the input terminal of said first inverter, the gate of the input terminal and the second PMOS transistor, a gate of the second NMOS transistor, the fourth PMO
An output circuit comprising a second inverter connected to the gate of the S transistor and the gate of the fourth NMOS transistor.