JPH06164244A - Fm demodulator - Google Patents

Abstract

(57) [Abstract] [Purpose] To improve the SN ratio and resolution of the demodulated signal while suppressing the inversion phenomenon related to the reproduced FM luminance signal of the VTR. [Structure] Two subtractors 14 and 15 are provided to remove phase distortion from the output signals of the variable amplifier circuits 12 and 13. The first subtractor 14 located in the main path system is provided with a frequency characteristic that gives the highest priority to the improvement of the noise balance at the time of low luminance, and the second subtracter 15 located in the sub path system is missing a zero-cross point. It has frequency characteristics with prevention as the highest priority. The output signal of the first subtractor 14 is directly given to the first limiter circuit 16, and the output signal of the second subtractor 15 is given to the second limiter circuit 17 via the delay circuit 21. The three mono-multi circuits 18, 19, 20 and one A are arranged so that the zero-cross points of the sub-path system are replaced only when the zero-cross points are missing in the main-path system.
A timing circuit 41 is configured with the ND circuit 22.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a VTR (Video Tape R).
The present invention relates to an FM demodulation device that suppresses the inversion phenomenon of a reproduction signal in a magnetic recording / reproduction device such as ecorder).

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing an example of the configuration of a conventional FM demodulator for a VTR. In FIG. 6, 1 is an input terminal to which a reproduced FM luminance signal from the VTR head is input, and 2 and 3 are first T1s having the same delay time T1.
And a second delay circuit (DL), 4 is an adder, 5 is a variable amplifier circuit (GCA), 6 is a subtractor, and 7 is an equalizer (E).
Q), 8 is a limiter circuit (LIM), 9 is a monostable multivibrator circuit (hereinafter abbreviated as monomulticircuit (MM)), 10 is a low-pass filter (LPF), 11 is an output for outputting a reproduction luminance signal. It is a terminal.

The operation of the conventional FM demodulator having the above structure will be described in detail below.

First, a reproduced FM luminance signal having a frequency characteristic as shown in FIG. 7 is input from the input terminal 1. The output characteristics of the head show a tendency that the output amplitude decreases in the high frequency region, and therefore the CN ratio (carrier to noise ratio) deteriorates in the high region. The input terminal 1 is connected in series to the first and second delay circuits 2 and 3 having the same delay time T1. Then, the input signal of the first delay circuit 2 and the output signal of the second delay circuit 3 are added by the adder 4.
The signals added by the adder 4 are input to the variable amplification circuit 5,
By subtracting the output signal of the first delay circuit 2 from the output signal of the variable amplifier circuit 5 by the subtractor 6, frequency characteristics without phase distortion are realized.

Further, the output signal of the subtractor 6 is connected to the equalizer 7 in order to adjust the frequency characteristic and the phase characteristic of the output signal of the subtractor 6. The output signal of the equalizer 7 is
As shown in FIG. 8, the frequency characteristic has a peak near the white peak frequency (7 MHz in the S-VHS mode) of the reproduced FM luminance signal. The output signal of the equalizer 7 is converted into a square wave by the limiter circuit 8, and the zero-cross point is detected by the mono-multi circuit 9 triggered by both the rising and falling edges, so that the reproduced FM luminance signal is doubled. It becomes a pulse signal with a frequency and a constant amplitude and a constant pulse width. When this pulse signal is passed through the low pass filter 10, a reproduction luminance signal can be taken out from the output terminal 11.

[0006]

Generally, in the FM demodulator which handles the reproduced FM luminance signal as described above, a so-called inversion phenomenon, which is a lack of a zero cross point in the overshoot portion caused by the emphasis during recording, easily occurs. .
Therefore, in the conventional FM demodulator shown in FIG. 6, the frequency characteristic of the equalizer 7 is set so that peaking is applied near the white peak frequency (7 MHz) of the reproduced FM luminance signal so that the inversion phenomenon does not occur. However, this causes a problem that the SN ratio of the demodulated signal is adversely affected.

That is, since the carrier level is set to have a peak in the vicinity of 7 MHz, the noise level also has a peak in the vicinity of 7 MHz as shown in FIG. 8. As a result, at low luminance (around 6 MHz), The noise level in the upper sideband is higher than that in the lower sideband. Due to this poor noise balance, the SN ratio after demodulation, and thus the resolution, is poor.

An object of the present invention is to improve the SN ratio and resolution of a demodulated signal while suppressing the inversion phenomenon.

[0009]

In order to achieve the above object, the present invention provides a main path system having a frequency characteristic in which the improvement of noise balance at low brightness is given the highest priority, and the prevention of the loss of the zero cross point is the highest priority. The sub-path system having the frequency characteristics set in parallel and the sub-path system signal are delayed for a certain time with respect to the main-path system signal, and the zero-cross point of the sub-pass system is generated only when the zero-cross point is missing in the main path system. It adopts a configuration that replaces.

Specifically, the invention of claim 1 is, as shown in FIGS. 1 and 4, an equalizer (EQ) for adjusting the frequency characteristic and phase characteristic of the reproduced FM luminance signal from the head of the magnetic recording / reproducing apparatus. ) 7, the first delay circuit (DL) 2 to which the output signal of the equalizer 7 is input, and the first delay circuit 2 having the same delay time T1 as that of the first delay circuit 2
Of the output signal of the second delay circuit 3, an adder 4 for adding the input signal of the first delay circuit 2 and the output signal of the second delay circuit 3, First and second variable amplifier circuits (GCA) for amplifying output signals
12, 13 and the first frequency characteristic is set so that the noise balance at the time of low luminance for subtracting the output signal of the first delay circuit 2 from the output signal of the first variable amplifier circuit 12 is improved. The second subtracter 14 and the second variable amplifier circuit 13 having the frequency characteristic set so that the output for subtracting the output signal of the first delay circuit 2 from the output signal of the second variable amplifier circuit 13 does not have a missing zero-cross point. Subtractor 15 and the first subtractor 1
A first limiter circuit (LIM) 16 for converting the output signal of No. 4 into a square wave, and a third delay circuit 21 having a delay time T2 and receiving the output signal of the second subtractor 15 are input.
A second limiter circuit 17 for converting the output signal of the third delay circuit 21 into a square wave; both rising and falling edges of the output signal of the first limiter circuit 16; and a second limiter circuit. The zero crossing point missing in the output signal of the first subtractor 14 is compensated at the zero crossing point in the output signal of the second subtractor 15 at the timing based on both the rising and falling edges of the output signal of 17 Timing circuits 41 and 42 for outputting pulse signals, and a low pass filter (L) for converting the output signals of the timing circuits 41 and 42 into reproduction luminance signals.
PF) 10 is adopted.

According to the second aspect of the invention, as shown in FIG.
The timing circuit 41 is a first mono-multi circuit (MM) 18 that outputs a negative logic pulse signal having a constant pulse width W1 when triggered by both the rising and falling edges of the output signal of the first limiter circuit 16. , A second mono-multi circuit 19 that outputs a negative logic pulse signal having a constant pulse width W2 by being triggered by both rising and falling edges of the output signal of the second limiter circuit 17, and the first and second mono-multi circuits. An AND circuit 22 to which the output signals of the multi-circuits 18 and 19 are input, and a third mono-multi circuit 20 that is triggered only by the falling edge of the output signal of the AND circuit 22 and outputs a pulse signal having a constant pulse width And decided to prepare.

Further, in the invention of claim 3, the output pulse width W2 of the second mono-multi circuit 19 is set to be smaller than the output pulse width W1 of the first mono-multi circuit 18.

According to the invention of claim 4, as shown in FIG.
The timing circuit 42 is triggered only by the rising edge of the output signal of the first limiter circuit 16 to output a negative logic pulse signal having a constant pulse width W1, and a second mono-multi circuit (MM) 23. The second mono-multi circuit 24, which is triggered only by the rising edge of the output signal of the limiter circuit 17 and outputs the negative logic pulse signal of the constant pulse width W2, and the falling edge of the output signal of the first limiter circuit 16 only. Third mono-multi circuit 25 that is triggered to output a negative logic pulse signal having a constant pulse width W3
And a fourth mono-multi circuit 26 that outputs a negative logic pulse signal having a constant pulse width W4 by being triggered only by the falling edge of the output signal of the second limiter circuit 17, and the first and second mono-multi circuits. A first AND circuit 29 to which the output signals of 23 and 24 are input, and a second A circuit to which the output signals of the third and fourth mono-multi circuits 25 and 26 are input.
An ND circuit 30, and a fifth mono-multi circuit 27 that outputs a negative logic pulse signal with a constant pulse width by being triggered only by the falling edge of the output signal of the first AND circuit 29,
A sixth mono-multi circuit 28 that outputs a negative logic pulse signal having the same pulse width as that of the fifth mono-multi circuit 27 by being triggered only by the falling edge of the output signal of the second AND circuit 30; The third AND circuit 31 to which each output signal of the mono-multi circuits 27 and 28 of 6 is input.

According to a fifth aspect of the present invention, the output signals of the first and second AND circuits 29 and 30 are set to the third one so as to reduce the number of mono-multi circuits in the timing circuit 42 of FIG. A fifth mono-multi circuit is provided, which is input directly to the AND circuit 31 and is triggered only by the falling edge of the output signal of the third AND circuit 31 to output a pulse signal having a constant pulse width. .

In the sixth aspect of the invention, the output pulse width W2 of the second mono-multi circuit 24 is set smaller than the output pulse width W1 of the first mono-multi circuit 23,
And the output pulse width W4 of the fourth mono-multi circuit 26
Is set to be smaller than the output pulse width W3 of the third mono-multi circuit 25.

[0016]

According to the first aspect of the present invention, the frequency characteristic of the first subtractor 14 belonging to the main path system having the first limiter circuit 16 is such that the improvement of the noise balance at low luminance is given the highest priority. In order to extend the frequency band of the demodulated signal, for example, it is set to have a broad peak near 6 MHz (see FIG. 3). Therefore, the first subtractor 14
There may be a case where the zero-cross point is missing in the output signal of. On the other hand, the frequency characteristic of the second subtracter 15 belonging to the sub-path system having the third delay circuit 21 and the second limiter circuit 17 is, for example, the reproduction FM luminance, with the prevention of the inversion phenomenon as the highest priority. It is set so that peaking is applied near the white peak frequency (7 MHz) of the signal (see FIG. 8). Moreover, unlike the output signal of the first subtractor 14, the output signal of the second subtractor 15 is delayed by the third delay circuit 21 by the fixed time T2. As a result, the zero-cross points missing due to carrier loss in the main path system are replaced by the zero-cross points in the sub-path system by the timing circuits 41 and 42, and the inversion phenomenon is removed.
Further, since the zero-cross point of the main path system is prioritized in the part where the zero-cross point is not missing in the main path system, the SN ratio and the resolution are improved.

According to the second aspect of the invention, the timing circuit 41 for compensating for the zero-cross point is composed of three mono-multi circuits 18 to 20 and one AND circuit 22 as shown in FIG. At this time, the replacement of the zero-cross points is achieved by taking the logical sum (negative logic) in the AND circuit 22. Further, since the third mono-multi circuit 20 outputs a pulse signal having a constant pulse width, the linearity of the demodulated signal is improved.

Further, according to the invention of claim 3, the output pulse width W2 of the second mono-multi circuit 19 is set smaller than the output pulse width W1 of the first mono-multi circuit 18, so that the linearity in the high range is achieved. Can be further improved. In other words, since the reversal phenomenon occurs in the overshoot portion due to the emphasis during recording, the cycle is short in the high frequency region. Therefore, if the output pulse width W2 of the second mono-multi circuit 19 of the sub-pass system is narrowed, the linearity can be improved up to the high frequency range.

According to the fourth aspect of the present invention, the timing circuit 42 for compensating the zero-cross point is composed of six mono-multi circuits 23 to 28 and three AND circuits 29 to 31, as shown in FIG. To do. At this time, the zero-cross points in the direction from negative to positive and the zero-cross points in the opposite direction of the output signals of the first and second subtractors 14 and 15 are separately processed, and three AND circuits 29 to 31 are used. The replacement of the zero-cross points is achieved. Further, since the fifth and sixth mono-multi circuits 27 and 28 output pulse signals having the same pulse width, the linearity of the demodulated signal is improved.

According to the invention of claim 5, a circuit having the same function as the timing circuit 42 shown in FIG. 4 can be constituted by five mono-multi circuits and three AND circuits. Moreover, since the fifth mono-multi circuit outputs a pulse signal having a constant pulse width, the linearity of the demodulated signal is improved.

According to the invention of claim 6, the output pulse widths W1 and W2 of the first and second mono-multi circuits 23 and 24, which are both triggered only by the rising edge, and both are triggered only by the falling edge. The output pulse widths W3 and W4 of the third and fourth mono-multi circuits 25 and 26 are set so as to satisfy W1> W2 and W3> W4. Therefore, as in the case of the invention of claim 3, It is possible to further improve the linearity in the high range.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram showing the configuration of an FM demodulator according to a first embodiment of the present invention.
In FIG. 1, 1 is an input terminal to which a reproduced FM luminance signal from a VTR head is input, 2 and 3 are first and second delay circuits (DL) having the same delay time T1, 4 is an adder,
7 is an equalizer (EQ), 10 is a low-pass filter (L
PF) and 11 are output terminals. However, unlike the case of the conventional example (FIG. 6), the input terminal 1 and the first delay circuit 2 are
The equalizer 7 is interposed between and. 12 and 13 are first and second variable amplifier circuits (GCA), 14 and 15 are first and second subtractors, 16 and 17 are first and second limiter circuits (LIM), and 18 and 19 are First and second mono-multi circuits (MM) triggered by both rising and falling edges, 20 is a third mono-multi circuit triggered only by falling edges, and 21 is a third mono-multi circuit having a delay time of T2. 3 is a delay circuit, and 22 is an AND circuit. 41
Is the first to third mono-multi circuits 18 to 20 and AND
It is a timing circuit composed of the circuit 22.

The operation of the FM demodulating apparatus according to the first embodiment constructed as above will be described in detail below. FIG. 2 is a signal waveform diagram of each part in FIG.

First, when a reproduced FM luminance signal having a frequency characteristic as shown in FIG. 7 is input from the input terminal 1, the reproduced FM luminance signal has its frequency characteristic and phase characteristic adjusted by the equalizer 7. The output side of the equalizer 7 is connected in series to the first and second delay circuits 2 and 3 having the same delay time T1, and the input signal of the first delay circuit 2 and the output signal of the second delay circuit 3 are connected. Are added by the adder 4, and the adder 4
The output signal of is supplied to the first and second variable amplifier circuits 12 and 13, respectively. Then, in order to take phase distortion from the output signal of the first variable amplifier circuit 12, the first delay circuit 2
Is subtracted by the first subtractor 14 (waveform A in FIG. 2). However, the frequency characteristic of the first subtractor 14 is
As shown in FIG. 3, the improvement of the noise balance at the time of low luminance is given the highest priority, and the frequency band of the demodulated signal is extended so as to have a broad peak near 6 MHz. At the edge portion where the video signal sharply rises from the black level to the white level, the lower sideband component is emphasized as compared with the carrier component of the reproduced FM luminance signal, so that α and β in the waveform A in FIG. As shown in
The output signal of the subtractor 14 may lack a zero-cross point.

The output signal of the first subtractor 14 is converted into a square wave by the first limiter circuit 16 and by the first mono-multi circuit 18 triggered by both rising and falling edges (zero cross points). , A negative logic pulse signal having a constant amplitude and a constant pulse width, which has twice the frequency of the reproduced FM luminance signal (waveform B in FIG. 2). In addition,
1/2 of the maximum carrier frequency (about 10 MHz)
Is about 50 ns, the linearity of the FM demodulator cannot be secured unless the pulse width is within 50 ns. Therefore, in this embodiment, the output pulse width W1 of the first mono-multi circuit 18 is set to about 35 ns.

On the other hand, in order to obtain phase distortion from the output signal of the second variable amplifier circuit 13, the output signal of the first delay circuit 2 is subtracted by the second subtractor 15 (waveform C in FIG. 2). ). However, the frequency characteristic of the second subtractor 15 is shown in FIG.
As described above, the setting is made in the same manner as the conventional example. That is, as a result of setting the frequency characteristics so that peaking is applied near the white peak frequency (7 MHz), the carrier component of the reproduced FM luminance signal and the lower sideband are generated at the edge portion where the video signal sharply rises from the black level to the white level. The balance with the components is improved and the inversion phenomenon does not occur. Therefore, unlike the waveform A, the missing of zero-cross points does not occur unlike the waveform C in FIG.

The output signal of the second subtractor 15 is about 10n.
It is supplied to the third delay circuit 21 having a delay time T2 of s (waveform D in FIG. 2), converted into a square wave by the second limiter circuit 17, and further triggered by both rising and falling edges. By the second mono-multi circuit 19 that is a negative logic pulse signal having a constant amplitude and a constant pulse width (W2 = about 35 ns) having a frequency twice that of the reproduced FM luminance signal (waveform E in FIG. 2). .

First and second mono-multi circuits 18, 19
Each output signal of is logically summed (negative logic) by the AND circuit 22 and has a pulse waveform like the waveform F in FIG. It can be seen that the pulse signal at the zero-cross point, which is missing due to the inversion phenomenon in the waveform B in FIG. 2, is compensated by the pulse signal shown in the waveform E, and the inversion phenomenon is suppressed in the waveform F. Here, the reason why the third delay circuit 21 delays by about 10 ns is that the falling edge (that is, the zero-cross point) of the waveform B on the main path side on the sub path side when the logical sum is obtained by the AND circuit 22. This is because it is not affected by the falling edge of a certain waveform E.

Further, the output signal of the AND circuit 22 is connected to the third mono-multi circuit 20 which is triggered only by the falling edge, and the pulse width is constant (about 20 ns) as shown by the waveform G in FIG. You can get them. In the output waveform F of the AND circuit 22, the compensated pulse width (X1) is smaller than the other pulse widths (X2). Therefore, the linearity after demodulation is not improved unless the third mono-multi circuit 20 is connected. . When the third mono-multi circuit 20 is connected, the pulse widths become equal, and the linearity of the FM demodulator can be improved. At that time, the compensated pulse is about 1
In consideration of the delay of 0 ns, the output pulse width of the third mono-multi circuit 20 is set to about 20 ns. When the pulse signal of waveform G is passed through the low pass filter 10, it can be taken out from the output terminal 11 as a reproduction luminance signal.

As described above, according to this embodiment, the output signal (waveform A in FIG. 2) of the first subtractor 14 which gives the highest priority to the improvement of the noise balance at the time of low luminance and the zero cross point. A signal (waveform D in FIG. 2) obtained by delaying the output signal of the second subtractor 15 which gives the highest priority to the loss prevention by about 10 ns by the third delay circuit 21, and the limiter circuit 16, respectively.
17 and mono-multi circuit 18, 19
Since it is input to the D circuit 22 and the logical sum is obtained, when the zero-cross point of the output signal of the first subtractor 14 is missing, the result is compensated at the zero-cross point of the output signal of the second subtractor 15, resulting in inversion. The phenomenon can be suppressed. In addition, since the output signal of the second subtractor 15 is delayed by the third delay circuit 21, the zero cross point is not missing in the portion where the zero cross point in the output signal of the first subtractor 14 is not missing. Priority is given to ensuring a high SN ratio and high resolution.

In the above description, the output pulse widths W1 and W2 of the first and second mono-multi circuits 18 and 19 are made equal (W1 = W2 = about 35 ns), but W2 is smaller than W1 (W1> W2). For example, the output pulse width W1 of the first mono-multi circuit 18 is about 35 ns, and the output pulse width W2 of the second mono-multi circuit 19 is about 15 n.
Let s. Even if W2 is set small in this way, as a result of the replacement of the zero-cross points as described above, the high SN ratio
Inversion phenomenon can be suppressed while ensuring high resolution. Moreover, by setting the output pulse width W2 of the second mono-multi circuit 19 to be as small as about 15 ns, the linearity in the high frequency band can be further improved. In other words, since the reversal phenomenon occurs in the overshoot portion due to the emphasis during recording, the cycle is short in the high frequency region. Therefore, if the output pulse width W2 of the second mono-multi circuit 19 on the sub-path side is reduced, the linearity can be improved up to the high frequency range.

(Embodiment 2) FIG. 4 is a block diagram showing the configuration of an FM demodulator according to a second embodiment of the present invention.
In FIG. 4, reference numerals 23 and 24 denote first and second mono-multi circuits which are triggered only by rising edges, and 25 and 2 respectively.
6, 27 and 28 are third to sixth monomulti circuits which are triggered only by the falling edge, and 29, 30, 31 are the first
~ The third AND circuit. Reference numeral 42 denotes the first to sixth mono-multi circuits 23 to 28 and the first to third AND circuits 29.
Is a timing circuit composed of 31 to 31. Since the other points are the same as those of the first embodiment, detailed description of the configuration will be omitted.

The operation of the FM demodulating device according to the second embodiment having the above-mentioned structure will be described in detail below.

FIG. 5 is a signal waveform diagram of each part in FIG. In FIG. 5, waveform a is the output signal of the first subtractor 14 in which the zero crossing point is missing, waveform d is the output signal of the second subtracter 15 in which the zero crossing point is not missing, and waveform e is T.
The output signals of the third delay circuit 21 having the delay time of 2 are shown respectively, but the operation of these circuit blocks is the same as that of the first embodiment, and the explanation thereof is omitted.

The output signal of the first subtractor 14 (waveform a in FIG. 5) is converted into a square wave by the first limiter circuit 16 and by the first mono-multi circuit 23 triggered only by the rising edge. , And the pulse width W1 becomes a negative logic pulse signal of about 35 ns (waveform b in FIG. 5). Each pulse in this waveform b corresponds to a zero-cross point in the direction from negative to positive in the output signal (waveform a) of the first subtractor 14. In addition, the same first limiter circuit 16
The output signal of the pulse width W3 is about 35 due to the third mono-multi circuit 25 triggered only by the falling edge.
It becomes a negative logic pulse signal of ns (waveform c in FIG. 5). Each pulse in the waveform c corresponds to a zero-cross point in the positive to negative direction in the output signal (waveform a) of the first subtractor 14, respectively.

On the other hand, the output signal of the third delay circuit 21 (waveform e in FIG. 5) is converted into a square wave by the second limiter circuit 17, and the second monomulti circuit is triggered only by the rising edge. 24, the pulse width W2 is about 3
It becomes a negative logic pulse signal of 5 ns (waveform f in FIG. 5).
Each pulse in the waveform f corresponds to a zero-cross point in the direction from the negative to the positive in the output signal (waveform e) of the third delay circuit 21. Further, the output signal of the same second limiter circuit 17 has a pulse width W by the fourth mono-multi circuit 26 which is triggered only by the falling edge.
4 becomes a negative logic pulse signal of about 35 ns (waveform g in FIG. 5). Each pulse in the waveform g is supplied to the third delay circuit 2
1 corresponding to the zero-cross points in the direction from positive to negative in the output signal (waveform e).

The output signal of the first mono-multi circuit 23 (waveform b in FIG. 5) and the output signal of the second mono-multi circuit 24 (waveform f in FIG. 5) are logically processed by the first AND circuit 29. The sum (negative logic) is taken to form a pulse waveform like the waveform h in FIG. 5, and the fifth monomulti circuit 27 produces a negative logic pulse signal having a pulse width of about 20 ns (waveform i in FIG. 5). ). Similarly, the output signal of the third mono-multi circuit 25 (waveform c in FIG. 5) and the fourth mono-multi circuit 2
The output signal of 6 (waveform g in FIG. 5) is ORed (negative logic) by the second AND circuit 30 to form a pulse waveform like the waveform j in FIG. The circuit 28 produces a negative logic pulse signal having a pulse width of about 20 ns (waveform k in FIG. 5). The pulse signals at the zero cross points that are missing due to the inversion phenomenon in the waveforms b and c in FIG. 5 are compensated by the pulse signals shown in the waveforms f and g in FIG. 5, respectively.

The output signal of the fifth mono-multi circuit 27 (waveform i in FIG. 5) and the output signal of the sixth mono-multi circuit 28 (waveform k in FIG. 5) are further processed by the third AND circuit 31. The logical sum (negative logic) is obtained, and as shown by the waveform 1 in FIG. 5, the frequency is twice that of the reproduced FM luminance signal.
The negative logic pulse signal has a constant amplitude and a constant pulse width (about 20 ns). As a result, from the output terminal 11, the first
The reproduction luminance signal can be obtained through the low-pass filter 10 as in the case of the above embodiment.

As described above, according to the present embodiment, the zero-cross point that has been lost due to the inversion phenomenon can be restored as in the case of the first embodiment, and a high SN ratio and high resolution can be secured. The inversion phenomenon can be suppressed. Also, the fifth
And the sixth mono-multi circuits 27 and 28 adjust the pulse widths to 20 ns, respectively, and then the third AND circuit 31 performs a logical sum to double the frequency of the reproduced FM luminance signal, so theoretically the linearity is about 25 MHz. [= 1 / (2 ×
20 ns)] can be improved.

As in the case of the first embodiment,
The output pulse widths W2 and W4 of the second and fourth mono-multi circuits 24 and 26 are the same as those of the first and third mono-multi circuits 2 respectively.
The output pulse widths W1 and W3 of 3 and 25 can be made smaller. For example, the output pulse widths W1 and W3 of the first and third mono-multi circuits 23 and 25 are both about 35 ns, and the output pulse widths W2 and W4 of the second and fourth mono-multi circuits 24 and 26 are both. Is about 15 ns. Thereby, the linearity in the high range can be further improved.

In the second embodiment, the timing circuit 42 includes the first and second AND circuits 29 and 30.
Output signals of the fifth and sixth mono-multi circuits 27,
Although it is given to the third AND circuit 31 via 28, a configuration may be adopted in which the output signals of the first and second AND circuits 29 and 30 are directly input to the third AND circuit 31. . In this case, the pulse signal having a constant pulse width (for example, 20 ns) is output by being triggered only by the falling edge of the output signal of the third AND circuit 31 (the fifth).
()) Mono-multi circuit is provided. As a result, the number of mono-multi circuits forming the timing circuit 42 is reduced by one.

[0043]

As described above, according to the first aspect of the present invention, the main path system having the frequency characteristic in which the improvement of the noise balance at the time of low luminance is the highest priority, and the loss prevention of the zero cross point is the highest priority. The sub-path system having the frequency characteristics set in parallel and the sub-path system signal are delayed for a certain time with respect to the main-path system signal, and the zero-cross point of the sub-pass system is generated only when the zero-cross point is missing in the main path system. By adopting the configuration that is replaced with, it is possible to realize an excellent FM demodulation device that is resistant to the inversion phenomenon and that can obtain a demodulation signal with a high SN ratio and high resolution.

According to the present invention, the timing circuit for compensating for the zero-cross point is composed of a mono-multi circuit and an AND circuit, whereby the replacement of the zero-cross point is achieved, and the output stage is Since the pulse signal given to the low pass filter has a constant pulse width, the linearity of the demodulated signal is improved.

According to the third and sixth aspects of the invention, since the output pulse width of the sub-path mono-multi circuit is set smaller than the output pulse width of the main-path mono-multi circuit, the high frequency range is adopted. The linearity in can be further improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an FM demodulation device according to a first embodiment of the present invention.

FIG. 2 is a signal waveform diagram of each part in FIG.

[Fig. 3] Fig. 1 set with emphasis on high SN ratio and high resolution.
It is a figure which shows the frequency characteristic of the 1st subtractor in the inside.

FIG. 4 is a block diagram showing a configuration of an FM demodulation device according to a second embodiment of the present invention.

5 is a signal waveform diagram of each part in FIG.

FIG. 6 is a block diagram showing an example of the configuration of a conventional FM demodulation device for a VTR.

FIG. 7 is a diagram showing frequency characteristics of a reproduced FM luminance signal output from a VTR head.

FIG. 8 is a diagram showing frequency characteristics of the equalizer in FIG. 6 which is set so as not to cause loss of zero-cross points.

[Explanation of symbols]

1 Input Terminal 2 First Delay Circuit 3 Second Delay Circuit 4 Adder 7 Equalizer 10 Low Pass Filter 11 Output Terminal 12 First Variable Amplifier Circuit 13 Second Variable Amplifier Circuit 14 First Subtractor 15 Second Subtractor 16 First limiter circuit 17 Second limiter circuit 18 First mono-multi circuit (first monostable multivibrator circuit) 19 Second mono-multi circuit (second monostable multivibrator circuit) 20th 3 mono-multi circuit (third monostable multivibrator circuit) 21 3rd delay circuit 22 AND circuit 23 1st monomulti circuit (first monostable multivibrator circuit) 24 2nd monomulti circuit (first 2 monostable multivibrator circuit) 25 third monostable multicircuit (third monostable multivibrator circuit) 26 4th monostable multivibrator circuit Circuit (4th monostable multivibrator circuit) 27 5th monostable circuit (5th monostable multivibrator circuit) 28 6th monostable circuit (6th monostable multivibrator circuit) 29 1st AND Circuit 30 Second AND circuit 31 Third AND circuit 41 Timing circuit 42 Timing circuit

Claims (6)

[Claims] 1. A reproducing F from a head of a magnetic recording / reproducing apparatus.
An equalizer for adjusting the frequency characteristic and the phase characteristic of the M luminance signal; a first delay circuit to which an output signal of the equalizer is input; and a first delay circuit having the same delay time as the first delay circuit and having the first delay circuit.
Second delay circuit to which the output signal of the delay circuit is input, an adder for adding the input signal of the first delay circuit and the output signal of the second delay circuit, and the adder, respectively. And a second variable amplification circuit for amplifying the output signal of the first delay circuit, and noise at low luminance for subtracting the output signal of the first delay circuit from the output signal of the first variable amplification circuit The first frequency characteristic is set so that the balance is improved.
And a second subtracter for setting the frequency characteristic so that the output of the first variable delay circuit is subtracted from the output signal of the second variable amplifier circuit so that the output does not lack a zero-cross point. Subtractor, a first limiter circuit for converting the output signal of the first subtractor into a square wave, a third delay circuit to which the output signal of the second subtractor is input, and the third Second, which converts the output signal of the delay circuit of to a square wave
And a timing based on both rising and falling edges of the output signal of the first limiter circuit and both rising and falling edges of the output signal of the second limiter circuit, and A timing circuit for outputting a pulse signal so as to compensate a missing zero-cross point in the output signal of the subtractor at the zero-cross point in the output signal of the second subtractor; and a reproduction luminance signal for the output signal of the timing circuit. An FM demodulation device comprising: a low-pass filter for converting into 2. The FM demodulator according to claim 1, wherein the timing circuit is a negative logic pulse signal having a constant pulse width W1 triggered by both rising and falling edges of the output signal of the first limiter circuit. And a second monostable multivibrator circuit for outputting a negative logic pulse signal having a constant pulse width W2 triggered by both rising and falling edges of the output signal of the second limiter circuit. A stable multivibrator circuit, an AND circuit to which the output signals of the first and second monostable multivibrator circuits are input, and a pulse having a constant pulse width that is triggered only by the falling edge of the output signal of the AND circuit An FM demodulation device comprising a third monostable multivibrator circuit for outputting a signal. 3. The FM demodulator according to claim 2, wherein the output pulse width W2 of the second monostable multivibrator circuit is set smaller than the output pulse width W1 of the first monostable multivibrator circuit. An FM demodulation device characterized by the above. 4. The FM demodulator according to claim 1, wherein the timing circuit is triggered only by a rising edge of an output signal of the first limiter circuit to output a negative logic pulse signal having a constant pulse width W1. A monostable multivibrator circuit, a second monostable multivibrator circuit that is triggered only by a rising edge of an output signal of the second limiter circuit, and outputs a negative logic pulse signal having a constant pulse width W2; A third monostable multivibrator circuit that outputs a negative logic pulse signal having a constant pulse width W3 by being triggered only by the falling edge of the output signal of the first limiter circuit, and the falling edge of the output signal of the second limiter circuit. Fourth monostable multivibrator which is triggered only by edges and outputs a negative logic pulse signal with a constant pulse width W4 A first AND circuit to which the output signals of the first and second monostable multivibrator circuits are input, and the output signals of the third and fourth monostable multivibrator circuits. A second AND circuit; a fifth monostable multivibrator circuit for outputting a negative logic pulse signal having a constant pulse width by being triggered only by the falling edge of the output signal of the first AND circuit; A sixth signal which is triggered only by the falling edge of the output signal of the second AND circuit and outputs a negative logic pulse signal having the same pulse width as that of the fifth monostable multivibrator circuit.
And a third AND circuit to which the output signals of the fifth and sixth monostable multivibrator circuits are input, respectively. 5. The FM demodulator according to claim 1, wherein the timing circuit is triggered only by a rising edge of an output signal of the first limiter circuit to output a negative logic pulse signal having a constant pulse width W1. A monostable multivibrator circuit, a second monostable multivibrator circuit that is triggered only by a rising edge of an output signal of the second limiter circuit, and outputs a negative logic pulse signal having a constant pulse width W2; A third monostable multivibrator circuit that outputs a negative logic pulse signal having a constant pulse width W3 by being triggered only by the falling edge of the output signal of the first limiter circuit, and the falling edge of the output signal of the second limiter circuit. Fourth monostable multivibrator which is triggered only by edges and outputs a negative logic pulse signal with a constant pulse width W4 A first AND circuit to which the output signals of the first and second monostable multivibrator circuits are input, and the output signals of the third and fourth monostable multivibrator circuits. A second AND circuit, a third AND circuit to which the output signals of the first and second AND circuits are input, and a third AND circuit triggered by only the falling edge of the output signal of the third AND circuit. An FM demodulation device, comprising: a fifth monostable multivibrator circuit that outputs a pulse signal having a constant pulse width. 6. The FM demodulator according to claim 4, wherein an output pulse width W2 of the second monostable multivibrator circuit is set smaller than an output pulse width W1 of the first monostable multivibrator circuit. And the output pulse width W4 of the fourth monostable multivibrator circuit is equal to the output pulse width W of the third monostable multivibrator circuit.
An FM demodulation device characterized by being set smaller than 3.