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JPH06152285A - Agc circuit - Google Patents

Agc circuit

Info

Publication number
JPH06152285A
JPH06152285A JP29755692A JP29755692A JPH06152285A JP H06152285 A JPH06152285 A JP H06152285A JP 29755692 A JP29755692 A JP 29755692A JP 29755692 A JP29755692 A JP 29755692A JP H06152285 A JPH06152285 A JP H06152285A
Authority
JP
Japan
Prior art keywords
circuit
signal
converter
detection
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP29755692A
Other languages
Japanese (ja)
Other versions
JP3036263B2 (en
Inventor
Takayuki Shibata
隆行 柴田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP29755692A priority Critical patent/JP3036263B2/en
Publication of JPH06152285A publication Critical patent/JPH06152285A/en
Application granted granted Critical
Publication of JP3036263B2 publication Critical patent/JP3036263B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
  • Control Of Amplification And Gain Control (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE:To make the device compact without requiring complicated control circuits by inputting amplitudes I, Q from a waveform shaping circuit and a digital signal from A/D converter and generating an AGC signals on the calculation by a signal processing circuit. CONSTITUTION:The detection voltage detected by a detection circuit 6 is A/D converted 8 at every specific timing by a timing signal 12 from a waveform shaping circuit 2 and outputted to a signal processing circuit 1. The circuit 1 is provided with a memory function, storing the detection characteristic of the circuit 6 and discriminating the detection level based on the output of a converter 8. The signal processing circuit 1 generates and outputs an AGC signal 11 by calculation to let the detection level judged by the output of the converter 8 approach the output level calculated from amplitudes (i) and (q) of an orthogonal basement signal. The signal 11 is D/A converted by a D/A converter 7 the specific timing by the timing signal 12. By generating the AGC voltage to control the gain of the RF amplifier circuit 5, the output of it is kept constant.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はAGC回路に関し、特に
ディジタル変調されたRF信号の増幅回路に使用される
AGC回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an AGC circuit, and more particularly to an AGC circuit used as an amplifier circuit for a digitally modulated RF signal.

【0002】[0002]

【従来の技術】従来のAGC回路は図2に示すように、
入力信号を所定のフォーマットに変換して変調信号を生
成する信号処理回路1と、変調信号を直交ベースバンド
信号I,Qに変換する波形整形回路2と、直交ベースバ
ンド信号I,QをD/A変換するD/A変換機3と、そ
の出力を直交変調する直交変調回路4と、その出力を増
幅するRF増幅回路5と、RF増幅回路5の入力を検波
する第1の検波回路9と、検波回路9の検波電圧を増幅
する増幅器10と、増幅器10の出力を特定のタイミン
グでサンプルホールドする第1のサンプルホールド回路
11と、RF増幅回路5の出力を検波する第2の検波回
路6と、検波回路6の検波電圧を特定のタイミングでサ
ンプルホールドする第2のサンプルホールド回路13
と、サンプルホールド回路11の出力電圧とサンプルホ
ールド回路13の出力電圧を比較してRF増幅回路5に
AGC電圧を与える比較器12で構成されている。この
従来のAGC回路は、特定のタイミングにおいて、サン
プリングされるRF増幅回路5の入力信号検波電圧の増
幅器10による増幅電圧と、RF増幅回路5の出力信号
検波電圧とを等しくするように動作させていた。
2. Description of the Related Art A conventional AGC circuit, as shown in FIG.
A signal processing circuit 1 for converting an input signal into a predetermined format to generate a modulated signal, a waveform shaping circuit 2 for converting the modulated signal into quadrature baseband signals I and Q, and a D / r quadrature baseband signal I / Q. A D / A converter 3 for A conversion, a quadrature modulation circuit 4 for quadrature modulation of its output, an RF amplification circuit 5 for amplifying its output, and a first detection circuit 9 for detecting the input of the RF amplification circuit 5. An amplifier 10 that amplifies the detection voltage of the detection circuit 9, a first sample hold circuit 11 that samples and holds the output of the amplifier 10 at a specific timing, and a second detection circuit 6 that detects the output of the RF amplification circuit 5. And a second sample-hold circuit 13 that samples and holds the detection voltage of the detection circuit 6 at a specific timing.
And a comparator 12 that compares the output voltage of the sample hold circuit 11 with the output voltage of the sample hold circuit 13 and applies an AGC voltage to the RF amplifier circuit 5. This conventional AGC circuit operates so that the amplified voltage of the input signal detection voltage of the RF amplification circuit 5 to be sampled by the amplifier 10 and the output signal detection voltage of the RF amplification circuit 5 become equal at a specific timing. It was

【0003】[0003]

【発明が解決しようとする課題】この従来のAGC回路
では、RF増幅回路5の制御を正しく行うためには、シ
ンボルタイミングでの振幅変動範囲において、第1の検
波回路9および増幅器10の総合検波特性と、第2の検
波回路6の検波特性が等しくならなければならないが、
実際には第1の検波回路9と第2の検波回路6の検波特
性が異なるので、増幅器10の利得制御のために複雑な
回路が必要になる。さらに、温度等環境の変化によって
増幅器10、第1の検波回路9および増幅器10の総合
検波特性と第2の検波回路6の検波特性が異ってしま
い、AGCが正しくかからないという欠点があった。
In this conventional AGC circuit, in order to properly control the RF amplifier circuit 5, the total detection of the first detection circuit 9 and the amplifier 10 is performed in the amplitude variation range at the symbol timing. The characteristic and the detection characteristic of the second detection circuit 6 must be equal,
Actually, since the detection characteristics of the first detection circuit 9 and the second detection circuit 6 are different, a complicated circuit is required for controlling the gain of the amplifier 10. Further, there is a drawback that the AGC cannot be applied correctly because the total detection characteristics of the amplifier 10, the first detection circuit 9 and the amplifier 10 and the detection characteristics of the second detection circuit 6 differ due to changes in environment such as temperature.

【0004】本発明の目的は、特定のシンボルタイミン
グにおける振幅が一定値にならない信号の増幅回路の制
御を簡単な回路構成で行えるAGC回路を提供すること
にある。
An object of the present invention is to provide an AGC circuit which can control an amplifier circuit for a signal whose amplitude at a specific symbol timing does not become a constant value with a simple circuit configuration.

【0005】[0005]

【課題を解決するための手段】本発明のAGC回路は入
力信号を信号処理回路により所定のフォーマットに変換
して変調信号を生成する信号処理回路と、前記変調信号
から波形整形回路により直交ベースバンド信号I,Qの
振幅値を出力する波形整形回路と、前記ベースバンド信
号I,QをD/A変換する第1のD/A変換器と、前記
第1のD/A変換器の出力を直交変調する直交変調回路
と、前記直交変調回路の出力を増幅するRF増幅回路
と、前記RF増幅回路の出力信号レベルを検波する検波
回路と、前記検波回路の出力電圧を特定のタイミング信
号でA/D変換するA/D変換器と、前記信号処理回路
が直交ベースバンド信号I,Qの振幅値及び前記A/D
変換器の出力を入力し、演算処理によって得られたAG
C信号を第2のD/A変換器を経由して前記RF増幅回
路に帰還することを特徴とする。
The AGC circuit of the present invention is a signal processing circuit for converting an input signal into a predetermined format by a signal processing circuit to generate a modulated signal, and a quadrature baseband circuit from the modulated signal by a waveform shaping circuit. A waveform shaping circuit for outputting the amplitude values of the signals I, Q; a first D / A converter for D / A converting the baseband signals I, Q; and an output of the first D / A converter. A quadrature modulation circuit for quadrature modulation, an RF amplification circuit for amplifying the output of the quadrature modulation circuit, a detection circuit for detecting the output signal level of the RF amplification circuit, and an output voltage of the detection circuit with a specific timing signal A A / D converter for A / D conversion, the signal processing circuit includes amplitude values of the quadrature baseband signals I and Q, and the A / D converter.
The output of the converter is input and the AG obtained by arithmetic processing
The C signal is fed back to the RF amplifier circuit via the second D / A converter.

【0006】[0006]

【実施例】次に本発明について図面を参照して説明す
る。図1は本発明の一実施例を示すブロック図である。
図1の実施例は、信号処理回路1、波形整形回路2、第
1のD/A変換器3、直交変調回路4、RF増幅回路
5、検波回路6、第2のD/A変換器7、A/D変換器
8で構成されている。ここでD/A変換器3、直交変調
回路4、RF増幅回路5、検波回路6は従来例の構成と
同様である。波形整形回路2は特定のタイミングにおけ
る直交ベースバンド信号I,Qの振幅値i,qを信号処
理回路1に供給する。信号処理回路1は演算機能を有
し、i,qから出力レベルを算出することができる。ま
た、検波回路6によって検波された検波電圧は波形整形
回路2からのタイミング信号12により特定のタイミン
グごとにA/D変換器8によってA/D変換され、信号
処理回路1に出力される。信号処理回路1はメモリ機能
を有し、検波回路6の検波特性を記憶しており、A/D
変換器8の出力から検波レベルを判別する。信号処理回
路1はA/D変換器8の出力から判定される検波レベル
を、i,qから算出した出力レベルに近づけるような制
御を行うためのAGC信号11を計算によって生成して
出力する。AGC信号11は第2のD/A変換器7でタ
イミング信号12による特定のタイミングでD/A変換
され、RF増幅回路5の利得を制御するAGC電圧12
を生成してRF増幅回路5の出力を一定になるように制
御する。
The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.
In the embodiment of FIG. 1, the signal processing circuit 1, the waveform shaping circuit 2, the first D / A converter 3, the quadrature modulation circuit 4, the RF amplification circuit 5, the detection circuit 6, and the second D / A converter 7 are provided. , A / D converter 8. Here, the D / A converter 3, the quadrature modulation circuit 4, the RF amplification circuit 5, and the detection circuit 6 have the same configurations as those of the conventional example. The waveform shaping circuit 2 supplies the amplitude values i and q of the orthogonal baseband signals I and Q at a specific timing to the signal processing circuit 1. The signal processing circuit 1 has an arithmetic function and can calculate the output level from i and q. Further, the detection voltage detected by the detection circuit 6 is A / D converted by the A / D converter 8 at a specific timing by the timing signal 12 from the waveform shaping circuit 2 and output to the signal processing circuit 1. The signal processing circuit 1 has a memory function and stores the detection characteristics of the detection circuit 6,
The detection level is discriminated from the output of the converter 8. The signal processing circuit 1 calculates and generates an AGC signal 11 for performing control so that the detection level determined from the output of the A / D converter 8 approaches the output level calculated from i and q, and outputs it. The AGC signal 11 is D / A-converted by the second D / A converter 7 at a specific timing by the timing signal 12, and the AGC voltage 12 that controls the gain of the RF amplifier circuit 5.
Is generated to control the output of the RF amplification circuit 5 to be constant.

【0007】[0007]

【発明の効果】以上説明したように本発明のAGC回路
は、信号処理回路が波形整形回路からI,Qの振幅とA
/D変換器8からのディジタル信号を入力して計算によ
ってAGC信号を生成しているので、従来例のようにふ
たつの異なる検波回路の出力を調整するための複雑な制
御回路を必要とせず、しかも素子数削減により小型化が
可能であるという効果を有する。
As described above, in the AGC circuit of the present invention, the signal processing circuit operates from the waveform shaping circuit to the amplitudes of I, Q and A.
Since the digital signal from the / D converter 8 is input to generate the AGC signal by calculation, a complicated control circuit for adjusting the outputs of two different detection circuits as in the conventional example is not required, Moreover, there is an effect that the size can be reduced by reducing the number of elements.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例のブロック図である。FIG. 1 is a block diagram of an embodiment of the present invention.

【図2】従来のAGC回路のブロック図である。FIG. 2 is a block diagram of a conventional AGC circuit.

【符号の説明】[Explanation of symbols]

1 信号処理回路 2 波形整形回路 3,7 D/A変換器 4 直交変調回路 5 RF増幅回路 6,9 検波回路 8 A/D変換器 10 増幅器 11,13 サンプルホールド回路 12 比較器 1 signal processing circuit 2 waveform shaping circuit 3, 7 D / A converter 4 quadrature modulation circuit 5 RF amplification circuit 6, 9 detection circuit 8 A / D converter 10 amplifier 11, 13 sample hold circuit 12 comparator

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 入力信号を信号処理回路により所定のフ
ォーマットに変換して変調信号を生成する信号処理回路
と、前記変調信号から波形整形回路により直交ベースバ
ンド信号I,Qの振幅値を出力する波形整形回路と、前
記ベースバンド信号I,QをD/A変換する第1のD/
A変換器と、前記第1のD/A変換器の出力を直交変調
する直交変調回路と、前記直交変調回路の出力を増幅す
るRF増幅回路と、前記RF増幅回路の出力信号レベル
を検波する検波回路と、前記検波回路の出力電圧を特定
のタイミング信号でA/D変換するA/D変換器と、前
記信号処理回路が直交ベースバンド信号I,Qの振幅値
及び前記A/D変換器の出力を入力し、演算処理によっ
て得られたAGC信号を第2のD/A変換器を経由して
前記RF増幅回路に帰還することを特徴とするAGC回
路。
1. A signal processing circuit for converting an input signal into a predetermined format by a signal processing circuit to generate a modulated signal, and a waveform shaping circuit for outputting amplitude values of quadrature baseband signals I and Q from the modulated signal. A waveform shaping circuit and a first D / A converter for D / A converting the baseband signals I and Q.
An A converter, a quadrature modulation circuit that quadrature modulates the output of the first D / A converter, an RF amplification circuit that amplifies the output of the quadrature modulation circuit, and an output signal level of the RF amplification circuit is detected. A detection circuit, an A / D converter for A / D converting an output voltage of the detection circuit with a specific timing signal, and an amplitude value of the quadrature baseband signals I and Q by the signal processing circuit and the A / D converter. The AGC circuit which inputs the output of the above, and feeds back the AGC signal obtained by the arithmetic processing to the RF amplifier circuit via the second D / A converter.
【請求項2】 前記信号処理回路が前記検波回路の検波
特性を記憶する機能を備えていることを特徴とする請求
項1記載のAGC回路。
2. The AGC circuit according to claim 1, wherein the signal processing circuit has a function of storing a detection characteristic of the detection circuit.
JP29755692A 1992-11-09 1992-11-09 AGC circuit Expired - Fee Related JP3036263B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29755692A JP3036263B2 (en) 1992-11-09 1992-11-09 AGC circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29755692A JP3036263B2 (en) 1992-11-09 1992-11-09 AGC circuit

Publications (2)

Publication Number Publication Date
JPH06152285A true JPH06152285A (en) 1994-05-31
JP3036263B2 JP3036263B2 (en) 2000-04-24

Family

ID=17848082

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29755692A Expired - Fee Related JP3036263B2 (en) 1992-11-09 1992-11-09 AGC circuit

Country Status (1)

Country Link
JP (1) JP3036263B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7196658B2 (en) * 2002-08-26 2007-03-27 Mitsubishi Denki Kabushiki Kaisha Waveform generation method, waveform generation program, waveform generation circuit and radar device
US7277689B2 (en) 2001-07-05 2007-10-02 Infineon Technologies Ag Transmission arrangement with power regulation

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7277689B2 (en) 2001-07-05 2007-10-02 Infineon Technologies Ag Transmission arrangement with power regulation
US7196658B2 (en) * 2002-08-26 2007-03-27 Mitsubishi Denki Kabushiki Kaisha Waveform generation method, waveform generation program, waveform generation circuit and radar device
EP1928093A1 (en) * 2002-08-26 2008-06-04 Mitsubishi Denki K.K. Waveform generation method, waveform generation program, waveform generation circuit and radar apparatus

Also Published As

Publication number Publication date
JP3036263B2 (en) 2000-04-24

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