JPH06151846A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH06151846A JPH06151846A JP31936692A JP31936692A JPH06151846A JP H06151846 A JPH06151846 A JP H06151846A JP 31936692 A JP31936692 A JP 31936692A JP 31936692 A JP31936692 A JP 31936692A JP H06151846 A JPH06151846 A JP H06151846A
- Authority
- JP
- Japan
- Prior art keywords
- groove
- layer
- electrode
- substrate
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 52
- 239000012535 impurity Substances 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 239000004020 conductor Substances 0.000 claims abstract description 36
- 238000000034 method Methods 0.000 abstract description 10
- 229910052751 metal Inorganic materials 0.000 abstract description 7
- 239000002184 metal Substances 0.000 abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 6
- 229910021332 silicide Inorganic materials 0.000 abstract description 5
- 239000000126 substance Substances 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 230000008018 melting Effects 0.000 abstract description 4
- 238000002844 melting Methods 0.000 abstract description 4
- 238000010438 heat treatment Methods 0.000 abstract description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract description 2
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 79
- 238000009792 diffusion process Methods 0.000 description 16
- 239000003870 refractory metal Substances 0.000 description 8
- 230000002457 bidirectional effect Effects 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 4
- 229910000838 Al alloy Inorganic materials 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000000605 extraction Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- 239000013543 active substance Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、高周波用半導体装置等
に関するもので、特にチップ表面に形成された電極を、
基板内部を通りチップ裏面に取り出す例えば横型MOS
FETのソース電極取り出し等の構造に係るものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high frequency semiconductor device and the like, and particularly to an electrode formed on a chip surface,
Taken out to the back surface of the chip through the inside of the substrate, for example, lateral MOS
The present invention relates to the structure of taking out the source electrode of the FET.
【0002】[0002]
【従来の技術】高周波用半導体装置(急峻な波形変化の
デジタル信号用デバイスを含む)のうち、例えば横型M
OSFETのように、チップの裏面を接地電位にとるこ
とのできる半導体装置では、半導体チップの組み込まれ
る外囲器の接地電極面に直接取り付けることができる。
前記横型MOSFETは、通常ソース電極を接地電位に
して使用することが多いが、ソース電極はチップ表面に
形成されているため、ソース電極を裏面側と電気的に接
続する必要がある。2. Description of the Related Art Among high frequency semiconductor devices (including devices for digital signals with sharp waveform changes), for example, a horizontal type M
In the case of a semiconductor device such as the OSFET capable of having the back surface of the chip at the ground potential, it can be directly attached to the ground electrode surface of the envelope in which the semiconductor chip is incorporated.
In the lateral MOSFET, the source electrode is usually used with the ground potential in many cases, but since the source electrode is formed on the surface of the chip, it is necessary to electrically connect the source electrode to the back surface side.
【0003】この接続を金属細線を用いて行なうと、細
線部分に高いインダクタンスを生じるため、MOSFE
Tの高周波特性が低下する。If this connection is made by using a thin metal wire, a high inductance is generated in the thin wire portion, so that the MOSFE is used.
The high frequency characteristics of T deteriorate.
【0004】そこで、金属細線を使わずに接続する方法
として、図6に示すような構造のMOSFETが用いら
れている。同図において、横型MOSFETは、P+ 半
導体基板1上のP- 層2及びその上に形成される。ゲー
ト電極8は、ゲート酸化膜4を介してP- 層2の表面層
のチャネル領域2aと対向している。チャネル領域2a
を挟んでN+ ドレイン領域9及びN+ ソース領域7が形
成され、両領域にそれぞれオーム接触するドレイン電極
10及びソース電極11が設けられる。符号5は層間絶
縁膜である。P+ 基板1の下面(図面上)は図示してな
いが例えば接地電位の外囲器に取り付けられる。Therefore, a MOSFET having a structure as shown in FIG. 6 is used as a method of connecting without using a thin metal wire. In the figure, the lateral MOSFET is formed on the P − layer 2 on the P + semiconductor substrate 1 and on it. Gate electrode 8 is opposed to channel region 2a of the surface layer of P − layer 2 with gate oxide film 4 in between. Channel region 2a
An N + drain region 9 and an N + source region 7 are formed with the drain electrode 10 and the source electrode 11 in ohmic contact with each other. Reference numeral 5 is an interlayer insulating film. Although not shown, the lower surface (on the drawing) of the P + substrate 1 is attached to, for example, an envelope of ground potential.
【0005】このMOSFETでは、ソース電極11を
接地電位に接続する方法として、基板表面からイオン注
入法や不純物拡散源からの熱拡散によってP+ 拡散層3
を形成し、拡散層3の表面は、ソース電極11の延在部
分と接続し、拡散層3の下部は、P+ 基板1に達するよ
うにし、ソース電極11をチップ裏面に取り出してい
る。In this MOSFET, as a method of connecting the source electrode 11 to the ground potential, the P + diffusion layer 3 is formed by ion implantation from the substrate surface or thermal diffusion from an impurity diffusion source.
The surface of the diffusion layer 3 is connected to the extended portion of the source electrode 11, the lower part of the diffusion layer 3 reaches the P + substrate 1, and the source electrode 11 is taken out to the back surface of the chip.
【0006】チップ表面の電極を上記不純物拡散層を用
いてチップ裏面に取り出す方法は、インダクタンスは減
少するけれど、高濃度拡散層の抵抗は、金属細線の抵抗
に比し大きく、やはり高周波特性を十分に引き出せなく
なる。In the method of extracting the electrode on the surface of the chip to the back surface of the chip by using the impurity diffusion layer, the inductance is reduced, but the resistance of the high concentration diffusion layer is larger than the resistance of the thin metal wire, and the high frequency characteristic is still sufficient. Can't be pulled out to.
【0007】この方法で抵抗分を減らすためには、不純
物拡散領域として広い面積を取る必要がある。特に大電
力用のMOSFETでは、ドレイン・ソース間の耐圧を
高くするため、半導体基板上の低不純物濃度層を厚くし
なければならない。一般に不純物の熱拡散では、基板の
厚さ方向への拡散と共に横方向へも拡散するので、低不
純物濃度層が厚くなれば、さらに広い面積を要すること
となり、チップ面積が増大し、素子の集積化に対して不
利となる。In order to reduce the resistance component by this method, it is necessary to take a large area as the impurity diffusion region. Particularly in a high power MOSFET, the low impurity concentration layer on the semiconductor substrate must be thickened in order to increase the drain-source breakdown voltage. In general, thermal diffusion of impurities diffuses not only in the thickness direction of the substrate but also in the lateral direction. Therefore, if the low-impurity concentration layer becomes thicker, a larger area will be required, increasing the chip area and increasing the device integration. Will be disadvantageous to the conversion.
【0008】[0008]
【発明が解決しようとする課題】一般に矩形波のパルス
信号を取り扱う半導体装置を含め、高周波用半導体装置
では、電極を外部に取り出すリード線等の導電性物体の
抵抗及びインダクタンスは、高周波特性を劣化させるの
で、できるだけ小さくすることが必要である。Generally, in a high-frequency semiconductor device including a semiconductor device that handles a rectangular wave pulse signal, the resistance and inductance of a conductive object such as a lead wire for extracting an electrode deteriorates high-frequency characteristics. Therefore, it is necessary to make it as small as possible.
【0009】これまで述べたように、チップ表面に形成
されている電極を、チップ内部を通り裏面の高濃度層
(または基板)に取り出す従来の方法は、不純物拡散層
により、表面電極と裏面高濃度領域とを接続するもので
ある。この方法では、電極取りだし用の導電体のインダ
クタンスは減少するが、抵抗分が増加する。抵抗分を減
らすためには、電極取りだしのための拡散層の面積を大
きくする必要があり、チップ面積が増大する。As described above, the conventional method of extracting the electrode formed on the front surface of the chip to the high concentration layer (or substrate) on the back surface through the inside of the chip is to use the impurity diffusion layer to increase the height of the front surface electrode and the back surface. It connects the concentration area. In this method, the inductance of the conductor for taking out the electrode is reduced, but the resistance is increased. In order to reduce the resistance component, it is necessary to increase the area of the diffusion layer for taking out the electrodes, which increases the chip area.
【0010】本発明は、高周波用半導体装置において、
チップ表面に形成された電極を、チップ裏面に取り出す
ための導電体の抵抗及びインダクタンスの増加をできる
だけ抑え、素子本来の高周波特性の劣化や、チップ面積
の増加が少ない電極取りだし用導電体を具備する半導体
装置を提供することを目的とする。The present invention relates to a high frequency semiconductor device,
Equipped with a conductor for electrode extraction that suppresses the increase in resistance and inductance of the conductor for taking out the electrode formed on the surface of the chip on the back surface of the chip as much as possible, and does not deteriorate the high frequency characteristics inherent to the element or increase the chip area. An object is to provide a semiconductor device.
【0011】[0011]
【課題を解決するための手段】本発明の請求項1に係る
半導体装置は、高不純物濃度の半導体基板と、この基板
上に形成された低不純物濃度の半導体層と、この半導体
層上に絶縁膜を介しまたは直接形成される電極と、前記
絶縁膜または前記半導体層の表面から前記半導体層を通
り前記半導体基板に達する幅よりも深さの大きい溝と、
この溝の側壁及び底面に形成され若しくは溝を埋め込ん
で形成され、かつ前記電極と前記高不純物濃度の半導体
基板とを電気接続する導電性物質層とを、具備すること
を特徴とする半導体装置である。According to a first aspect of the present invention, there is provided a semiconductor device having a high impurity concentration semiconductor substrate, a low impurity concentration semiconductor layer formed on the substrate, and an insulating layer on the semiconductor layer. An electrode formed through a film or directly, and a groove having a depth larger than the width reaching the semiconductor substrate through the semiconductor layer from the surface of the insulating film or the semiconductor layer,
A semiconductor device comprising: a conductive material layer which is formed on a side wall and a bottom surface of the groove or is embedded in the groove and electrically connects the electrode and the semiconductor substrate having a high impurity concentration. is there.
【0012】また本発明の請求項2に係る半導体装置
は、前記低不純物濃度の半導体層が、溝の内面から拡散
形成された高不純物濃度層を有することを特徴とする請
求項1記載の半導体装置である。A semiconductor device according to a second aspect of the present invention is characterized in that the semiconductor layer having a low impurity concentration has a high impurity concentration layer diffused from the inner surface of the groove. It is a device.
【0013】なお上記高不純物濃度及び低不純物濃度の
それぞれの代表値は約1018 atoms/cm3 程度及び約1014
atoms/cm3 程度である。また上記導電性物質層として
は、Al,Al合金或いはMo,W,Ti,Ta等の高
融点金属及びこれら高融点金属のシリサイドが含まれ、
また高不純物濃度の多結晶シリコンも使用できる。The typical values of the high impurity concentration and the low impurity concentration are about 10 18 atoms / cm 3 and about 10 14 respectively.
It is about atoms / cm 3 . Further, the conductive material layer includes refractory metals such as Al, Al alloys, Mo, W, Ti and Ta, and silicides of these refractory metals,
Also, polycrystalline silicon having a high impurity concentration can be used.
【0014】[0014]
【作用】請求項1に係る半導体装置においては、低不純
物濃度層上に絶縁膜を介しまたは直接形成された電極
を、高不純物濃度の基板裏面に取り出すのに、絶縁膜ま
たは低不純物濃度層の表面から低不純物濃度層を通り、
高不純物濃度の基板に達する幅よりも深さの大きい(す
なわちアスペクト比(深さ/幅)> 1)溝を、ドライエ
ッチング法等により掘り、溝の側壁及び底面に低抵抗の
導電性物質層を被着するか或いは溝内を低抵抗導電性物
質で埋め込むことにより、前記表面電極を基板裏面に取
り出している。In the semiconductor device according to the first aspect of the present invention, the electrode formed on the low impurity concentration layer via the insulating film or directly is taken out of the insulating film or the low impurity concentration layer for taking out to the back surface of the substrate having the high impurity concentration. From the surface through the low impurity concentration layer,
A groove having a depth larger than that reaching a substrate with a high impurity concentration (that is, an aspect ratio (depth / width)> 1) is dug by a dry etching method or the like, and a low resistance conductive material layer is formed on the side wall and bottom surface of the groove. Is deposited or the inside of the groove is filled with a low resistance conductive material to take out the front surface electrode to the back surface of the substrate.
【0015】このため電極取り出しのための導電性物質
層の長さは、低不純物濃度層の厚さ程度できわめて短
く、また導電性物質としては低抵抗の金属等を使用して
いるので、前記基板表面の電極を、抵抗及びインダクタ
ンスを低く抑えた状態で、基板裏面に取り出すことが可
能である。また溝のアスペクト比を 1以上に制限するこ
とにより、従来の不純物拡散層による方法に比し、電極
取り出しのための所要チップ面積を大幅に減少すること
ができる。For this reason, the length of the conductive material layer for taking out the electrode is extremely short, which is about the thickness of the low impurity concentration layer, and a low resistance metal or the like is used as the conductive material. It is possible to take out the electrode on the front surface of the substrate to the back surface of the substrate while suppressing the resistance and the inductance to be low. Further, by limiting the aspect ratio of the groove to 1 or more, the chip area required for electrode extraction can be significantly reduced as compared with the conventional method using an impurity diffusion layer.
【0016】請求項2に係る半導体装置は、請求項1記
載の作用に加えて、溝の側壁及び底面から不純物を拡散
して、溝の周囲に高不純物濃度層を形成し、さらに電極
取りだし用導電体の抵抗を減少させたものである。特に
溝内に形成される導電性物質層が、不純物拡散源として
使用できる場合には有効である。In the semiconductor device according to a second aspect of the present invention, in addition to the action of the first aspect, impurities are diffused from the side wall and the bottom surface of the groove to form a high impurity concentration layer around the groove, and further for electrode extraction. The resistance of the conductor is reduced. In particular, it is effective when the conductive material layer formed in the groove can be used as an impurity diffusion source.
【0017】[0017]
【実施例】本発明を実施例により、さらに詳細に説明す
る。EXAMPLES The present invention will be described in more detail by way of examples.
【0018】図1は本発明の半導体装置の第1実施例の
横型MOSFETの断面図である。このMOSFET
は、高不純物濃度(ボロン、約1018 atoms/cm3 )のP
+ 半導体基板21と、P+ 基板21上にエピタキシャル
成長により形成された低不純物濃度(ボロン、約1014 a
toms/cm3 )のP- 半導体層22と、ゲート酸化膜24
及び層間絶縁膜25より成る絶縁膜上に形成されるソー
ス電極31と、この絶縁膜の表面からP- 層22を通り
P+ 基板21に達する、幅よりも深さの大きい溝32
と、この溝32を埋め込み、かつ前記ソース電極31と
P+ 基板21とを電気接続するMo 埋め込み層(導電性
物質層)33とを具備することを特徴としている。 上
記MOSFETの、主な構成部分は公知の方法により形
成される。すなわちP- 層22の表面に熱酸化によりゲ
ート酸化膜24を形成、次に高融点金属或いは高融点金
属シリサイド等を用いてゲート電極28を形成する。ゲ
ート電極28をマスクにして、不純物を拡散し、N+ ソ
ース領域27及びN+ ドレイン領域29を形成する。次
に層間絶縁膜25を堆積し、ソース領域27及びドレイ
ン領域29上にコンタクトホ―ルを開口し、次に蒸着ま
たはスパッタリングにより基板上に被着したAl 合金膜
をパターニングして、ドレイン電極30及びソース電極
31を形成する。FIG. 1 is a sectional view of a lateral MOSFET according to a first embodiment of a semiconductor device of the present invention. This MOSFET
Is P with a high impurity concentration (boron, about 10 18 atoms / cm 3 ).
+ Semiconductor substrate 21 and a low impurity concentration (boron, about 10 14 a) formed by epitaxial growth on the P + substrate 21.
toms / cm 3 ) of P − semiconductor layer 22 and gate oxide film 24
And the source electrode 31 formed on the insulating film including the interlayer insulating film 25, and the groove 32 having a depth larger than the width and reaching the P + substrate 21 from the surface of the insulating film through the P − layer 22.
And a Mo embedded layer (conductive material layer) 33 that fills the groove 32 and electrically connects the source electrode 31 and the P + substrate 21. The main constituent parts of the MOSFET are formed by a known method. That is, a gate oxide film 24 is formed on the surface of the P − layer 22 by thermal oxidation, and then a gate electrode 28 is formed using a refractory metal or refractory metal silicide. Impurities are diffused using the gate electrode 28 as a mask to form an N + source region 27 and an N + drain region 29. Next, an interlayer insulating film 25 is deposited, contact holes are opened on the source region 27 and the drain region 29, and then an Al alloy film deposited on the substrate is patterned by vapor deposition or sputtering to form a drain electrode 30. And the source electrode 31 is formed.
【0019】本発明の特徴であるソース電極31とP+
基板21とを電気接続する溝32と、Mo 埋め込み層3
3とについて、さらに詳しく説明する。本実施例では、
溝は、深さ数μm 、アスペクト比 2〜 3程度で、反応性
イオンエッチング(RIE)により基板の厚さ方向に形
成される。The source electrode 31 and P + which are the features of the present invention
Groove 32 for electrically connecting to substrate 21 and Mo embedded layer 3
3 will be described in more detail. In this embodiment,
The groove has a depth of several μm and an aspect ratio of about 2 to 3 and is formed in the thickness direction of the substrate by reactive ion etching (RIE).
【0020】溝を埋める導電性物質としては、Mo を使
用したが、W,Ti ,Ta 等の高融点金属またはこれら
高融点金属のシリサイド並びに不純物をドープした多結
晶シリコンを使用できる。このように融点の高い導電性
物質を埋め込み、導電性物質層として使用すれば、MO
SFET作製時に必要な高温熱処理工程にも耐えること
ができるので、MOSFETを作製する前に、埋め込み
導電性物質層を形成することが望ましい。溝部分を形成
するには、比較的厚いSi O2 膜などで溝以外の部分を
マスクする必要があるが、溝部分を先に形成し、高融点
物質で埋め込んだ後、不必要になったSi O2 膜等を全
部剥がして、半導体層表面を平坦化してからMOSFE
Tを作製すれば、その後の工程が容易にできる。Although Mo was used as the conductive material for filling the groove, refractory metals such as W, Ti and Ta, silicides of these refractory metals and polycrystalline silicon doped with impurities can be used. If a conductive material having a high melting point is embedded and used as a conductive material layer, MO
It is desirable to form the buried conductive material layer before manufacturing the MOSFET, because it can withstand the high temperature heat treatment step required when manufacturing the SFET. In order to form the groove portion, it is necessary to mask the portion other than the groove with a relatively thick SiO 2 film, but after forming the groove portion first and filling it with a high melting point substance, it became unnecessary. The surface of the semiconductor layer is flattened by completely removing the SiO 2 film, etc.
If T is manufactured, the subsequent steps can be easily performed.
【0021】図2は、本発明の半導体装置の第2実施例
の横型MOSFETの断面図である。本実施例では、異
方性エッチングによって溝32は形成され、溝の側面及
び底面にAl 等の導電性物質層43を形成したものであ
る。この実施例の溝32は、MOSFET作製前、或い
はMOSFETのドレイン及びソースのコンタクトホー
ルを開口した後で、RIE法により形成され、溝の内面
に被着する導電性物質は、前記コンタクトホールをAl
またはAl 合金で埋め込む際に同時に形成することもで
きる。なお図2において図1と同符号は同一部分または
対応部分を表わす。FIG. 2 is a sectional view of a lateral MOSFET according to a second embodiment of the semiconductor device of the present invention. In this embodiment, the groove 32 is formed by anisotropic etching, and the conductive material layer 43 of Al or the like is formed on the side surface and the bottom surface of the groove. The groove 32 of this embodiment is formed by the RIE method before the MOSFET is manufactured or after the contact holes of the drain and the source of the MOSFET are opened, and the conductive material deposited on the inner surface of the groove is Al.
Alternatively, they can be formed at the same time when they are embedded with Al alloy. In FIG. 2, the same reference numerals as those in FIG. 1 represent the same parts or corresponding parts.
【0022】図6に示す従来のMOSFETでは、拡散
層3の抵抗分がMOSFET全体のオン抵抗の10%程度
を占めるのに対し、上記実施例のようにAl 系金属を使
用したMOSFETでは、導電性物質層43の抵抗を全
体のオン抵抗の 0.01 %以下に抑えることができた。In the conventional MOSFET shown in FIG. 6, the resistance of the diffusion layer 3 occupies about 10% of the on-resistance of the entire MOSFET, whereas in the MOSFET using the Al-based metal as in the above embodiment, the conductivity is reduced. The resistance of the active substance layer 43 could be suppressed to 0.01% or less of the total on-resistance.
【0023】また溝に形成する導電性物質層32を、M
OSFETのゲート電極と同物質(不純物をドープした
多結晶シリコン、或いはMo ,W,Ti 等の高融点金属
及びこれら高融点金属のシリサイド等)で構成すれば、
ゲート電極28と導電性物質層32の形成を同一工程で
行なうことも可能である。Further, the conductive material layer 32 formed in the groove is M
If it is made of the same material as the gate electrode of the OSFET (polycrystalline silicon doped with impurities, or refractory metals such as Mo, W, and Ti and silicides of these refractory metals),
The gate electrode 28 and the conductive material layer 32 can be formed in the same step.
【0024】図3は、本発明の半導体装置の第3実施例
で、請求項2に係る装置の断面図である。符号34は溝
32の内面から拡散形成されたP+ 型(ボロンドープ)
の高不純物濃度層である。高不純物濃度層34の形成方
法は、CVD法によりボロンドープドオキサイド(BS
G)膜を溝の内面に被着し、このBSG膜を不純物源と
して、ボロンを低不純物濃度層22に熱拡散する。その
後、BSG膜を除去し、導電性物質層33を溝に充填す
る。或いは、BSG膜の代わりに、高濃度にボロンをド
ープした多結晶シリコンで溝32を埋め込み、MOSF
ET作製のための熱処理工程を利用して、不純物拡散を
行ない、高不純物濃度層34を形成し、不純物拡散源の
多結晶シリコン層をそのまま残し、導電性物質層33a
として使用する。この場合には、表面電極と基板裏面と
を接続する導電性物質層は、高不純物濃度層34と導電
性物質層33aとを並設したものとなり、特に余分の工
程を追加せずに、該導電性物質層の抵抗を下げることが
できる。FIG. 3 is a sectional view of a semiconductor device according to a second embodiment of the present invention. Reference numeral 34 is a P + type (boron-doped) diffused from the inner surface of the groove 32.
Is a high impurity concentration layer. The high-impurity concentration layer 34 is formed by a CVD method using boron-doped oxide (BS
G) A film is deposited on the inner surface of the groove, and boron is thermally diffused into the low impurity concentration layer 22 by using this BSG film as an impurity source. Then, the BSG film is removed, and the conductive material layer 33 is filled in the groove. Alternatively, instead of the BSG film, the groove 32 is filled with high-concentration boron-doped polycrystalline silicon, and the MOSF is formed.
Using the heat treatment process for ET fabrication, impurity diffusion is performed to form a high impurity concentration layer 34, leaving the polycrystalline silicon layer of the impurity diffusion source as it is, and the conductive material layer 33a.
To use as. In this case, the conductive material layer that connects the front surface electrode and the back surface of the substrate is formed by arranging the high impurity concentration layer 34 and the conductive material layer 33a in parallel, and without adding extra steps, The resistance of the conductive material layer can be reduced.
【0025】次に横型MOSFETを多数ならべた半導
体装置に、本発明を適用した第4実施例について説明す
る。図4は、該装置の電極配線パターンを示す模式的な
平面図である。同図に示すように、ドレイン電極40及
びソース電極41は、ゲート電極48を挟んで交互に並
設され、それぞれ両側に形成されるMOSFETの共通
のドレイン電極またはソース電極となっている。各電極
は、いずれか一方の端部を配線電極により連結され、櫛
状のパターンを形成している。複数のソース電極41
は、配線電極により一体化される。符号42は、この配
線電極と基板裏面とを接続する紙面に垂直方向に形成さ
れた導電性物質層であり、これにより各ソース電極は、
一度に基板裏面電位(多くの場合、接地電位)となる。Next, a fourth embodiment in which the present invention is applied to a semiconductor device having a large number of lateral MOSFETs will be described. FIG. 4 is a schematic plan view showing an electrode wiring pattern of the device. As shown in the figure, the drain electrodes 40 and the source electrodes 41 are alternately arranged side by side with the gate electrode 48 interposed therebetween, and serve as a common drain electrode or source electrode of MOSFETs formed on both sides. Each of the electrodes is connected at one end by a wiring electrode to form a comb-shaped pattern. Multiple source electrodes 41
Are integrated by the wiring electrodes. Reference numeral 42 denotes a conductive material layer formed in a direction perpendicular to the paper surface connecting the wiring electrode and the back surface of the substrate, whereby each source electrode is
The back surface potential of the substrate (in many cases, the ground potential) is obtained.
【0026】次にMOSFETの入力端に設けられる双
方向の保護ダイオードに、本発明を適用した第5の実施
例について説明する。図5(a)は、上記MOSFET
の入力端部分の断面図、同図(b)はその部分の等価回
路図である。Next, a fifth embodiment in which the present invention is applied to a bidirectional protection diode provided at the input end of the MOSFET will be described. FIG. 5A shows the above MOSFET.
Is a cross-sectional view of the input end portion of FIG. 3B, and FIG. 6B is an equivalent circuit diagram of that portion.
【0027】図5(b)において双方向の保護ダイオー
ド60は、MOSFETの入力端子T1 ,接地端子T2
と入力回路素子のMOSFET59のゲート電極G、ソ
ース電極(接地側)Sとの間に挿入され、なんらかの原
因で過電圧がT1 ,T2 間に印加されたとき、その過電
圧を吸収し、MOSFET59のゲート絶縁膜等を保護
する作用をする。保護ダイオード60の一方のアノード
電極55は入力端子T1 に、また他方のアノード電極5
6は接地端子T2 に接続されるが、接続電極配線の抵抗
やインダクタンスが大きいと、過電圧を吸収する速度が
遅れ、保護作用を損なうおそれがある。In FIG. 5B, the bidirectional protection diode 60 includes a MOSFET input terminal T 1 and a ground terminal T 2.
Is inserted between the gate electrode G and the source electrode (ground side) S of the MOSFET 59 of the input circuit element, and when an overvoltage is applied between T 1 and T 2 for some reason, the overvoltage is absorbed and the MOSFET 59 It acts to protect the gate insulating film and the like. One anode electrode 55 of the protection diode 60 is connected to the input terminal T 1 and the other anode electrode 5
6 is connected to the ground terminal T 2 , but if the resistance or the inductance of the connecting electrode wiring is large, the speed of absorbing the overvoltage may be delayed and the protective action may be impaired.
【0028】図5(a)において、P+ 基板51上に形
成されたP型層52内に、N型層53が形成され、さら
にN型層53内にP型層54が拡散形成される。P型層
54とN型層53とによりPN接合ダイオード60a
が、またN型層53とP型層52とによりNP接合ダイ
オード60bが形成され、P型層54は、双方向保護ダ
イオード60の一方のアノード電極55にオーム接触す
る。P+ 型層57は、他方のアノード領域P型層52に
連接するアノード取り出し用の高濃度層で、他方のアノ
ード電極56とオーム接触をする。本発明の特徴である
アノード電極56とP+ 基板51とを電気接続する導電
性物質層61は、Al 系金属から成り、アノード電極5
6と同体となっている。アノード電極56または導電性
物質層61はさらにチップ表面上に延在して、図示して
ないが、MOSFET59のソース電極に連結される。
すなわち双方向保護ダイオードの接地電位のアノード電
極56とMOSFET59のソース電極とを一度に導電
性物質層61により接地するものである。また本実施例
は、半導体層上に直接形成されたアノード電極56が、
この半導体層の表面から掘られた溝内の導電性物質層に
より、高不純物濃度基板に接続される例である。In FIG. 5A, an N type layer 53 is formed in a P type layer 52 formed on a P + substrate 51, and a P type layer 54 is diffused in the N type layer 53. . The P-type layer 54 and the N-type layer 53 form a PN junction diode 60a.
However, the N-type layer 53 and the P-type layer 52 form an NP junction diode 60b, and the P-type layer 54 makes ohmic contact with one anode electrode 55 of the bidirectional protection diode 60. The P + -type layer 57 is a high-concentration layer for extracting the anode that is connected to the other anode region P-type layer 52, and is in ohmic contact with the other anode electrode 56. The conductive material layer 61 that electrically connects the anode electrode 56 and the P + substrate 51, which is a feature of the present invention, is made of an Al-based metal, and the anode electrode 5
It is the same body as 6. The anode electrode 56 or the conductive material layer 61 further extends on the surface of the chip and is connected to the source electrode of the MOSFET 59 (not shown).
That is, the ground electrode anode 56 of the bidirectional protection diode and the source electrode of the MOSFET 59 are grounded at once by the conductive material layer 61. In this embodiment, the anode electrode 56 formed directly on the semiconductor layer is
This is an example of connecting to the high impurity concentration substrate by the conductive material layer in the trench dug from the surface of the semiconductor layer.
【0029】本発明は、上記第1ないし第5実施例で述
べた半導体装置に限定されない。高不純物濃度の基板上
に低不純物濃度層を有するチップを使用し、チップ表面
に形成されるMOS型、バイポーラ型等の能動素子また
はコンデンサ、抵抗等の受動素子の電極のうち、裏面の
高不純物濃度基板と同電位(例えば接地電位)で使用さ
れる電極を具備するLSI等の半導体装置に対して、本
発明は適用できる。The present invention is not limited to the semiconductor device described in the first to fifth embodiments. Using a chip with a low impurity concentration layer on a substrate with a high impurity concentration, active elements or capacitors of MOS type, bipolar type, etc. formed on the surface of the chip, electrodes of passive elements such as resistors, etc. The present invention can be applied to a semiconductor device such as an LSI provided with an electrode used at the same potential as the concentration substrate (eg, ground potential).
【0030】[0030]
【発明の効果】これまで述べたように、本発明は、高周
波用半導体装置等において、チップ表面に形成された電
極を、チップ裏面の例えば接地電極まで取り出すのに、
アスペクト比が 1より大きい溝を掘り、低抵抗の導電性
物質層を溝内に埋め込みまたは溝内面に被覆するように
した。これにより電極取り出しのためのリード用導電体
の抵抗及びインダクタンスの増加を軽減し、素子本来の
高周波特性の劣化やチップ面積の増加が少ない電極取り
だし用導電体を具備する半導体装置を提供することがで
きた。As described above, according to the present invention, in a high frequency semiconductor device or the like, an electrode formed on the front surface of a chip can be taken out to, for example, a ground electrode on the back surface of the chip.
A groove having an aspect ratio of greater than 1 was dug, and a low resistance conductive material layer was embedded in the groove or covered on the inner surface of the groove. As a result, it is possible to provide a semiconductor device provided with an electrode lead-out conductor that reduces the resistance and inductance of the lead conductor for taking out the electrode, and that does not cause deterioration of the high frequency characteristics inherent to the element or increase in the chip area. did it.
【図1】本発明の半導体装置の第1実施例の横型MOS
FETの断面図である。FIG. 1 is a lateral MOS according to a first embodiment of a semiconductor device of the present invention.
It is sectional drawing of FET.
【図2】本発明の半導体装置の第2実施例の横型MOS
FETの断面図である。FIG. 2 is a lateral MOS according to a second embodiment of the semiconductor device of the present invention.
It is sectional drawing of FET.
【図3】本発明の半導体装置の第3実施例の横型MOS
FETの断面図である。FIG. 3 is a lateral MOS according to a third embodiment of the semiconductor device of the present invention.
It is sectional drawing of FET.
【図4】本発明の半導体装置の第4実施例で、複数の横
型MOSFETを並設したときの電極配線パターンを示
す平面図である。FIG. 4 is a plan view showing an electrode wiring pattern when a plurality of lateral MOSFETs are arranged in parallel in a fourth embodiment of the semiconductor device of the present invention.
【図5】本発明の半導体装置の第5実施例のMOSFE
Tにおける、入力端に設けられる保護ダイオードの同図
(a)は断面図、同図(b)は等価回路図である。FIG. 5 is a MOSFE of a fifth embodiment of the semiconductor device of the present invention.
FIG. 11A is a sectional view of the protection diode provided at the input end at T, and FIG. 9B is an equivalent circuit diagram thereof.
【図6】従来の横型MOSFETの断面図である。FIG. 6 is a cross-sectional view of a conventional lateral MOSFET.
1,21,51 高不純物濃度の半導体
基板 2,22,52 低不純物濃度層 4,24 ゲート酸化膜 5,25,58 層間絶縁膜 7,27 ソース領域 8,28,48 ゲート電極 9,29 ドレイン領域 10,30,40 ドレイン電極 11,31,41 ソース電極 32 溝 33,33a,42,43,61 導電性物質層 34 高不純物濃度層 59 横型MOSFET 60 双方向保護ダイオー
ド1,21,51 High impurity concentration semiconductor substrate 2,22,52 Low impurity concentration layer 4,24 Gate oxide film 5,25,58 Interlayer insulating film 7,27 Source region 8,28,48 Gate electrode 9,29 Drain Region 10, 30, 40 Drain electrode 11, 31, 41 Source electrode 32 Groove 33, 33a, 42, 43, 61 Conductive material layer 34 High impurity concentration layer 59 Horizontal MOSFET 60 Bidirectional protection diode
Claims (2)
に形成された低不純物濃度の半導体層と、この半導体層
上に絶縁膜を介しまたは直接形成される電極と、前記絶
縁膜または前記半導体層の表面から前記半導体層を通り
前記半導体基板に達する幅よりも深さの大きい溝と、こ
の溝の側壁及び底面に形成され若しくは溝を埋め込んで
形成され、かつ前記電極と前記高不純物濃度の半導体基
板とを電気接続する導電性物質層とを、具備することを
特徴とする半導体装置。1. A high-impurity-concentration semiconductor substrate, a low-impurity-concentration semiconductor layer formed on this substrate, an electrode formed on or directly to the semiconductor layer via an insulating film, the insulating film or the A groove having a depth larger than a width reaching from the surface of the semiconductor layer to the semiconductor substrate through the semiconductor layer, and formed or embedded in the sidewall and bottom surface of the groove, and the electrode and the high impurity concentration. And a conductive material layer electrically connecting to the semiconductor substrate.
から拡散形成された高不純物濃度層を有することを特徴
とする請求項1記載の半導体装置。2. The semiconductor device according to claim 1, wherein the low impurity concentration semiconductor layer has a high impurity concentration layer diffused from the inner surface of the groove.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP31936692A JPH06151846A (en) | 1992-11-04 | 1992-11-04 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP31936692A JPH06151846A (en) | 1992-11-04 | 1992-11-04 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH06151846A true JPH06151846A (en) | 1994-05-31 |
Family
ID=18109354
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP31936692A Pending JPH06151846A (en) | 1992-11-04 | 1992-11-04 | Semiconductor device |
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JP (1) | JPH06151846A (en) |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1998011609A1 (en) | 1996-09-10 | 1998-03-19 | Spectrian, Inc. | Lateral dmos transistor for rf/mircrowave applications |
WO1998057379A1 (en) * | 1997-06-10 | 1998-12-17 | Spectrian | Lateral diffused mos transistor with trench source contact |
US6091449A (en) * | 1995-08-11 | 2000-07-18 | Kabushiki Kaisha Toshiba | MOS-type solid-state imaging apparatus |
JP2001308108A (en) * | 2000-04-19 | 2001-11-02 | Oki Electric Ind Co Ltd | Field effect transistor and method of manufacturing the same |
JP2003152178A (en) * | 2001-10-29 | 2003-05-23 | Power Integrations Inc | Lateral power MOSFET for high switching speed |
JP2004342810A (en) * | 2003-05-15 | 2004-12-02 | Fujitsu Ltd | Compound semiconductor device |
US6864533B2 (en) | 2000-09-11 | 2005-03-08 | Kabushiki Kaisha Toshiba | MOS field effect transistor with reduced on-resistance |
JP2008199037A (en) * | 2008-03-10 | 2008-08-28 | Renesas Technology Corp | Semiconductor device for electric power and power supply circuit |
US9059027B2 (en) | 2013-09-12 | 2015-06-16 | Kabushiki Kaisha Toshiba | Semiconductor device |
-
1992
- 1992-11-04 JP JP31936692A patent/JPH06151846A/en active Pending
Cited By (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6091449A (en) * | 1995-08-11 | 2000-07-18 | Kabushiki Kaisha Toshiba | MOS-type solid-state imaging apparatus |
US5821144A (en) * | 1996-09-10 | 1998-10-13 | Spectrian, Inc. | Lateral DMOS transistor for RF/microwave applications |
WO1998011609A1 (en) | 1996-09-10 | 1998-03-19 | Spectrian, Inc. | Lateral dmos transistor for rf/mircrowave applications |
JP2002504267A (en) * | 1997-06-10 | 2002-02-05 | スペクトリアン | Lateral diffusion MOS transistor with trench source contact |
US5869875A (en) * | 1997-06-10 | 1999-02-09 | Spectrian | Lateral diffused MOS transistor with trench source contact |
WO1998057379A1 (en) * | 1997-06-10 | 1998-12-17 | Spectrian | Lateral diffused mos transistor with trench source contact |
JP4778127B2 (en) * | 1997-06-10 | 2011-09-21 | ロベック アクイジションズ リミテッド エルエルシー | Lateral diffusion MOS transistor with trench source contact |
JP2001308108A (en) * | 2000-04-19 | 2001-11-02 | Oki Electric Ind Co Ltd | Field effect transistor and method of manufacturing the same |
US6864533B2 (en) | 2000-09-11 | 2005-03-08 | Kabushiki Kaisha Toshiba | MOS field effect transistor with reduced on-resistance |
JP2003152178A (en) * | 2001-10-29 | 2003-05-23 | Power Integrations Inc | Lateral power MOSFET for high switching speed |
JP2004297086A (en) * | 2001-10-29 | 2004-10-21 | Power Integrations Inc | Lateral power MOSFET for high switching speed |
JP2010187015A (en) * | 2001-10-29 | 2010-08-26 | Power Integrations Inc | Lateral power mosfet for high switching speed |
JP2004342810A (en) * | 2003-05-15 | 2004-12-02 | Fujitsu Ltd | Compound semiconductor device |
JP2008199037A (en) * | 2008-03-10 | 2008-08-28 | Renesas Technology Corp | Semiconductor device for electric power and power supply circuit |
US9059027B2 (en) | 2013-09-12 | 2015-06-16 | Kabushiki Kaisha Toshiba | Semiconductor device |
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